CN104685624B - 重组晶圆级微电子封装 - Google Patents

重组晶圆级微电子封装 Download PDF

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Publication number
CN104685624B
CN104685624B CN201380050994.1A CN201380050994A CN104685624B CN 104685624 B CN104685624 B CN 104685624B CN 201380050994 A CN201380050994 A CN 201380050994A CN 104685624 B CN104685624 B CN 104685624B
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microelectronic element
semiconductor die
conductive interconnection
microelectronics
microelectronics packaging
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CN104685624A (zh
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I·默罕默德
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Ying Fansasi Co
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Ying Fansasi Co
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Abstract

微电子封装（10）包括第一封装微电子元件（14）和第二封装微电子元件（16），每个都包括具有正面（20）和触点（26）的半导体裸片（14）。封装剂（28）与每个裸片的边缘表面（24）接触，并从边缘表面沿至少一个横向方向延伸。导电元件（36）从触点沿正面延伸至覆盖封装剂的位置。第一微电子元件和第二微电子元件相互固定在一起，使得第一裸片和第二裸片中的一个的正面或背面中的一个面定位为朝向第一裸片和第二裸片中的另一个的正面或背面。复数个导电互连件（40）穿过第一微电子元件和第二微电子元件的封装剂延伸，并与第一微电子元件和第二微电子元件中的至少一个半导体裸片电连接。

Description

重组晶圆级微电子封装
相关申请的交叉引用
本申请是申请号为13/563085、申请日为2012年7月31日的美国专利申请的继续申请，其公开的内容以引用的方式纳入本文。
背景技术
本申请的主题涉及微电子封装和包含微电子封装的组件。
半导体芯片一般设置为单独的、预封装的单元。标准芯片具有扁平的、长方形主体，其较大的正面上具有与芯片内部电路连接的触点。典型地，每个单独的芯片都包含在具有外部端子的封装内，外部端子再与如印刷电路板等的电路板电连接，并使芯片的触点与电路板的导体连接。在许多常规设计中，芯片封装在电路板上占据的面积比芯片自身面积大得多。在本发明中，当提到具有正面的扁平芯片时，所说的“芯片面积”应当理解为指的是正面的面积。
微电子封装可在晶圆级制造；也就是说，在芯片或裸片仍以晶圆形式时，制造封装外壳、端子及构造封装的其他特征。在晶圆内已形成裸片后，经过一系列的附加工艺步骤，以形成晶圆上的封装结构，然后切割晶圆，以释放出单个的封装裸片。晶圆级工艺可为优选的制造方法，因为其不仅可节约成本，而且由于每个裸片封装的安装位（footprint）可制成为与芯片自身的大小相同或接近相同，使将与封装裸片附接的印刷电路板上的面积可以非常有效地利用。以这种方式封装的裸片一般称为晶圆级芯片规格封装或晶圆级芯片尺寸封装（WLCSP）。
为节约安装封装裸片的基板上的附加空间，多个芯片可通过竖直堆叠而组合至单个封装内。典型地，堆叠内的每个裸片必须设置有与堆叠内其他的一个或多个裸片、或与安装堆叠的基板，或与二者都电连接的电连接机制。这样使竖直堆叠的多裸片封装占据的基板面积小于封装内所有芯片加在一起的总面积。但是，因为用于所有多个芯片的线路均沿封装的同一表面生成，这种布置需要使芯片至少有些偏离，以提供用于与上层芯片的触点电连接的通道。这样也会导致线路复杂化，且同一封装的不同芯片之间的外部连接逻辑电路需要不同路径。
根据以上所述，在多芯片微电子封装内，特别是在包括彼此之间互连或与其他封装互连的这种封装的组件内，可进行一些改进，以改善其电性能。
发明内容
本发明的一个方面涉及微电子封装。微电子封装包括第一封装微电子元件和第二封装微电子元件，每个都包括半导体裸片，半导体裸片具有沿第一横向方向和第二横向方向延伸的正面、在正面上的复数个触点、背对正面的背面、在正面与背面之间延伸的边缘表面。封装剂至少与半导体裸片的边缘表面接触，并从边缘表面沿至少一个横向方向延伸。导电元件从半导体裸片的触点延伸，并且在正面上沿至少一个横向方向延伸至覆盖封装剂的位置。第一微电子元件和第二微电子元件相互固定在一起，使得第一半导体裸片和第二半导体裸片中的一个的正面或背面中的一个面定位为朝向并邻近第一半导体裸片和第二半导体裸片中的另一个的正面或背面中的一个面。第一微电子元件和第二微电子元件的封装剂限定各自的朝外相对面（outwardly opposite surfaces）。封装进一步包括，穿过第一微电子元件和第二微电子元件的封装剂延伸的复数个导电互连件。至少一些导电互连件与第一微电子元件和第二微电子元件中的至少一个半导体裸片通过导电元件电连接。导电互连件在朝外相对面上暴露。
在一个示例中，第一微电子元件和第二微电子元件可相互固定在一起，使得第一半导体裸片和第二半导体裸片的正面彼此面对。在另一布置中，第一微电子元件和第二微电子元件可相互固定在一起，使得第二半导体裸片的正面面对第一半导体裸片的背面。在又一示例中，第一微电子元件和第二微电子元件可相互固定在一起，使得第一半导体裸片和第二半导体裸片的背面彼此面对。
至少一个微电子元件可设置为，使得封装剂的主表面与对应半导体裸片的正面共面。类似地，至少一个微电子元件可设置为，使得封装剂的第二主表面与对应半导体裸片的背面共面。
导电互连件可包括在封装剂的朝外相对面之间延伸、且与对应的导电元件相交的激光蚀刻的开口，开口至少部分地由导电金属填充。第一导电互连件可通过对应导电元件与第一半导体裸片电连接，且第二导电互连件可通过对应导电元件与第二半导体裸片电连接。在特定示例中，第一导电互连件的数量可与第二导电互连件的数量相等。此外，所有的导电互连件可都为第一导电互连件或第二导电互连件。
在一个示例中，第一半导体裸片和第二半导体裸片可为存储芯片，相对于任意其他功能的有源器件，所述存储芯片具有数量更多的、设置为提供记忆存储阵列功能（memorystorage array function）的有源器件。每个存储芯片可包括动态随机存取存储器（DRAM）存储阵列。
微电子组件可包括根据上文所述的第一微电子封装和第二微电子封装。第二微电子封装可限定具有暴露于其上的端子的第一表面和具有暴露于其上的封装触点的第二表面。第二微电子封装可进一步包括位于第一表面与第二表面之间、且与端子和封装触点电连接的微电子元件。复数个导电接合元件可在第一微电子封装的导电互连件的相对端部与第二微电子封装的端子之间接合。
第二封装的微电子元件可为逻辑芯片，相对于任意其他功能的有源器件，所述逻辑芯片具有数量更多的、设置为提供逻辑功能的有源器件。第二微电子封装可进一步包括基板，基板上安装微电子元件。基板可包括在微电子元件与端子之间电连接的导电元件。
第二封装的端子可为键合引线的端部，键合引线具有与对应导电元件接合的基底。在这种示例中，第二微电子封装可进一步包括形成在基板表面及微电子元件的至少一部分上的封装剂层。封装剂层可进一步沿键合引线的边缘表面延伸，并可使键合引线分隔开。封装剂层可限定第二封装的第一表面，且键合引线的端面可不被第二表面上的封装剂层覆盖。
在一个示例中，第一导电互连件可通过对应导电元件而与第一微电子元件电连接，第二导电互连件可通过对应导电元件而与第二微电子元件电连接，第三导电互连件可与第一微电子元件或第二微电子元件都不连接。第一微电子封装可进一步包括覆盖第一微电子封装的第三微电子封装，第三微电子封装具有与暴露在封装剂第一表面上的第三导电元件的端部接合的封装触点。
在一示例性的构造中，第二微电子封装可包括限定第二封装第一表面的基板，且基板具有背对第一表面的第三表面，微电子元件安装在第三表面上。
系统可包括，上述微电子组件和一个或多个电子元器件。
本发明的另一方面涉及包括第一封装微电子元件和第二封装微电子元件的微电子封装。每个微电子元件都包括半导体裸片，半导体裸片具有沿第一横向方向和第二横向方向延伸的正面、在正面上的复数个触点、背对正面的背面及在正面与背面之间延伸的边缘表面。每个微电子元件进一步具有至少与对应半导体裸片的边缘表面接触的封装剂，并从边缘表面沿至少一个横向方向延伸，从而限定与半导体裸片的正面共面或平行的主表面，且导电元件包括从半导体裸片的触点沿正面延伸的金属化通路。至少一些导电元件越过边缘表面延伸至覆盖封装剂主表面的位置。第一微电子元件和第二微电子元件可相互固定在一起，使得其正面彼此面对，且主表面也彼此面对。封装进一步包括穿过第一微电子元件和第二微电子元件的封装剂沿远离主表面的方向延伸的复数个导电互连件。至少一些导电互连件通过导电元件而与第一微电子元件和第二微电子元件中的至少一个半导体裸片电连接。导电互连件在封装剂的背对主表面的第一相对表面和第二相对表面暴露。
本发明另一方面涉及制造微电子封装的方法。该方法包括形成穿过第一封装微电子元件和第二封装微电子元件的复数个导电互连件。每个微电子元件都包括半导体裸片，半导体裸片具有沿第一横向方向和第二横向方向延伸的正面、在正面上的复数个触点、背对正面的背面、及在正面与背面之间延伸的边缘表面。封装剂至少与对应半导体裸片的边缘表面接触，并沿至少一个横向方向从边缘表面延伸。导电元件从半导体裸片的触点沿至少一个横向方向延伸至覆盖封装剂的位置。第一微电子元件和第二微电子元件相互固定在一起，使得第一半导体裸片和第二半导体裸片中的一个的正面或背面中的一个面定向为朝向并邻近第一半导体裸片和第二半导体裸片中的另一个的正面或背面中的一个面。第一微电子元件和第二微电子元件的封装剂限定各自的朝外相对面。导电互连件穿过第一微电子元件和第二微电子元件的封装剂而形成，使得至少一些导电互连件通过导电元件与第一微电子元件和第二微电子元件中的至少一个半导体裸片电连接。导电互连件在朝外相对面暴露。
导电互连件可通过激光蚀刻开口穿过第一微电子元件和第二微电子元件的封装剂而形成，并穿过相应的导电元件，并至少部分地用导电金属填充开口。
在一个示例中，方法可进一步包括使第一微电子元件和第二微电子元件相互固定，使得其正面彼此面对。在另一示例中，方法可进一步包括使第一微电子元件和第二微电子元件相互固定，使得第二微电子元件的正面面对第一微电子元件的背面。在又一示例中，方法可进一步包括使第一微电子元件和第二微电子元件相互固定，使得其背面彼此面对。
导电互连件可形成为，包括通过对应导电元件与第一微电子元件连接的第一导电互连件、及通过对应导电元件与第二微电子元件连接的第二导电互连件。封装内形成的第一导电互连件的数量可与封装内形成的第二导电通路的数量相等。导电互连件可进一步形成为，包括与封装内的其他电连接脱离的第三导电互连件。
方法可进一步包括，形成沿覆盖半导体裸片的对应正面和封装剂的第一主表面的介电区域延伸的导电元件。导电元件的形成可包括，在把微电子元件固定在一起之前，在第一微电子元件或第二微电子元件中的至少一个上形成导电元件。附加地或替代地，导电元件的形成可包括，在微电子元件固定在一起之前，在覆盖第一微电子元件或第二微电子元件中至少一个的介电区域上形成导电元件。
本发明的另一方面涉及制造微电子组件的方法。该方法包括，通过包括形成穿过第一封装微电子元件和第二封装微电子元件的复数个导电互连件的步骤，形成第一微电子封装。每个微电子元件都包括半导体裸片，半导体裸片具有沿第一横向方向和第二横向方向延伸的正面、在正面上的复数个触点、背对正面的背面、及在正面与背面之间延伸的边缘表面。封装剂至少与对应半导体裸片的边缘表面接触，并沿至少一个横向方向从边缘表面延伸。导电元件包括，从半导体裸片的触点沿至少一个横向方向延伸至覆盖封装剂的位置的金属化通路。第一微电子元件与第二微电子元件相互固定，使得第一半导体裸片和第二半导体裸片中一个的正面或背面中的一个面定向为朝向并邻近第一半导体裸片和第二半导体裸片中另一个的正面或背面中的一个面。第一微电子元件和第二微电子元件的封装剂限定对应的朝外相对面。导电互连件穿过第一微电子元件和第二微电子元件的封装剂而形成，使得至少一些导电互连件通过导电元件而与第一微电子元件和第二微电子元件中的至少一个半导体裸片电连接。导电互连件在朝外相对面暴露。方法进一步包括把第一微电子封装设置在包括逻辑芯片的第二微电子封装上，逻辑芯片与第二封装的第一表面上暴露的端子及第二微电子封装的第二表面上暴露的封装触点电连接。方法进一步包括，采用复数个导电接合元件，使第一微电子封装的面向第二微电子封装的导电互连件的端部与第二微电子封装的端子接合。
方法可进一步包括，把第三微电子封装设置在第一微电子封装上，第三微电子封装包括在其设置为面对第一封装的表面上暴露的端子。在这种示例中，方法可进一步包括，使第三微电子封装的端子与设置为朝向第三微电子封装的导电互连件的端部接合。
导电互连件可形成为，包括通过对应导电元件与第一微电子元件连接的第一导电互连件、通过对应导电元件与第二微电子元件连接的第二导电互连件、及与封装内其他电连接脱离的第三导电互连件。第三微电子封装的端子可与第三导电互连件的端部接合，第三导电互连件使第三封装与第二封装电连接。
附图说明
下面将参照附图描述本发明的各实施例。可以理解的是，这些附图仅是为了说明本发明的一些实施例，因此不可视为其限制本发明的范围。
图1示出了根据本发明一个实施例的微电子组件。
图1A示出了图1中组件包含的微电子封装的局部放大视图。
图2示出了图1所示封装的俯视图。
图3示出了图1所示封装的仰视图。
图4示出了根据本发明另一实施例的微电子组件。
图5示出了根据本发明另一实施例的微电子组件。
图6至图10示出了制造根据本发明另一实施例微电子元件的方法步骤中逐次加工的过程中单元。
图11示出了根据本发明另一实施例的微电子组件。
图12示出了根据本发明另一实施例的微电子组件。
图13示出了可包括根据本发明各实施例微电子组件的系统。
具体实施方式
现在参见附图，其中类似的标号用于指示类似的特征，图1所示的微电子组件10为第一微电子封装12堆叠在第二微电子封装50上的形式。在一个示例中，组件10可为逻辑搭载存储器（memory-on-logic）组件的形式，其中第一封装12为存储封装，而第二封装50为逻辑封装，但本文描述的布置可在不同类型的封装或不同类型的组合的布置中应用。第一封装12和第二封装50都包括一个或多个对应的半导体裸片18，裸片自身包括复数个有源器件。存储封装可为半导体裸片的封装，其中半导体裸片所具有的有源器件中大多数设置为用于记忆存储阵列功能(memory storage array function)。类似地，逻辑封装可为其内大多数有源器件设置为执行处理器功能（execute processor functions）的封装。
第一微电子封装12可包括第一封装微电子元件14和第二封装微电子元件16。每个封装的微电子元件14、16都包括半导体裸片18。如上所述，这些半导体裸片18可为存储芯片的形式，如DRAM芯片或类似的芯片。在其他示例中，半导体裸片18可为专用集成电路（ASIC）芯片的形式。封装12内可存在ASIC芯片与存储芯片的各种组合。半导体裸片18进一步包括沿横向方向延伸的正面20，且正面上暴露有元件触点26。背面22背对正面设置，且总体上与其平行。边缘表面24在正面20与背面22之间延伸，并限定裸片18的外周面。
封装剂28至少部分地围绕半导体裸片18。封装剂可由介电材料制成，且可模制或采用其他方法至少部分围绕裸片18而形成。封装剂28可与裸片18的一个或多个边缘表面24接触，且可从其沿垂直于边缘表面24的一个或多个横向方向向外延伸。在一个示例中，正面20和背面22可为长方形或正方形，且四个对应边缘表面24可在正面20与背面22的对应侧边之间延伸。封装剂28可围绕所有四个边缘表面24，且可从其向外延伸，以使微电子元件14或16具有长方体的形状。封装剂28包括，分别与半导体裸片18的正面20和背面22相关联并平行的第一主表面30和第二主表面32。在一些示例中，封装剂28可进一步与背面22接触，并从其向外延伸，使得第二主表面32覆盖背面22。在其他实施例中，如图1所示，正面20和背面22可不被封装剂28覆盖，使得第一表面30与正面20基本共面地延伸，和/或第二主表面32与背面22基本共面地延伸。
每个微电子元件14、16可进一步都包括，至少覆盖半导体裸片18正面20的介电区域48。如图1A中所见，介电区域48可延伸越过半导体裸片18的边缘表面24以覆盖封装剂28的第一主表面30。介电区域48可部分地或全部由任意适当的介电材料制成。例如，介电区域48可包括柔性材料层，如聚酰亚胺、BT树脂或一般用于制造带式自动结合（“TAB”）的带的其他介电材料层。替代地，介电区域48可包括相对硬质的板状材料，如纤维强化环氧树脂的厚层，如Fr-4或Fr-5板。无论采用何种材料，介电区域48都可包括单层或多层的介电材料。
如图1A的局部放大图所示，导电元件可与半导体裸片18的触点26连接。特别地，导电通路38可延伸穿过介电区域48，以与半导体裸片18的触点26连接。如迹线36等的附加导电特征可与导电通路38连接，并可沿一个或多个横向方向从导电通路38沿正面20上的介电区域48向外延伸，且可进一步在封装剂28的第一主表面30上延伸，以与一个或多个触点26连接，触点26可沿第一主表面30设置在各种位置。这种导电元件可由如铜、金、银、镍、铝等的导电金属或其各种合金制成。
进一步如图1A所示，第一微电子元件14和第二微电子元件16可组装在一起，使得对应半导体裸片18的正面20相互面对。在这种布置中，各封装剂28的第一主表面30也可同时相互面对。微电子元件可通过结合层44而接合在一起，结合层可为粘接剂、模制介电材料或可在微电子元件14、16的介电区域48之间结合的类似物质。结合层44可进一步设置为，围绕并分隔开如迹线36和垫34等的导电元件。在所示的示例中，结合层44把微电子元件14和16分隔开，使得迹线36的布线模式（routing patterns）彼此之间互不干涉。在其他示例中，第一微电子元件14和第二微电子元件16的各自的布线模式可构造成沿横向彼此分隔开，使微电子元件14和16可靠得更近。
导电互连件40可贯穿第一微电子元件14及第二微电子元件16的封装剂28延伸，使得导电互连件40的端面46A可在第一微电子元件14的封装剂28的第二主表面32上暴露，且相对的另一端面46B在第二微电子元件16的封装剂28的第二主表面32上暴露。导电互连件40还可贯穿与微电子元件14、16中的任一个相关联的相应导电元件而延伸，并与其连接。在图1A的示例中，导电元件40A可与迹线36端部的垫34连接，该迹线36沿主表面30和微电子元件14的正面20延伸，并与微电子元件14的半导体裸片18的对应触点连接。类似地，导电元件40B与另一迹线36端部的垫34连接，该迹线36沿主表面30和微电子元件16的正面20延伸，并与微电子元件16的半导体裸片18的对应触点连接。通过如此布置，可在微电子元件14、16的第二主表面32与任一半导体裸片18之间生成一定数量的连接。例如，通过在微电子元件16的第二主表面32上暴露的导电互连件40的端面46B，这样可允许两个微电子元件14、16的半导体裸片18之间的连接，或反之亦然。导电互连件可为通过在开口内电镀导电金属而形成的金属化通路，所述开口可贯穿封装剂并穿过位于封装剂之间的导电元件的部分，并通过蚀刻、钻孔或类似方法而形成，如下文进一步详述。用于互连件40的导电金属可包括铜、金、银、镍、铝或其各种合金。
导电互连件40可在封装剂28内以任意结构或模式布置。在图2所示的示例中，导电互连件40以面阵模式布置，其中互连件40以多行和多列的栅格模式排列在封装剂28内并围绕半导体裸片18。这种阵列内的互连件40可依照阵列的间距而彼此分隔开，例如，间距可小于500微米，而在另一示例中可在250微米与300微米之间。例如，上述阵列可设置为与第二封装50的端子58的阵列对齐，以通过使端子58与互连件40的端面46B接合而生成封装间的特定电连接。这样可允许在如微电子元件52与第一封装12内的两微电子元件14、16的半导体裸片18之间的连接。
各微电子元件14、16的导电元件可布置为，使得一个半导体裸片18上的仅一个触点26与对应导电互连件40连接。例如，各微电子元件14、16的垫34可以按照不同阵列或其他模式布置，每个垫34部分地对应于导电互连件40的阵列。在微电子元件14、16之间，这种部分对应模式可以不同，使得与微电子元件14相关联的垫34都不占据与微电子元件16相关联的垫34的位置，且反之亦然。这种差异模式可具有无数的布置。在一个示例中，微电子元件16的所有垫34都可设置在微电子元件14的垫34的阵列的内部。在另一示例中，替代地，微电子元件14的垫34可位于微电子元件16的垫34的阵列的内部，而另外的布置也是可能的。迹线36可布置为，使得除了与单个垫34及相应半导体裸片18上的单个触点26接触以外，迹线36不与封装12内的任何特征接触。
如之前提到的，导电互连件40可设置为与第二封装50的端子58连接，在一个示例中，第二封装50可为逻辑封装。如图1所示，第二封装50可为微电子元件52承载在基板54上的形式，在覆盖基板的封装剂的表面上具有端子58。端子58可为从导电元件延伸的互连件56的端面，导电元件沿基板54的表面延伸，以与微电子元件52连接，例如通过导电块70而连接。互连件可为众多设置方式中的任意形式，且可包括导电引脚或柱。在另一示例中，互连件56可为键合引线的方式，如授予Otremba、专利号为7391121的美国专利、公开号为2005/0095835的美国专利申请（描述了可认为是键合引线的形式的楔形键合工艺）、及共同转让的申请号分别为13/462158、13/404408、13/405108、13/405125、13/404458的美国专利申请中所述，这些文献公开的内容以全文的方式因引用而纳入本文。基板54可包括再分布层，以使背对端子58在基板54上的暴露的封装触点与微电子元件52连接，以在微电子系统内生成组件10与其他微电子器件之间的连接。在一个实施例中，封装触点60可通过导电接合块而与电路板或类似物（未示出）上的端子连接。这种封装触点60可以图3所示的模式或阵列布置，且可作为组件10的输入和输出连接。
如图4所示，附加封装12B可在封装12A顶上堆叠。封装12B可与封装12A的构造类似，而封装12A自身与参照图1至图3在上文所述的封装12类似。在这种示例中，封装12A可设置为方便封装12B与封装50之间的电连接。为实现此目的，封装12A内的一些导电互连件40可不与封装12A内的任一个半导体裸片18连接。进一步地，这种互连件40可不与任何导电元件，如封装12A内的垫34或迹线36等连接。封装12A内的这些未连接的互连件40可与封装12B内的导电互连件40连接，通过与参照图1A的封装12在上文所述的类似的方式，封装12B内的导电互连件40自身可与封装12B内的半导体裸片18连接。在另一示例中，封装12B内的一些导电互连件40可不与封装12B内的任一半导体裸片18连接，且可与封装12A内的未连接互连件40一起，可方便封装50与堆叠在封装12B顶部的又一封装（未示出）之间的电连接。在这种堆叠布置中，最上层的封装可与封装12A或12B类似，如图4所示，或可为封装微电子元件（或多个微电子元件）的另一形式，具有至少在面对其下方的封装的导电互连件40的表面上暴露的触点。
图5示出的组件110为图1中组件的变例。特别地，组件110包括与图1至图3所示封装12结构类似的第一封装112。组件110进一步包括与图1至图4所示封装50类似的第二封装150，不同在于第二封装150设置为互连件156的端部160远离封装112并作为用于使组件110与如电路板或类似物等的外部元器件连接的触点。相应地，基板154上背对微电子元件152的触点用作端子158，采用导电接合块170或类似物将封装112的导电互连件140的端面146B与端子160连接。在这种布置中，互连件156可为如上所述的封装键合引线的方式，以获得作为互连件156端部160的、具有较小间距的触点。可设置穿过基板154（或其上的层）、用于构造所需的端子158的再分布层，以与导电互连件140连接。另一封装（未示出）可以参照图4在上文所述的类似方式包含在组件110内。
图6至图10示出了在根据本发明实施例制造组件10方法的步骤中的各元器件。特别地，图6示出了组装在一起之前的第一微电子元件14和第二微电子元件16。微电子元件14、16可形成为重组晶圆级封装（reconstituted wafer-level packages）。也就是说，其可形成在具有嵌入封装剂层内的复数个半导体裸片的晶圆内。然后该晶圆可切割或分离成单独的微电子元件，例如，微电子元件包括单个半导体裸片和一部分封装剂，封装剂至少部分地围绕半导体裸片。用于制造特定封装的其他工艺步骤可包括，研磨封装剂的一个或多个表面，以生成与半导体裸片18的正面20和背面22平齐的主表面30、32，在这种研磨过程中半导体裸片自身也可变薄。在分离前或后，包括垫34、迹线36和导电通路38等的导电元件可根据上述原理沿半导体裸片18的正面20和封装剂28的第一主表面30而形成。根据需要，可形成在第一主表面30及正面20上未被导电元件覆盖的部分上的附加介电层。
然后如图6所示，微电子元件14、16可以按照正面20与第一主表面30彼此面对的方式放置，且微电子元件的各导电元件相对于彼此适当放置，如上文所述。然后，通过粘接剂或位于微电子元件14、16之间的可固化的介电材料层，微电子元件14、16可结合在一起。在一些实施例中，当微电子元件14、16移动至一起时，这种层可在导电元件之间散布。这种结合可生成图7所示的过程中封装（in-process package）12＇。
然后可处理图7的过程中单元，以形成贯穿第一微电子元件14和第二微电子元件16的封装剂28、并贯穿与其关联的导电元件的所需部分的开口。在一个示例中，其中当微电子元件14、16组装在一起时，与微电子元件14、16相关联的垫34布置为阵列，开口42可形成为贯穿垫34及覆盖垫34的封装剂28区域的一部分。在所示的示例中，开口42可完全贯穿过程中单元12而延伸，使得其在微电子元件14、16的第二主表面32上都开放。在其他实施例中，如当所要制造的封装预定作为堆叠内的最上层封装时，开口可从单个第二主表面32延伸至适合于贯穿垫34延伸的深度。开口42可通过钻孔、蚀刻或类似方式而制成。蚀刻可利用化学蚀刻剂或类似物及至少临时覆盖在第二主表面32上的掩模层而进行。在另一示例中，开口42可通过激光蚀刻而形成。激光蚀刻可为优选的，因为其可利用能定位及靶定过程中封装12＇位置的、特别配置的设备，以检测到垫34而形成开口42。
然后可在开口42内填充，如铜或上述的其他金属等的导电金属，以形成导电互连件40。这可通过在孔内镀导电金属而完成。这种镀层可采用电镀或化学镀（electrolessplating）工艺进行，且可在开口42内沉积籽晶层或类似物后进行。当采用这种籽晶层时，籽晶层可导电，以允许导电互连件40与垫34或其他导电元件之间的电连接。在一些实施例中，导电互连件40的端面46A、46B可通过研磨或类似工艺而平面化，使得其基本与第二主表面32平齐。在其他示例中，触点可在互连件40的端面46A、46B上形成，以提供与其他元器件连接的附加区域。
如图10所示，封装12接下来与封装50对齐，使得导电互连件40、尤其是其端面46B与封装50的所需端子58对齐。在一个示例中，封装50可形成为包括封装键合引线互连的封装，通过上文参考的共同转让的申请号分别为13/462158、13/404408、13/405108、13/405125及13/404458的美国专利申请中所描述的任意方法而形成。然后利用如焊料球或类似物等的导电接合块70，互连件40的端面46B与相应端子58接合，以形成如图1所示的封装。还可进行附加步骤，包括形成与封装12类似、可进一步组装在封装12上的附加封装，且该附加封装的导电互连件与封装12的某些导电互连件40连接，如参照图4在上文所述。
图11示出了微电子组件，包括封装212，其与另一微电子封装250组装在一起，其中封装250可与参照图1所描述的封装50类似。封装212可为图1所示封装12的变例，二者具有许多共同特征。特别地，封装212可包括第一微电子元件214和第二微电子元件216，每个都包括半导体裸片218，并具有至少部分地围绕半导体裸片218的封装剂228。每个微电子元件214、216都包括各自的导电元件，导电元件包括：与各自半导体裸片218的触点226连接的导电通路、和沿正面220及第一主表面230延伸至垫的迹线236。在图11所示实施例中，第一微电子元件214和第二微电子元件216可组装在一起，使得微电子元件214的第一主表面230面对微电子元件216的第二主表面232。此外，在这种布置中，第一微电子元件214的半导体裸片218的正面220面对第二微电子元件216的半导体裸片218的背面222。
在图11的布置中，导电元件的位置，尤其是各微电子元件214、216的垫的位置，可以如图1至图4中微电子封装12的垫的类似的方式来确定。特别地，所述垫可设置为，使得每个导电互连件240仅穿过微电子元件214或216中一个的仅一个垫。同样，如图1至图4的封装12，一些导电互连件240可不与封装212内的任一个半导体裸片218电连接，且可用于使堆叠在封装212顶上的另一封装（未示出）与封装250的端子258连接。
制造如图11所示组件的方法也可与图6至图10所描述的组件10的制造方法类似，但不同在于，当组装在一起时，微电子元件214、216放置为如上所述的背对正布置。此外，第二微电子元件216的导电元件可在与第一微电子元件214组装后形成。
图12示出了另一变例的微电子组件310，包括封装312，与另一微电子封装350组装在一起，其中封装350可与参照图1所描述的封装50类似。封装312可为图1所示封装12的变例，二者具有许多共同特征。特别地，封装312包括第一微电子元件314和第二微电子元件316，都包括半导体裸片318，且具有至少部分地围绕半导体裸片318的封装剂328。每个微电子元件314、316可都包括各自的导电元件，导电元件包括：与各自半导体裸片318的触点326连接的导电通路、和沿正面320及第一主表面330延伸至垫的迹线336。图12所示实施例中，第一微电子元件314和第二微电子元件316可组装在一起，使得微电子元件314、316的第二主表面332相互面对。此外，在这种布置中，第一微电子元件314和第二微电子元件316的半导体裸片318的背面322可相互面对。
在图12的布置中，导电元件的位置，尤其是各微电子封装314、316的垫的位置，可以如图1至图4中微电子封装12的垫的类似的方式来确定。特别地，所述垫可设置为，使得每个导电互连件340仅穿过微电子元件314或316中一个的仅一个垫。同样，如同图1至图4所示的封装12，一些导电互连件340可不与封装312内的任一个半导体裸片318电连接，且可用于使堆叠在封装312顶上的另一封装（未示出）与封装350的端子358连接。在图12所示封装312的一些变例中，第二微电子元件316的导电垫在封装312上暴露，且面对封装350的端子358，因此，所述垫可与端子358通过焊料球370或类似物而直接连接。相应地，这种垫可无需任何导电互连件340与其相关联。在这种示例中，导电互连件340可与第一微电子元件314的垫连接，且还可在封装312内为非连接状态，用于与封装312上方组装的附加封装（未示出）连接。
制造组件310的方法也可与图6至图10所描述的组件10的制造方法类似，但不同在于，当组装在一起时，微电子元件314、316放置为如上所述的背对背布置。此外，第一微电子元件314和第二微电子元件316的导电元件可在组装在一起后形成。
上述的结构可在各种电子系统的构造中应用。例如，根据本发明另一实施例的系统1包括与其他电子元器件2和3联接的、如参照图1至图4在上文所述的微电子组件10。在所描述的示例中，元器件2为半导体芯片而元器件3为显示屏，但任意其他元器件都可使用。当然，尽管为了图示清楚起见，图13中只示出了两个附加元器件，系统可包括任意数量的这种元器件。如上所述，微电子组件10可为例如与图1相关联在上文所述的微电子封装，或参照图4在上文所述的包含多个微电子封装的结构。组件10可进一步包括图11或图12所描述的任意一个实施例。在另一变例中，可提供多种变化，且可采用任意数量的这种结构。
微电子组件10和元器件2、3，被安装在图中以虚线示意性地描述的共同的外壳4内，且当需要时可彼此之间电互连，以形成所需电路。在所示的示例性系统中，该系统包括如柔性印刷电路板等的电路板5，且该电路板包括大量的使元器件之间彼此电互连的导电体6，但在图13中只示出了一个。然而，这仅是为了示例的目的，用于形成电连接的任意适当结构都可使用。
图示的外壳4为便携式类型的外壳，例如用于移动电话或个人数字助理，显示屏3暴露在外壳表面。其中微电子组件10包括如成像芯片等的光敏元件，还可配置镜头7或其他光学器件，以将光传送至结构。同样，图13内所示的简化系统只是示例，其他系统，包括一般视为固定结构的系统，如台式计算机、路由器及类似的结构，都可应用上述的结构而制成。
尽管本发明参照特定实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下，说明的实施例可做出许多修改及可设计出其他布置。
工业实用性
本申请的主题涉及微电子封装和包含微电子封装的组件。

Claims (40)

1.微电子组件，包括：
第一微电子封装，其中所述第一微电子封装包括封装的第一微电子元件和第二微电子元件，每个都包括：
半导体裸片，具有沿第一横向方向和第二横向方向延伸的正面、在所述正面上的复数个触点、背对所述正面的背面、在所述正面与所述背面之间延伸的边缘表面；
封装剂，至少与所述半导体裸片的边缘表面接触，并从所述边缘表面沿至少一个所述横向方向延伸；及
导电元件，从所述半导体裸片的触点延伸，并且在所述正面上沿至少一个所述横向方向延伸至覆盖所述封装剂的位置；
其中所述第一微电子元件和所述第二微电子元件通过接合区域相互固定在一起，所述接合区域在所述第一微电子元件和第二微电子元件的相对表面之间延伸，使得第一半导体裸片和第二半导体裸片中的一个的正面或背面中的一个面定位为朝向并邻近所述第一半导体裸片和第二半导体裸片中的另一个的正面或背面中的一个面，并且至少一个所述微电子元件中的至少一些导电元件邻近所述接合区域，所述第一微电子元件和所述第二微电子元件的封装剂分别限定了远离所述接合区域且相互背对的第一朝外表面和第二朝外表面；及
复数个导电互连件，每个导电互连件延伸穿过具有连续内表面的开口，所述连续内表面从所述第一朝外表面延伸穿过所述第一微电子元件的封装剂，并穿过所述接合区域和所述第二微电子元件的封装剂而延伸至所述第二朝外表面，其中一个所述导电互连件仅与一个所述导电元件在邻近所述接合区域的位置电连接，从而仅与所述第一微电子元件和所述第二微电子元件中的一个所述半导体裸片电连接；
第二微电子封装，其限定了暴露端子的第一表面和暴露封装触点的第二表面，所述第二微电子封装还包括与所述端子和所述封装触点电连接的微电子元件;和
复数个导电接合元件，与所述第一微电子封装的导电互连件的面对端部和所述第二微电子封装的所述端子电连接，
其中，与所述导电接合元件中的第一导电接合元件接合的所述导电互连件中的第一导电互连件与所述第一微电子元件或第二微电子元件都没有形成电连接。
2.根据权利要求1所述的微电子组件，其中所述第一微电子封装的所述第一微电子元件和所述第二微电子元件相互固定在一起，使得所述第一半导体裸片和所述第二半导体裸片的正面彼此面对。
3.根据权利要求1所述的微电子组件，其中所述第一微电子封装的所述第一微电子元件和所述第二微电子元件相互固定在一起，使得所述第二半导体裸片的正面面对所述第一半导体裸片的背面。
4.根据权利要求1所述的微电子组件，其中所述第一微电子封装的所述第一微电子元件和所述第二微电子元件相互固定在一起，使得所述第一半导体裸片和所述第二半导体裸片的背面彼此面对。
5.根据权利要求1所述的微电子组件，其中所述第一微电子封装的至少一个微电子元件设置为，使得所述封装剂的第一主表面与对应半导体裸片的所述正面共面。
6.根据权利要求1所述的微电子组件，其中所述第一微电子封装的至少一个微电子元件设置为，使得所述封装剂的第二主表面与对应半导体裸片的所述背面共面。
7.根据权利要求1所述的微电子组件，其中所述开口包括在所述封装剂的朝外相对面之间延伸且与对应的导电元件相交的激光蚀刻的开口，所述开口至少部分地由导电金属填充。
8.根据权利要求1所述的微电子组件，其中第一导电互连件通过对应导电元件与所述第一半导体裸片电连接，且第二导电互连件通过对应导电元件与所述第二半导体裸片电连接。
9.根据权利要求8所述的微电子组件，其中所述第一导电互连件的数量与第二导电互连件的数量相等。
10.根据权利要求8所述的微电子组件，其中所有的导电互连件都为第一导电互连件或第二导电互连件。
11.根据权利要求1所述的微电子组件，其中所述第一半导体裸片和所述第二半导体裸片为存储芯片，相对于任意其他功能的有源器件，所述存储芯片具有数量更多的、设置为提供记忆存储阵列功能的有源器件。
12.根据权利要求11所述的微电子组件，其中每个存储芯片包括动态随机存取存储器（“DRAM”）存储阵列。
13.根据权利要求1所述的微电子组件，其中所述第二微电子封装的微电子元件为逻辑芯片，相对于任意其他功能的有源器件，所述逻辑芯片具有数量更多的、设置为提供逻辑功能的有源器件。
14.根据权利要求1所述的微电子组件，其中所述第二微电子封装进一步包括安装所述第二微电子封装的所述微电子元件的基板，所述基板包括在这样的微电子元件与所述端子之间电连接的导电元件。
15.根据权利要求14所述的微电子组件，其中所述端子为键合引线的端部，所述键合引线具有与对应导电元件接合的基底。
16.根据权利要求15所述的微电子组件，其中所述第二微电子封装进一步包括形成在所述基板的表面及所述第二微电子封装的所述微电子元件的至少一部分上的封装剂层，所述封装剂层进一步沿所述键合引线的边缘表面延伸，且使所述键合引线分隔开，所述封装剂层限定所述第二微电子封装的第一表面，且所述键合引线的端面不被所述第二微电子封装的所述第二表面上的封装剂层覆盖。
17.根据权利要求1所述的微电子组件，其中所述第二微电子封装进一步包括基板，所述基板限定所述第二微电子封装的第一表面且具有背对所述第一表面的第三表面，所述第二微电子封装的所述微电子元件安装在所述第三表面上。
18.根据权利要求1所述的微电子组件，其中第二导电互连件通过所述导电元件当中相应的第二导电元件与所述第一微电子元件电连接，其中第三导电互连件通过所述导电元件当中相应的第三导电元件与所述第二微电子元件电连接。
19.根据权利要求18所述的微电子组件，进一步包括覆盖所述第一微电子封装的第三微电子封装，所述第三微电子封装具有与所述导电互连件中的导电互连件的端部接合的封装触点。
20.系统，包括：如权利要求1所述的微电子组件和一个或多个电子元器件。
21.微电子组件，包括：
第一微电子封装，其中所述第一微电子封装包括：
封装的第一微电子元件和第二微电子元件，每个微电子元件都包括半导体裸片，所述半导体裸片具有沿第一横向方向和第二横向方向延伸的正面、在所述正面上的复数个触点、背对所述正面的背面、在所述正面与所述背面之间延伸的边缘表面，每个微电子元件具有：
封装剂，至少与对应的半导体裸片的所述边缘表面接触，并从所述边缘表面沿至少一个横向方向延伸，从而限定与所述半导体裸片的正面共面或平行的主表面，及
导电元件，包括从所述半导体裸片的触点沿所述正面延伸的金属化通路，至少一些导电元件越过所述边缘表面延伸至覆盖所述封装剂的主表面的位置，
其中所述第一微电子元件和所述第二微电子元件通过接合区域相互固定在一起，所述接合区域在所述第一微电子元件和第二微电子元件的相对表面之间延伸，使得所述正面彼此面对，且所述主表面也彼此面对，并且至少一个所述微电子元件中的至少一些导电元件邻近所述接合区域，所述第一微电子元件和所述第二微电子元件的封装剂分别限定了远离所述接合区域且相互背对的第一朝外表面和第二朝外表面；及
复数个导电互连件，每个导电互连件延伸穿过具有连续内表面的开口，所述连续内表面从所述第一朝外表面延伸穿过所述第一微电子元件的封装剂，并穿过所述接合区域和所述第二微电子元件的封装剂而延伸至所述第二朝外表面，其中一个所述导电互连件仅与一个所述导电元件在邻近所述接合区域的位置电连接，从而仅与所述第一微电子元件和所述第二微电子元件中的一个所述半导体裸片电连接；
第二微电子封装，其限定了暴露端子的第一表面和暴露封装触点的第二表面，所述第二微电子封装还包括设置在所述第一表面与第二表面之间并与所述端子和所述封装触点电连接的微电子元件;和
复数个导电接合元件，在所述第一微电子封装的导电互连件的面对端部与所述第二微电子封装的所述端子之间接合，
其中，与所述导电接合元件中的第一导电接合元件接合的所述导电互连件中的第一导电互连件与所述第一微电子元件或第二微电子元件都没有形成电连接。
22.制造微电子封装的方法，包括：
形成穿过封装的第一微电子元件和第二微电子元件的复数个导电互连件，每个微电子元件都包括：
半导体裸片，具有沿第一横向方向和第二横向方向延伸的正面、在所述正面上的复数个触点、背对所述正面的背面、在所述正面与所述背面之间延伸的边缘表面；
封装剂，至少与对应的半导体裸片的边缘表面接触，并沿至少一个横向方向从所述边缘表面延伸；及
导电元件，从所述半导体裸片的触点沿至少一个横向方向延伸至覆盖所述封装剂的位置；
其中所述第一微电子元件和所述第二微电子元件相互固定在一起，使得第一半导体裸片和第二半导体裸片中的一个的正面或背面中的一个面定向为朝向并邻近所述第一半导体裸片和所述第二半导体裸片中的另一个的正面或背面中的一个面，所述第一微电子元件和所述第二微电子元件的封装剂限定各自的朝外相对面；及
其中所述导电互连件形成为穿过所述第一微电子元件和所述第二微电子元件的封装剂，使得一个所述导电互连件仅通过一个所述导电元件而仅与所述第一微电子元件和所述第二微电子元件中的一个所述半导体裸片电连接，所述导电互连件在所述朝外相对面暴露。
23.根据权利要求22所述的方法，其中所述导电互连件通过激光蚀刻穿过所述第一微电子元件和所述第二微电子元件的封装剂的开口、并穿过相应的导电元件、且至少部分地用导电金属填充所述开口而形成。
24.根据权利要求22所述的方法，进一步包括使所述第一微电子元件和所述第二微电子元件相互固定，使得所述正面彼此面对。
25.根据权利要求22所述的方法，进一步包括使所述第一微电子元件和所述第二微电子元件相互固定，使得所述第二微电子元件的正面面对所述第一微电子元件的背面。
26.根据权利要求22所述的方法，进一步包括使所述第一微电子元件和所述第二微电子元件相互固定，使得所述背面彼此面对。
27.根据权利要求22所述的方法，其中所述导电互连件形成为，包括通过对应导电元件与所述第一微电子元件连接的第一导电互连件以及通过对应导电元件与所述第二微电子元件连接的第二导电互连件。
28.根据权利要求27所述的方法，其中所述封装内形成的第一导电互连件的数量与所述封装内形成的第二导电通路的数量相等。
29.根据权利要求27所述的方法，其中所述导电互连件进一步形成为，包括与所述封装内的其他电连接脱离的第三导电互连件。
30.根据权利要求22所述的方法，进一步包括形成沿覆盖所述半导体裸片的对应正面和所述封装剂的第一主表面的介电区域延伸的导电元件。
31.根据权利要求30所述的方法，其中所述导电元件的形成包括，在把所述微电子元件固定在一起之前，在所述第一微电子元件或所述第二微电子元件中的至少一个上形成导电元件。
32.根据权利要求30所述的方法，其中所述导电元件的形成包括，在把所述微电子元件固定在一起之前，在覆盖所述第一微电子元件或所述第二微电子元件中至少一个的介电区域上形成导电元件。
33.制造微电子组件的方法，包括：
制造第一微电子封装，通过以下方法，包括：
形成穿过封装的第一微电子元件和第二微电子元件的复数个导电互连件，每个微电子元件都包括：
半导体裸片，具有沿第一横向方向和第二横向方向延伸的正面、在所述正面上的复数个触点、背对所述正面的背面以及在所述正面与所述背面之间延伸的边缘表面；
封装剂，至少与对应的半导体裸片的所述边缘表面接触，并沿至少一个横向方向从所述边缘表面延伸；及
导电元件，包括从所述半导体裸片的触点沿至少一个所述横向方向延伸至覆盖所述封装剂的位置的金属化通路；
其中所述第一微电子元件与所述第二微电子元件相互固定，使得第一半导体裸片和第二半导体裸片中一个的正面或背面中的一个面定向为朝向并邻近所述第一半导体裸片和所述第二半导体裸片中另一个的正面或背面中的一个面，所述第一微电子元件和所述第二微电子元件的封装剂限定对应的朝外相对面；及
其中所述导电互连件形成为穿过所述第一微电子元件和所述第二微电子元件的封装剂，使得一个所述导电互连件仅通过一个所述导电元件而仅与所述第一微电子元件和所述第二微电子元件的一个所述半导体裸片电连接，所述导电互连件在所述朝外相对面暴露；
把所述第一微电子封装设置在包括逻辑芯片的第二微电子封装上，所述逻辑芯片与所述第二微电子封装的第一表面上暴露的端子及所述第二微电子封装的第二表面上暴露的封装触点电连接；及
采用复数个导电接合元件，使所述第一微电子封装的面向所述第二微电子封装的导电互连件的端部与所述第二微电子封装的端子接合。
34.根据权利要求33所述的方法，进一步包括把第三微电子封装设置在所述第一微电子封装上，所述第三微电子封装包括在其设置为面对所述第一微电子封装的表面上暴露的端子，所述方法进一步包括，使所述第三微电子封装的端子与设置为朝向所述第三微电子封装的导电互连件的端部接合。
35.根据权利要求34所述的方法，其中所述导电互连件形成为，包括通过对应导电元件与所述第一微电子元件连接的第一导电互连件、通过对应导电元件与所述第二微电子元件连接的第二导电互连件以及与所述封装内其他电连接脱离的第三导电互连件，所述第三微电子封装的端子与所述第三导电互连件的端部接合，所述第三导电互连件使所述第三微电子封装与所述第二微电子封装电连接。
36.微电子封装，包括：
封装的第一微电子元件和第二微电子元件，每个微电子元件都包括：
半导体裸片，所述半导体裸片具有沿第一横向方向和第二横向方向延伸的正面、在所述正面上的复数个触点、背对所述正面的背面、在所述正面与所述背面之间延伸的边缘表面；
封装剂，至少与所述半导体裸片的所述边缘表面接触，并从所述边缘表面沿至少一个横向方向延伸；及
导电元件，从所述半导体裸片的触点在所述正面上沿至少一个所述横向方向延伸至覆盖所述封装剂的位置，
其中所述第一微电子元件和所述第二微电子元件通过接合区域相互固定在一起，所述接合区域在所述第一微电子元件和第二微电子元件的相对表面之间延伸，使得第一半导体裸片和第二半导体裸片中的一个半导体裸片的正面或背面中的一个面朝向并邻近所述第一半导体裸片和第二半导体裸片中的另一个半导体裸片的正面或背面中的一个面，并且至少一个所述微电子元件中的至少一些导电元件邻近所述接合区域，所述第一微电子元件和所述第二微电子元件的封装剂分别限定了远离所述接合区域且相互背对的第一朝外表面和第二朝外表面；
复数个导电互连件，每个导电互连件延伸穿过具有连续内表面的开口，所述连续内表面从所述第一朝外表面延伸穿过所述第一微电子元件的封装剂，并穿过所述接合区域和所述第二微电子元件的封装剂而延伸至所述第二朝外表面，其中一个所述导电互连件仅与一个所述导电元件在邻近所述接合区域的位置电连接，从而仅与所述第一微电子元件和所述第二微电子元件中的一个所述半导体裸片电连接。
37.根据权利要求36所述的微电子封装，其中所述开口的连续内表面与所述第一微电子元件和第二微电子元件中的至少一个导电元件相交。
38.根据权利要求36所述的微电子封装，其中所述第一微电子元件和第二微电子元件的半导体裸片的正面朝向彼此。
39.根据权利要求38所述的微电子封装，其中所述第一微电子元件的半导体裸片的复数个触点面对所述第二微电子元件的半导体裸片的相应触点。
40.根据权利要求36所述的微电子封装，其中所述第一微电子元件的半导体裸片的正面背离所述第二微电子元件的半导体裸片的正面。
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