IT201700055983A1 - Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti - Google Patents

Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti

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Publication number
IT201700055983A1
IT201700055983A1 IT102017000055983A IT201700055983A IT201700055983A1 IT 201700055983 A1 IT201700055983 A1 IT 201700055983A1 IT 102017000055983 A IT102017000055983 A IT 102017000055983A IT 201700055983 A IT201700055983 A IT 201700055983A IT 201700055983 A1 IT201700055983 A1 IT 201700055983A1
Authority
IT
Italy
Prior art keywords
semiconductor
correspondent
procedure
circuit devices
producing
Prior art date
Application number
IT102017000055983A
Other languages
English (en)
Inventor
Federico Giovanni Ziglioli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102017000055983A priority Critical patent/IT201700055983A1/it
Priority to US15/987,102 priority patent/US10424525B2/en
Publication of IT201700055983A1 publication Critical patent/IT201700055983A1/it
Priority to US16/551,272 priority patent/US10861760B2/en

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    • H01L2224/821—Forming a build-up interconnect
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10741466B2 (en) 2017-11-17 2020-08-11 Infineon Technologies Ag Formation of conductive connection tracks in package mold body using electroless plating
US20200185293A1 (en) * 2018-12-07 2020-06-11 Infineon Technologies Ag Semiconductor Package Having a Laser-Activatable Mold Compound
US11133281B2 (en) 2019-04-04 2021-09-28 Infineon Technologies Ag Chip to chip interconnect in encapsulant of molded semiconductor package
EP3754691A1 (en) * 2019-06-21 2020-12-23 Infineon Technologies Austria AG Semiconductor package having a laser-activatable mold compound
CN112018052A (zh) 2019-05-31 2020-12-01 英飞凌科技奥地利有限公司 具有可激光活化模制化合物的半导体封装
US11302613B2 (en) 2019-07-17 2022-04-12 Infineon Technologies Ag Double-sided cooled molded semiconductor package
US10886199B1 (en) * 2019-07-17 2021-01-05 Infineon Technologies Ag Molded semiconductor package with double-sided cooling
DE102019119521A1 (de) * 2019-07-18 2021-01-21 Infineon Technologies Ag Chipgehäuse und verfahren zur herstellung eines chipgehäuses
US11552024B2 (en) * 2019-08-16 2023-01-10 Stmicroelectronics S.R.L. Method of manufacturing quad flat no-lead semiconductor devices and corresponding quad flat no-lead semiconductor device
DE102019130898A1 (de) * 2019-08-16 2021-02-18 Infineon Technologies Ag Zweistufige laserbearbeitung eines verkapselungsmittels eines halbleiterchipgehäuses
US11521861B2 (en) 2019-08-16 2022-12-06 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
KR20210024869A (ko) * 2019-08-26 2021-03-08 삼성전자주식회사 반도체 칩 적층 구조, 반도체 패키지 및 이들의 제조 방법
US11626340B2 (en) * 2019-12-12 2023-04-11 Qorvo Us, Inc. Integrated circuit (IC) package with embedded heat spreader in a redistribution layer (RDL)
US11587800B2 (en) 2020-05-22 2023-02-21 Infineon Technologies Ag Semiconductor package with lead tip inspection feature

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030094693A1 (en) * 2001-11-20 2003-05-22 Jen-Kuang Fang Multi-chip module packaging device
US20040154163A1 (en) * 2003-02-06 2004-08-12 Shinichi Miyazaki Method of forming a connecting conductor and wirings of a semiconductor chip
US20040238945A1 (en) * 2003-05-28 2004-12-02 Silicon Precision Industries Co., Ltd. Thermally enhanced semiconductor package and fabrication method thereof
US20070158837A1 (en) * 2005-07-10 2007-07-12 Nec Electronics Corporation Semiconductor device
US7632753B1 (en) * 2007-10-04 2009-12-15 Amkor Technology, Inc. Wafer level package utilizing laser-activated dielectric material
CN101930958A (zh) * 2010-07-08 2010-12-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法
US20120261818A1 (en) * 2010-05-13 2012-10-18 Stats Chippac, Ltd. Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611140A (en) 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5074947A (en) 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US6064217A (en) 1993-12-23 2000-05-16 Epi Technologies, Inc. Fine pitch contact device employing a compliant conductive polymer bump
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7262082B1 (en) 2000-10-13 2007-08-28 Bridge Semiconductor Corporation Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture
TW490821B (en) 2000-11-16 2002-06-11 Orient Semiconductor Elect Ltd Application of wire bonding technique on manufacture of wafer bump and wafer level chip scale package
US6770959B2 (en) 2000-12-15 2004-08-03 Silconware Precision Industries Co., Ltd. Semiconductor package without substrate and method of manufacturing same
US6732913B2 (en) 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US20040130034A1 (en) 2001-06-13 2004-07-08 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package
JP2007521656A (ja) 2003-06-25 2007-08-02 アドバンスド インターコネクト テクノロジーズ リミテッド 半導体パッケージのためのリード・フレーム・ルーティングされたチップ・パッド
US7109107B2 (en) 2003-08-08 2006-09-19 University Of Delaware Method for creating flip-chip conductive-polymer bumps using photolithography and polishing
US7291380B2 (en) 2004-07-09 2007-11-06 Hewlett-Packard Development Company, L.P. Laser enhanced plating for forming wiring patterns
JP5592055B2 (ja) 2004-11-03 2014-09-17 テッセラ，インコーポレイテッド 積層パッケージングの改良
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
US7446419B1 (en) 2004-11-10 2008-11-04 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar of stacked metal balls
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP2008211125A (ja) * 2007-02-28 2008-09-11 Spansion Llc 半導体装置およびその製造方法
US20090236726A1 (en) 2007-12-12 2009-09-24 United Test And Assembly Center Ltd. Package-on-package semiconductor structure
US7919406B2 (en) 2009-07-08 2011-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming pillar bump structure having sidewall protection
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9679863B2 (en) 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8642387B2 (en) * 2011-11-01 2014-02-04 Flextronics Ap, Llc Method of fabricating stacked packages using laser direct structuring
US8860222B2 (en) 2011-12-27 2014-10-14 Maxim Integrated Products, Inc. Techniques for wafer-level processing of QFN packages
US8643150B1 (en) 2012-02-15 2014-02-04 Maxim Integrated Products, Inc. Wafer-level package device having solder bump assemblies that include an inner pillar structure
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9263412B2 (en) 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8659153B2 (en) 2012-07-16 2014-02-25 Micron Technology, Inc. Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9783890B2 (en) 2012-10-26 2017-10-10 Rohm And Haas Electronic Materials Llc Process for electroless plating and a solution used for the same
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9443789B2 (en) 2013-09-11 2016-09-13 Harris Corporation Embedded electronic packaging and associated methods
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9330994B2 (en) * 2014-03-28 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
KR101753225B1 (ko) * 2015-06-02 2017-07-19 에더트로닉스코리아 (주) Ｌｄｓ 공법을 이용한 적층 회로 제작 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030094693A1 (en) * 2001-11-20 2003-05-22 Jen-Kuang Fang Multi-chip module packaging device
US20040154163A1 (en) * 2003-02-06 2004-08-12 Shinichi Miyazaki Method of forming a connecting conductor and wirings of a semiconductor chip
US20040238945A1 (en) * 2003-05-28 2004-12-02 Silicon Precision Industries Co., Ltd. Thermally enhanced semiconductor package and fabrication method thereof
US20070158837A1 (en) * 2005-07-10 2007-07-12 Nec Electronics Corporation Semiconductor device
US7632753B1 (en) * 2007-10-04 2009-12-15 Amkor Technology, Inc. Wafer level package utilizing laser-activated dielectric material
US20120261818A1 (en) * 2010-05-13 2012-10-18 Stats Chippac, Ltd. Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation
CN101930958A (zh) * 2010-07-08 2010-12-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法

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