JPWO2010041630A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法Info
- Publication number
- JPWO2010041630A1 JPWO2010041630A1 JP2010532907A JP2010532907A JPWO2010041630A1 JP WO2010041630 A1 JPWO2010041630 A1 JP WO2010041630A1 JP 2010532907 A JP2010532907 A JP 2010532907A JP 2010532907 A JP2010532907 A JP 2010532907A JP WO2010041630 A1 JPWO2010041630 A1 JP WO2010041630A1
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- Prior art keywords
- wiring
- semiconductor element
- metal plate
- semiconductor device
- forming
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Abstract
Description
本発明は、日本国特許出願:特願2008−264141号(2008年10月10日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、半導体装置及びその製造方法に関し、特に、半導体素子を配線基板に内蔵させ、樹脂等の絶縁層で覆い、その上に多層の配線層と絶縁層を積層した半導体装置及びその製造方法に関する。
特許文献1では、金属放熱板101上にICチップ103の回路面を上側にして搭載し、絶縁層樹脂層104aで埋め込み、半田を介することなくIC側実装用パッド131とBGA実装パッド108を配線導体107で接続した半導体素子内蔵基板が開示されている(図16参照)。これによれば、金属放熱板101を使用することで放熱特性の優れたパッケージが実現されるが、金属放熱板101が配線導体107と電気的に接続されていない構造のため、金属放熱板101が周辺デバイス、または(内蔵された)ICチップ103から発するノイズを拾うアンテナとして機能し、(内蔵された)ICチップ103、ひいては機器全体の性能劣化や誤作動の問題が懸念される。
さらに、以下の形態も可能である。
さらに、以下の形態も可能である。
11 金属板
11a 凹部
11b 開口部
12 半導体素子
13 接着層
14 電極端子
15 第1配線(配線層、第1の配線層)
16 第2配線(配線層)
17 第3配線(配線層、外部接続端子)
18 第1ビア(ビア、第1のビア)
19 第2ビア(ビア)
20 第3ビア(ビア)
21 第1絶縁樹脂(絶縁層、第1の絶縁層)
22 第2絶縁樹脂(絶縁層)
23 第3絶縁樹脂(絶縁層)
24 第4ビア(第2のビア)
25 金属ポスト
26 ボンディングワイヤ
27 プリプレグ
28 接着層
29 金属ポスト(第2の金属ポスト)
30 配線基板
101 金属放熱板
102 金属ペースト
103 ICチップ
104a、104b、104c 絶縁層樹脂層
107 配線導体
108 BGA実装パッド
109 BGAはんだバンプ
131 IC側実装用パッド
210 電子部品実装基板
211 配線基板部
212 実装部品
212a ハンダバンプ
213 放熱基板部
213a 下面
214 主基板
214a 溝
215 誘電体膜
216 導体パターン
216a 回路側パターン
216b グランド側パターン
216c パッド
217 凹部
218 熱伝導層
219 ハンダバンプ
221 接着層
222 接着層
223 空気層
301 LSIパッケージ
302 パッド
303 ヴィアホール
304 グランドピン
305 金属コンタクト
306 ヒートシンク
307 LSIチップ
308 グランドベタ層
309 プリント基板
309a LSI実装用パッド
310 ヒートスプレッダ
350 LSIのシールド装置
Claims (20)
- 電極端子を有する1以上の半導体素子と、
前記半導体素子を支持する金属板と、
前記半導体素子を覆うとともに、複数の絶縁層及び配線層が交互に積層され、配線層間がビアで電気的に接続され、表面に外部接続端子が設けられた配線基板と、
を備え、
前記電極端子と前記外部接続端子とは、前記配線層及び前記ビアのうち少なくとも一つを介して電気的に接続され、
前記電極端子、前記配線層、及び前記ビアのうち少なくとも一つは、前記金属板と電気的に接続されていることを特徴とする半導体装置。 - 前記配線層又は前記ビアと前記金属板とは、前記半導体素子の外周領域に設けられた第2のビアで電気的に接続されていることを特徴とする請求項1記載の半導体装置。
- 前記配線層又は前記ビアと前記金属板とは、前記半導体素子の外周領域に設けられた金属ポストで電気的に接続されていることを特徴とする請求項1記載の半導体装置。
- 前記電極端子と前記金属板とは、ボンディングワイヤで電気的に接続されていることを特徴とする請求項1記載の半導体装置。
- 前記電極端子のピッチは、前記外部接続端子のピッチより狭ピッチであることを特徴とする請求項1乃至4のいずれか一に記載の半導体装置。
- 一の前記絶縁層の絶縁材料は、他の前記絶縁層の絶縁材料と異なることを特徴とする請求項1乃至5のいずれか一に記載の半導体装置。
- 前記半導体素子を覆う前記絶縁層は、前記半導体素子の側端面を覆う絶縁材料と、前記半導体素子の前記電極端子側の面を覆う絶縁材料とが異なるように構成されていることを特徴とする請求項1乃至5のいずれか一に記載の半導体装置。
- 前記半導体素子の前記電極端子の表面に第2の金属ポストが設けられ、
前記第2の金属ポストは、前記配線基板における所定の配線と接続するように構成されていることを特徴とする請求項1乃至7のいずれか一に記載の半導体装置。 - 前記金属板は、前記半導体素子側の面に凹部を有し、
前記凹部の中に前記半導体素子が配設されていることを特徴とする請求項1乃至8のいずれか一に記載の半導体装置。 - 前記金属板は、開口部を有し、
前記開口部中に前記半導体素子が配設されていることを特徴とする請求項1乃至8のいずれか一に記載の半導体装置。 - 前記金属板の前記半導体素子側の面の反対面に、ヒートシンクが設けられていることを特徴とする請求項1乃至10のいずれか一に記載の半導体装置。
- 少なくとも前記金属板と前記半導体素子との間に、接着層が設けられていることを特徴とする請求項1乃至11のいずれか一に記載の半導体装置。
- 前記接着層は、前記半導体素子の側端面を覆う前記絶縁層の絶縁材料と等しいことを特徴とする請求項1乃至12のいずれか一に記載の半導体装置。
- 金属板上に、電極端子面を表にして半導体素子を搭載する工程と、
前記金属板上に、前記半導体素子を覆う第1の絶縁層を形成する工程と、
前記金属板上に前記第1の絶縁層を貫通する第2のビアを形成する工程と、
前記第2のビアを含む前記第1の絶縁層上に第1の配線層を形成する工程と、
前記第1の配線層を含む前記第1の絶縁層の上に、複数の絶縁層及び配線層が交互に積層され、前記配線層間がビアで接続された配線基板を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 金属板上に金属ポストを形成する工程と、
前記金属板の前記金属ポスト側の面に、電極端子面を表にして半導体素子を搭載する工程と、
前記金属板上に、前記半導体素子と前記金属ポストを覆う第1の絶縁層を形成する工程と、
前記金属ポストの表面が露出するまで前記第1の絶縁層の一部を除去する工程と、
前記金属ポストを含む前記第1の絶縁層上に第1の配線層を形成する工程と、
前記第1の配線層を含む前記第1の絶縁層の上に、複数の絶縁層及び配線層が交互に積層され、前記配線層間がビアで接続された配線基板を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 金属板上に、電極端子面を表にして半導体素子を搭載する工程と、
前記電極端子と前記金属板とをボンディングワイヤで接続する工程と、
前記金属板上に、前記半導体素子を覆う第1の絶縁層を形成する工程と、
前記第1の絶縁層上に第1の配線層を形成する工程と、
前記第1の配線層を含む前記第1の絶縁層の上に、複数の絶縁層及び配線層が交互に積層され、前記配線層間がビアで接続された配線基板を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1の絶縁層を形成する工程と前記第1の絶縁層を形成する工程の間に、前記電極端子上に前記第1の絶縁層を貫通する第1のビアを形成する工程を含み、
前記第1の配線層を形成する工程では、前記第1のビアを含む前記第1の絶縁層上に第1の配線層を形成することを特徴とする請求項14乃至16のいずれか一に記載の半導体装置の製造方法。 - 前記半導体素子を搭載する工程では、前記電極端子の表面に第2の金属ポストが設けられた前記半導体素子を搭載し、
前記第1の絶縁層を形成する工程と前記第1の配線層を形成する工程の間に、前記第2の金属ポストの表面が露出するように前記第1の絶縁層の一部を除去する工程を含み、
前記第1の配線層を形成する工程では、前記第2の金属ポストを含む前記第1の絶縁層上に第1の配線層を形成することを特徴とする請求項14乃至16のいずれか一に記載の半導体装置の製造方法。 - 前記第1の絶縁層を形成する工程では、前記半導体素子の前記電極端子側の面、及び側端面を覆う絶縁材料で一括で積層されることを特徴とする請求項14乃至18のいずれか一に記載の半導体装置の製造方法。
- 前記第1の絶縁層を形成する工程では、前記半導体素子の前記電極端子側の面を第1の絶縁材料で覆った後、前記半導体素子の側端面を前記第1の絶縁材料とは異なる第2の絶縁材料で覆うことを特徴とする請求項14乃至18のいずれか一に記載の半導体装置の製造方法。
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