TWI499024B - 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法 - Google Patents

堆疊式多封裝構造裝置、半導體封裝構造及其製造方法 Download PDF

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Publication number
TWI499024B
TWI499024B TW098100325A TW98100325A TWI499024B TW I499024 B TWI499024 B TW I499024B TW 098100325 A TW098100325 A TW 098100325A TW 98100325 A TW98100325 A TW 98100325A TW I499024 B TWI499024 B TW I499024B
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Taiwan
Prior art keywords
substrate
wafer
package structure
semiconductor package
interposer
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TW098100325A
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English (en)
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TW201027693A (en
Inventor
Chi Chih Chu
Cheng Yi Weng
Chen Kai Liao
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Advanced Semiconductor Eng
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Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW098100325A priority Critical patent/TWI499024B/zh
Priority to US12/507,305 priority patent/US8076765B2/en
Priority to US12/544,560 priority patent/US20100171206A1/en
Priority to US12/547,063 priority patent/US8012797B2/en
Publication of TW201027693A publication Critical patent/TW201027693A/zh
Priority to US13/290,819 priority patent/US20120049338A1/en
Application granted granted Critical
Publication of TWI499024B publication Critical patent/TWI499024B/zh

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Description

堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
本發明係有關於一種堆疊式多封裝構造裝置，更特別有關於一種堆疊式多封裝構造裝置之下封裝構造，其封膠化合物具有開口，可包圍且裸露出基板的電性接點。
目前，堆疊式多封裝構造(Package on Package；POP)裝置主要是指將一半導體封裝構造配置於另一半導體封裝構造上，其基本目的是要增加密度以在每單位空間中產生更大的功能性，以及更好的區域性效能，因此可降低整個堆疊式多封裝構造裝置之總面積，同時也降低其成本。
參考第1圖，美國專利第7,101,731號，標題為“具有倒置封裝構造堆疊在覆晶球格陣列封裝構造之半導體多封裝構造模組(Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA)package)”，其先前技術揭示一種堆疊式多封裝構造裝置50之結構，亦即兩個堆疊的多封裝構造模組(Multi-Package Module；MPM)，並藉由銲球28相互電性連接。在該堆疊式多封裝構造裝置50中，第一封裝構造為“上”封裝構造20，且第二封裝構造為“下”封裝構造10。該上封裝構造20堆疊在該下封裝構造10上。
然而，習知堆疊式多封裝構造裝置50之下封裝構造10的下封膠化合物17並未具有任何開口，其包圍且裸露出該下封裝構造10之上表面的該接墊11或該銲球28。因此，習知堆疊式多封裝構造裝置50無法降低銲接後之銲料溢出風險(solder extrusion risk)，進而無法降低線路間短路之可能性。
參考第2圖，目前已發展另一種習知堆疊式多封裝構造裝置150之結構。該堆疊式多封裝構造裝置150包含一上封裝構造120與一下封裝構造110。另一種習知堆疊式多封裝構造裝置150大體上類似於第1圖之習知堆疊式多封裝構造裝置50，類似元件標示類似的標號。兩者之不同處是在於該堆疊式多封裝構造裝置裝置150之上封裝構造120包含複數個銲球128，配置該基板122之下表面的接墊上，以電性連接於該下封裝構造110之晶片114的接墊115。該接墊115和絕緣層119兩者可稱為線路層，須藉由一種重新分配層(Redistribution Layer；RDL)的微影蝕刻製程而形成。由於該上封裝構造120之銲球128插入該下封裝構造110中，且該銲球128電性連接於該接墊115，因此該堆疊式多封裝構造裝置150中之該上封裝構造120及該下封裝構造110的相互連接將可達成。
然而，習知堆疊式多封裝構造裝置150之下封裝構造110的下封膠化合物117亦未具有任何開口，其包圍且裸露出該接墊115或該銲球128。因此，習知堆疊式多封裝構造裝置150無法降低銲接後之銲料溢出風險(solder extrusion risk)，進而無法降低線路間短路之可能性。
因此，便有需要提供一種堆疊式多封裝構造裝置，能夠解決前述的問題。
本發明提供一種堆疊式多封裝構造裝置，包含一下封裝構造及一上封裝構造。該第一晶片固定且電性連接於該第一基板之上表面。該第一封膠化合物包覆該第一基板及第一晶片，並裸露出該第一基板之下表面，其中該第一封膠化合物包含複數個開口，每一開口包圍且裸露出每一電性接點。該上封裝構造堆疊在該下封裝構造上，並包含一第二基板、一第二晶片及一第二封膠化合物。該第二基板具有一上表面及一下表面，該下表面相對於該上表面，且該第二基板之下表面電性連接於該第一基板之該些電性接點。該第二晶片固定且電性連接於該第二基板之上表面。該第二封膠化合物包覆該第二基板及第二晶片，並裸露出該第二基板之下表面。
根據本發明之堆疊式多封裝構造裝置，該下封裝構造的封膠化合物具有開口，其包圍且裸露出該下封裝構造之基板的電性接點，用以降低銲接後之銲料溢出風險(solder extrusion risk)，進而降低線路間短路之可能性。再者，由於該開口包圍該基板之電性接點，因此可定位該基板之電性接點之預銲劑或銲球，進而避免銲接後該上下封裝構造之間的封裝構造偏移(package offset)。
為了讓本發明之上述和其他目的、特徵、和優點能更明顯，下文將配合所附圖示，作詳細說明如下。
參考第3圖，其顯示本發明之第一實施例之堆疊式多封裝構造裝置(Package On Package；POP)200。該堆疊式多封裝構造裝置200包含一下封裝構造210一上封裝構造220。
該下封裝構造210包含一第一晶片214，其固定且電性連接於一第一基板212之上表面242。該第一基板212具有上金屬層及下金屬層，其可被圖案化以提供適當的電路，並藉由鍍通孔相互電性連接。一插入器(interposer)230可藉由諸如黏膠232而固定於該第一晶片214上，並電性連接於該第一基板212之上表面242。該插入器230可為一電路板或一基板。該插入器230具有一上表面236及一下表面238，該下表面238相對於該上表面236並面向該第一晶片214。該插入器230包含複數個電性接點234，其位於該插入器230之上表面236。在本實施例中，該電性接點234包含一接墊234a及一預銲劑(pre-solder)234b，該預銲劑234b配置於該接墊234a上；或者，在一替代實施例中，該電性接點234包含一接墊234a及一銲球(solder ball)(圖未示)，該銲球配置於該接墊234a上。複數條銲線231用以將該插入器230電性連接於該第一基板212之上表面242。一第一封膠化合物(molding compound)217包覆該第一基板212、第一晶片214、插入器230及該些銲線231，並裸露出該第一基板212之下表面244。再者，該第一封膠化合物217包含複數個開口256，每一開口256包圍且裸露出每一電性接點234。該開口256之剖面為錐形，諸如上寬下窄之方錐狀或圓錐狀；或者，該開口256之深度不小於該電性接點234之高度，藉此使該開口256具有較大的容積可容納銲接後之銲料(solder)，諸如迴銲後之預銲劑或銲球。
該上封裝構造220堆疊在該下封裝構造210上。該上封裝構造220包含一第二晶片224，其固定且電性連接於一第二基板222之上表面246。該第二基板之下表面248電性連接於該插入器230之該些電性接點234。該上封裝構造220之第二基板222亦具有上金屬層及下金屬層，其可被圖案化以提供適當的電路，並藉由鍍通孔相互電性連接。一第二封膠化合物227包覆該第二基板222及第二晶片224，並裸露出該第二基板222之下表面248。
在本實施例中，根據該下封裝構造210及該上封裝構造220，該第一及第二晶片214、224分別藉由黏膠213、223，諸如環氧樹脂而固定於該第一及第二基板212、222之上表面242、246，且該第一及第二晶片214、224可分別藉由複數條銲線216、226而打線接合於該第一及第二基板212、222之上表面242、246，以建立電性連接。該些銲線216、226亦分別由該第一封膠化合物217及第二下封膠化合物227所包覆。或者，在一替代實施例中，該第一及第二晶片214、224亦可分別藉由複數個凸塊(圖未示)而覆晶接合於該第一及第二基板212、222之上表面242、246。
複數個電性接點228(諸如銲球228b與接墊228a之組合)固定於該第二基板222之下表面248，用以電性連接於該下封裝構造210之該插入器230的該些電性接點234。因此，該堆疊式多封裝構造裝置200中之該上封裝構造220及該下封裝構造210的相互連接將可達成。複數個電性接點218(諸如銲球218b與接墊218a之組合)固定於該第一基板212之下表面244，用以電性連接於一外部電路板(圖未示)。
參考第4圖，在另一實施例中，一第三晶片252可藉由打線或覆晶接合製程而固定且電性連接於該第一基板212之下表面244，用以提供更多功能。
根據本發明之該實施例之堆疊式多封裝構造裝置，該下封裝構造的封膠化合物具有開口，其包圍且裸露出該下封裝構造之插入器的電性接點，用以降低銲接後之銲料溢出風險(solder extrusion risk)，進而降低線路間短路之可能性。再者，由於該開口包圍該插入器之電性接點，因此可定位該插入器之電性接點之預銲劑或銲球，進而避免銲接後該上下封裝構造之間的封裝構造偏移(package offset)。
參考第5至9圖，其顯示本發明之該第一實施例之堆疊式多封裝構造裝置200的下封裝構造(亦即半導體封裝構造)210製造方法。參考第5圖，首先提供一基板212，其具有一上表面242及一下表面244，該下表面244相對於該上表面242。在本實施例中，可藉由一黏膠213及複數條銲線216，將一晶片214固定且電性連接於該基板212之上表面242。參考第6圖，將一插入器230固定於該晶片214上，並電性連接於該基板212，其中該插入器230具有一上表面236及一下表面238，該下表面238相對於該上表面236並面向該晶片214。該插入器230包含複數個電性接點234，其位於該插入器230之上表面236。在本實施例中，該電性接點234包含一接墊234a及一預銲劑234b，該預銲劑234b配置於該接墊234a上。然後，提供複數條銲線231，用以將該插入器230電性連接於該基板212之上表面242。參考第7圖，模造一封膠化合物217，用以包覆該基板212、晶片214、插入器230及銲線231，並裸露出該基板212之下表面244。參考第8圖，藉由諸如一雷射鑽孔製程，將該封膠化合物217形成有複數個開口256，用以裸露出該插入器230之該些電性接點234。參考第9圖，最後將複數個銲球218b固定於該基板212之下表面248的接墊218a，如此以形成本發明之下封裝構造210。
參考第10圖，其顯示本發明之第二實施例之堆疊式多封裝構造裝置(POP)300。該堆疊式多封裝構造裝置300包含一下封裝構造310一上封裝構造320。
該下封裝構造310包含一第一晶片314，其固定且電性連接於一第一基板312之上表面342。該第一基板312具有上金屬層及下金屬層，其可被圖案化以提供適當的電路，並藉由鍍通孔相互電性連接。該第一基板312包含複數個電性接點334，其位於該第一基板312之上表面342。在本實施例中，該電性接點334包含一接墊334a及一預銲劑(pre-solder)334b，該預銲劑334b配置於該接墊334a上；或者，在一替代實施例中，該電性接點234包含一接墊334a及一銲球(圖未示)，該銲球配置於該接墊334a上。一第一封膠化合物317包覆該第一基板312及第一晶片314，並裸露出該第一基板312之下表面344。再者，該第一封膠化合物317包含複數個開口356，每一開口356包圍且裸露出每一電性接點334。該開口356之剖面為錐形，諸如上寬下窄之方錐狀或圓錐狀；或者，該開口356之深度不小於該電性接點334之高度，藉此該開口356具有較大的容積可容納銲接後之銲料(solder)，諸如迴銲後之預銲劑或銲球。
該上封裝構造320堆疊在該下封裝構造310上。該上封裝構造320包含一第二晶片324，其固定且電性連接於一第二基板322之上表面346。該第二基板之下表面348電性連接於該第一基板312之該些電性接點334。該上封裝構造320之第二基板322亦具有上金屬層及下金屬層，其可被圖案化以提供適當的電路，並藉由鍍通孔相互電性連接。一第二封膠化合物327包覆該第二基板322及第二晶片324，並裸露出該第二基板322之下表面348。
在本實施例中，根據該下封裝構造310及該上封裝構造320，該第一及第二晶片314、324分別藉由黏膠313、323，諸如環氧樹脂而固定於該第一及第二基板312、322之上表面342、346，且該第一及第二晶片314、324可分別藉由複數條銲線316、326而打線接合於該第一及第二基板312、322之上表面342、346，以建立電性連接。該些銲線316、326亦分別由該第一封膠化合物317及第二封膠化合物327所包覆。或者，在一替代實施例中，該第一及第二晶片314、324亦可分別藉由複數個凸塊(圖未示)而覆晶接合於該第一及第二基板212、222之上表面342、346。
複數個電性接點328(諸如銲球328b與接墊328a之組合)固定於該第二基板322之下表面348，用以電性連接於該下封裝構造310之該第一基板312的該些電性接點334。因此，該堆疊式多封裝構造裝置300中之該上封裝構造320及該下封裝構造310的相互連接將可達成。複數個電性接點318(諸如銲球318b與接墊318a之組合)固定於該第一基板312之下表面344，用以電性連接於一外部電路板(圖未示)。
參考第11圖，在另一實施例中，一第三晶片352可藉由打線或覆晶接合製程而固定且電性連接於該第一基板312之下表面344，用以提供更多功能。
根據本發明之該實施例之堆疊式多封裝構造裝置，該下封裝構造的封膠化合物具有開口，其包圍且裸露出該下封裝構造之基板的電性接點，用以降低銲接後之銲料溢出風險(solder extrusion risk)，進而降低線路間短路之可能性。再者，由於該開口包圍該基板之電性接點，因此可定位該基板之電性接點之預銲劑或銲球，進而避免銲接後該上下封裝構造之間的封裝構造偏移(package offset)。
參考第12至16圖，其顯示本發明之該第二實施例之堆疊式多封裝構造裝置300的下封裝構造(亦即半導體封裝構造)310製造方法。參考第12圖，首先提供一基板312，其具有一上表面342及一下表面344，該下表面344相對於該上表面342。該基板312包含複數個電性接點334，其位於該基板312之上表面342。該基板312包含複數個電性接點334，其位於該基板312之上表面342。在本實施例中，該電性接點334包含一接墊334a及一預銲劑334b，該預銲劑334b配置於該接墊334a上。可藉由打線接合製程，將一晶片314固定且電性連接於該基板312之上表面342。參考第13圖，藉由一正常模具(非特製模具)模造一封膠化合物317，用以包覆該基板312及晶片314，並裸露出該基板312之下表面344。參考第14圖，藉由諸如一雷射減厚製程，將位在該些電性接點334上之該封膠化合物317的厚度由H1減少為H2。換言之，利用雷射減厚製程，將該封膠化合物317形成有梯形斜角之外形。參考第15圖，藉由諸如一雷射鑽孔製程，將該封膠化合物317形成有複數個開口356，用以裸露出該基板312之該些電性接點334。換言之，利用雷射鑽孔製程，將該開口356形成有上寬下窄之錐狀或圓錐狀。由於該封膠化合物317的厚度已由H1減少為H2，因此該封膠化合物317較容易裸露該基板312之該些電性接點334，進而該些電性接點334容易與該些電性接點328電性連接(如第10圖所示)。參考第16圖，最後將複數個銲球318b固定於該基板312之下表面348的接墊318a，如此以形成本發明之下封裝構造310。
在一替代實施例中，該封膠化合物317包覆該基板312及晶片314，並裸露出該基板312之下表面344，如第13圖所示。參考第17圖，先藉由諸如雷射鑽孔製程，將該封膠化合物317形成有複數個開口356’，用以裸露出該基板312之該些電性接點334。然後，藉由諸如一雷射減厚製程，將位在該些電性接點334上之該封膠化合物317的厚度由H1減少為H2，如第15圖所示。最後，將複數個銲球318b固定於該基板312之下表面348的接墊318a，如此以形成本發明之下封裝構造310，如第16圖所示。
在另一替代實施例中，直接藉由諸如雷射鑽孔製程，將該封膠化合物317形成有複數個開口356’，用以裸露出該基板312之該些電性接點334，如第17圖所示。由於該封膠化合物317的厚度並未減少，因此該些開口356’具有較大的深度，進而具有較大的容積可容納銲接後之銲料(solder)。參考第18圖，最後將複數個銲球318b固定於該基板312之下表面348的接墊318a，如此以形成本發明之下封裝構造310。
雖然本發明已以前述實施例揭示，然其並非用以限定本發明，任何本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與修改。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．封裝構造
11．．．接墊
17．．．封膠化合物
20．．．封裝構造
22．．．基板
28．．．銲球
50．．．多封裝構造裝置
110．．．封裝構造
112．．．基板
113．．．黏膠
114．．．晶片
115．．．接墊
116．．．銲線
117．．．封膠化合物
118．．．銲球
119．．．絕緣層
120．．．封裝構造
122．．．基板
123．．．黏膠
124．．．晶片
125．．．接墊
126．．．銲線
127．．．封膠化合物
128．．．銲球
150．．．多封裝構造裝置
200．．．多封裝構造裝置
210．．．封裝構造
212．．．基板
213．．．黏膠
214．．．晶片
216．．．銲線
217．．．封膠化合物
218．．．電性接點
218a．．．接墊
218b．．．銲球
220．．．封裝構造
222．．．基板
223．．．黏膠
224．．．晶片
226．．．銲線
227．．．封膠化合物
228．．．電性接點
228a．．．接墊
228b．．．銲球
230．．．插入器
231．．．銲線
232．．．黏膠
234．．．電性接點
234a．．．接墊
234b．．．預銲劑
236．．．上表面
238．．．下表面
242．．．上表面
244．．．下表面
246．．．上表面
248．．．下表面
252．．．晶片
256．．．開口
300．．．多封裝構造裝置
310．．．封裝構造
312．．．基板
313．．．黏膠
314．．．晶片
316．．．銲線
317．．．封膠化合物
318．．．電性接點
318a．．．接墊
318b．．．銲球
320．．．封裝構造
322．．．基板
323．．．黏膠
324．．．晶片
326．．．銲線
327．．．封膠化合物
328．．．電性接點
328a．．．接墊
328b．．．銲球
334．．．電性接點
334a．．．接墊
334b．．．預銲劑
342．．．上表面
344．．．下表面
346．．．上表面
348．．．下表面
352．．．晶片
356．．．開口
356’．．．開口
H1．．．高度
H2．．．高度
第1圖為先前技術之一堆疊式多封裝構造裝置之剖面示意圖。
第2圖為先前技術之另一種堆疊式多封裝構造裝置之剖面示意圖。
第3圖為本發明之第一實施例之堆疊式多封裝構造裝置之剖面示意圖。
第4圖為本發明之另一實施例之堆疊式多封裝構造裝置之剖面示意圖。
第5至9圖為本發明之該第一實施例之堆疊式多封裝構造裝置之下封裝構造之製造方法之剖面示意圖。
第10圖為本發明之第二實施例之堆疊式多封裝構造裝置之剖面示意圖。
第11圖為本發明之另一實施例之堆疊式多封裝構造裝置之剖面示意圖。
第12至16圖為本發明之該第二實施例之堆疊式多封裝構造裝置之下封裝構造之製造方法之剖面示意圖。
第17圖為本發明之一替代實施例之堆疊式多封裝構造裝置之下封裝構造之製造方法之剖面示意圖。
第18圖為本發明之另一替代實施例之堆疊式多封裝構造裝置之下封裝構造之製造方法之剖面示意圖。
310．．．封裝構造
312．．．基板
313．．．黏膠
314．．．晶片
316．．．銲線
317．．．封膠化合物
318．．．電性接點
318a．．．接墊
318b．．．銲球
334．．．電性接點
334a．．．接墊
334b．．．預銲劑
342．．．上表面
344．．．下表面
356．．．開口

Claims (23)

  1. 一種半導體封裝構造，包含：一基板，具有一上表面及一下表面，該下表面相對於該上表面；一晶片，固定且電性連接於該基板之上表面；一插入器，固定於該晶片上，並電性連接於該基板之上表面，其中該插入器具有一上表面及一下表面，該下表面相對於該上表面並面向該晶片，該插入器包含複數個電性接點，其位於該插入器之上表面；以及一封膠化合物，包覆該基板、插入器及晶片，並裸露出該基板之下表面，其中該封膠化合物包含複數個開口，每一開口包圍且裸露出每一電性接點，該電性接點之高度係小於該開口之深度。
  2. 依申請專利範圍第1項之半導體封裝構造，其中該開口之剖面為錐形。
  3. 依申請專利範圍第2項之半導體封裝構造，其中該開口為上寬下窄之錐狀。
  4. 依申請專利範圍第3項之半導體封裝構造，其中該錐狀為方錐狀或圓錐狀中之一者。
  5. 依申請專利範圍第1項之半導體封裝構造， 其中該電性接點具有弧形的表面。
  6. 依申請專利範圍第1項之半導體封裝構造，其中該電性接點包含一接墊及一預銲劑，該預銲劑配置於該接墊上。
  7. 依申請專利範圍第1項之半導體封裝構造，其中該電性接點包含一接墊及一銲球，該銲球配置於該接墊上。
  8. 依申請專利範圍第1項之半導體封裝構造，另包含：另一晶片，固定且電性連接於該基板之下表面。
  9. 一種半導體封裝構造製造方法，包含下列步驟：提供一基板，其其有一上表面及一下表面，該下表面相對於該上表面；將一晶片固定且電性連接於該基板之上表面；將一插入器固定於該晶片上，並電性連接於該基板之上表面，其中該插入器具有一上表面及一下表面，該下表面相對於該上表面並面向該晶片，該插入器包含複數個電性接點，其位於該插入器之上表面；將一封膠化合物包覆該基板、插入器及晶片，裸露出該基板之下表面；以及 將該封膠化合物形成有複數個開口，其中每一開口包圍且裸露出每一電性接點，該電性接點之高度係小於該開口之深度。
  10. 依申請專利範圍第9項之半導體封裝構造製造方法，其中藉由一雷射鑽孔製程將該封膠化合物形成有複數個開口。
  11. 一種堆疊式多封裝構造裝置，包含：一下封裝構造，包含：一第一基板，具有一上表面及一下表面，該下表面相對於該上表面；一第一晶片，固定且電性連接於該第一基板之上表面；一插入器，固定於該第一晶片上，並電性連接於該第一基板之上表面，其中該插入器具有一上表面及一下表面，該下表面相對於該上表面並面向該第一晶片，該插入器包含複數個第一電性接點，其位於該插入器之上表面；以及一第一封膠化合物，包覆該第一基板、插入器及晶片，並裸露出該第一基板之下表面，其中該第一封膠化合物包含複數個開口，每一開口包圍且裸露出每一第一電性接點；以及一上封裝構造，堆疊在該下封裝構造 上，並包含：一第二基板，具有一上表面及一下表面，該下表面相對於該上表面，且該第二基板之下表面電性連接於該插入器之該些第一電性接點；一第二晶片，固定且電性連接於該第二基板之上表面；以及一第二封膠化合物，包覆該第二基板及第二晶片，並裸露出該第二基板之下表面。
  12. 一種半導體封裝構造，包含：一第一基板，具有一上表面及一下表面，並包含複數個電性接點，其中該下表面相對於該上表面，且該些電性接點位於該上表面；一第一晶片，電性連接且藉由一黏膠固定於該第一基板之上表面；以及一第一封膠化合物，包覆該第一基板、黏膠及第一晶片，並裸露出該第一基板之下表面，其中該第一封膠化合物包含複數個與該第一晶片分離之開口，每一開口包圍且裸露出每一電性接點，該電性接點之高度係小於該開口之深度。
  13. 依申請專利範圍第12項之半導體封裝構造，其中該開口之剖面為錐形。
  14. 依申請專利範圍第13項之半導體封裝構造， 其中該開口為上寬下窄之錐狀。
  15. 依申請專利範圍第14項之半導體封裝構造，其中該錐狀為方錐狀或圓錐狀中之一者。
  16. 依申請專利範圍第12項之半導體封裝構造，其中該電性接點具有弧形的表面。
  17. 依申請專利範圍第12項之半導體封裝構造，另包含：一第三晶片，固定且電性連接於該第一基板之下表面。
  18. 依申請專利範圍第12項之半導體封裝構造，另包含：一第二基板，具有一上表面及一下表面，該下表面相對於該上表面，且該第二基板之下表面電性連接於該第一基板之該些電性接點；一第二晶片，固定且電性連接於該第二基板之上表面；以及一第二封膠化合物，包覆該第二基板及第二晶片，並裸露出該第二基板之下表面。
  19. 一種半導體封裝構造製造方法，包含下列步驟：提供一基板，其具有一上表面及一下表面，並包含複數個電性接點，其中該下表面相對於該上表面，且該些電性接點位於該上 表面；將一晶片電性連接且藉由一黏膠固定於該基板之上表面；將一封膠化合物包覆該基板、黏膠及晶片，裸露出該基板之下表面；以及將該封膠化合物形成有複數個與該晶片分離之開口，其中每一開口包圍且裸露出每一電性接點，該電性接點之高度係小於該開口之深度。
  20. 依申請專利範圍第19項之半導體封裝構造製造方法，其中藉由一雷射鑽孔製程將該封膠化合物形成有該些開口。
  21. 依申請專利範圍第19項之半導體封裝構造製造方法，其中在該封膠化合物之包覆步驟後，且在該些開口之形成步驟前，該半導體封裝構造製造方法另包含下列步驟：將位在該些電性接點上之該封膠化合物的厚度減少。
  22. 依申請專利範圍第19項之半導體封裝構造製造方法，其中在該該些開口之形成步驟後，該半導體封裝構造製造方法另包含下列步驟：將位在該些電性接點上之該封膠化合物的厚度減少。
  23. 依申請專利範圍第21或22項之半導體封裝構造製造方法，其中藉由一雷射減厚製程將位在該些電性接點上之該封膠化合物的厚度減少。
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