US20120049338A1 - Stackable semiconductor device packages - Google Patents
Stackable semiconductor device packages Download PDFInfo
- Publication number
- US20120049338A1 US20120049338A1 US13/290,819 US201113290819A US2012049338A1 US 20120049338 A1 US20120049338 A1 US 20120049338A1 US 201113290819 A US201113290819 A US 201113290819A US 2012049338 A1 US2012049338 A1 US 2012049338A1
- Authority
- US
- United States
- Prior art keywords
- package
- connecting elements
- substrate unit
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 125
- 229910052799 carbon Inorganic materials 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 27
- 238000004519 manufacturing process Methods 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 17
- 230000002093 peripheral effect Effects 0.000 description 16
- 239000010410 layer Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 229910001092 metal group alloy Inorganic materials 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000012778 molding material Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 238000004513 sizing Methods 0.000 description 7
- 238000000608 laser ablation Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 230000007613 environmental effect Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000005553 drilling Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000712 assembly Effects 0.000 description 3
- 238000000429 assembly Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000037361 pathway Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001297 Zn alloy Inorganic materials 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000003637 basic solution Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- YCKOAAUKSGOOJH-UHFFFAOYSA-N copper silver Chemical compound [Cu].[Ag].[Ag] YCKOAAUKSGOOJH-UHFFFAOYSA-N 0.000 description 1
- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/45664—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- the present invention relates generally to semiconductor device packages. More particularly, the invention relates to stackable semiconductor device packages.
- Electronic products have become progressively more complex, driven at least in part by the demand for enhanced functionality and smaller sizes. While the benefits of enhanced functionality and smaller sizes are apparent, achieving these benefits also can create problems.
- electronic products typically have to accommodate a high density of semiconductor devices in a limited space.
- the space available for processors, memory devices, and other active or passive devices can be rather limited in cell phones, personal digital assistants, laptop computers, and other portable consumer products.
- semiconductor devices are typically packaged in a fashion to provide protection against environmental conditions as well as to provide input and output electrical connections. Packaging of semiconductor devices within semiconductor device packages can take up additional valuable space within electronic products. As such, there is a strong drive towards reducing footprint areas taken up by semiconductor device packages.
- One approach along this regard is to stack semiconductor device packages on top of one another to form a stacked package assembly, which is also sometimes referred as a package-on-package (“PoP”) assembly.
- PoP package-on-package
- FIG. 1 illustrates a stacked package assembly 100 implemented in accordance with a conventional approach, in which a top package 102 is disposed above and electrically connected to a bottom package 104 .
- the top package 102 includes a substrate unit 106 and a semiconductor device 108 , which is disposed on an upper surface 118 of the substrate unit 106 .
- the top package 102 also includes a package body 110 that covers the semiconductor device 108 .
- the bottom package 104 includes a substrate unit 112 , a semiconductor device 114 , which is disposed on an upper surface 120 of the substrate unit 112 , and a package body 116 , which covers the semiconductor device 114 . Referring to FIG.
- a lateral extent of the package body 116 is less than that of the substrate unit 112 , such that a peripheral portion of the upper surface 120 remains exposed. Extending between this peripheral portion and a lower surface 122 of the substrate unit 106 are solder balls, including solder balls 124 a and 124 b , which are initially part of the top package 102 and are reflowed during stacking operations to electrically connect the top package 102 to the bottom package 104 . As illustrated in FIG. 1 , the bottom package 104 also includes solder balls 126 a , 126 b , 126 c , and 126 d , which extend from a lower surface 128 of the substrate unit 112 and provide input and output electrical connections for the assembly 100 .
- the assembly 100 can suffer from a number of disadvantages.
- the relatively large solder balls, such as the solder balls 124 a and 124 b , spanning a distance between the top package 102 and the bottom package 104 take up valuable area on the upper surface 120 of the substrate unit 112 , thereby hindering the ability to reduce a distance between adjacent ones of the solder balls as well as hindering the ability to increase a total number of the solder balls.
- manufacturing of the assembly 100 can suffer from undesirably low stacking yields, as the solder balls 124 a and 124 b may not sufficiently adhere to the substrate unit 112 of the bottom package 104 during reflow.
- a semiconductor device package includes: (1) a substrate unit including an upper surface, a lower surface, and a lateral surface disposed adjacent to a periphery of the substrate unit and extending between the upper surface and the lower surface of the substrate unit; (2) connecting elements disposed adjacent to the periphery of the substrate unit and extending upwardly from the upper surface of the substrate unit, at least one of the connecting elements having a width W C ; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and a lateral surface, the lateral surface of the package body being substantially aligned with the lateral surface of the substrate unit, the package body defining openings disposed adjacent to the upper surface of the package body, the openings at least partially exposing respective ones of the connecting elements, at least one of the openings having a width W U adjacent to the
- a stacked package assembly includes: (1) a first semiconductor device package including (a) a substrate unit including an upper surface, (b) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit, and (c) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and defining openings disposed adjacent to the upper surface of the package body; (2) a second semiconductor device package disposed adjacent to the upper surface of the package body, the second semiconductor device package including a lower surface; and (3) stacking elements extending through respective ones of the openings of the package body and electrically connecting the first semiconductor device package and the second semiconductor device package, at least one of the stacking elements corresponding to a pair of fused conductive bumps and including (a) an upper portion disposed adjacent to the lower surface of the second semiconductor device package and having a width W SU , (b) a lower portion having a lateral boundary that is at least partially
- a further aspect of the invention relates to manufacturing methods.
- a manufacturing method includes: (1) providing a substrate including an upper surface and contact pads disposed adjacent to the upper surface of the substrate; (2) applying an electrically conductive material to the upper surface of the substrate to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to the upper surface of the substrate to form a molded structure covering the conductive bumps and the semiconductor device, the molded structure including an upper surface; (5) forming openings adjacent to the upper surface of the molded structure, the openings partially exposing respective ones of the conductive bumps to define covered portions and uncovered portions of the conductive bumps, at least one of the openings having a central depth D C and a peripheral depth D P , the central depth D C corresponding to a distance between the upper surface of the molded structure and an upper end of a respective one of the conductive bumps, the peripheral depth D P corresponding to a distance between the upper surface of
- FIG. 1 illustrates a stacked package assembly implemented in accordance with a conventional approach.
- FIG. 2 illustrates a perspective view of a stackable semiconductor device package implemented in accordance with an embodiment of the invention.
- FIG. 3 illustrates a cross-sectional view of the package of FIG. 2 , taken along line A-A of FIG. 2 .
- FIG. 4 illustrates an enlarged, cross-sectional view of a portion of the package of FIG. 2 .
- FIG. 5 illustrates a cross-sectional view of a stacked package assembly formed using the package of FIG. 2 , according to an embodiment of the invention.
- FIG. 6A through FIG. 6C illustrate enlarged, cross-sectional views of a portion of the assembly of FIG. 5 .
- FIG. 7 illustrates a cross-sectional view of a stackable semiconductor device package implemented in accordance with another embodiment of the invention.
- FIG. 8 illustrates a cross-sectional view of a stackable semiconductor device package implemented in accordance with another embodiment of the invention.
- FIG. 9A through FIG. 9G illustrate a manufacturing method of forming the package of FIG. 2 and the assembly of FIG. 5 , according to an embodiment of the invention.
- a set refers to a collection of one or more components.
- a set of layers can include a single layer or multiple layers.
- Components of a set also can be referred as members of the set.
- Components of a set can be the same or different.
- components of a set can share one or more common characteristics.
- Adjacent refers to being near or adjoining Adjacent components can be spaced apart from one another or can be in actual or direct contact with one another. In some instances, adjacent components can be connected to one another or can be formed integrally with one another.
- relative terms such as “inner,” “interior,” “outer,” “exterior,” “top,” “bottom,” “upper,” “upwardly,” “lower,” “downwardly,” “vertical,” “vertically,” “lateral,” “laterally,” “above,” and “below,” refer to an orientation of a set of components with respect to one another, such as in accordance with the drawings, but do not require a particular orientation of those components during manufacturing or use.
- connection refers to an operational coupling or linking.
- Connected components can be directly coupled to one another or can be indirectly coupled to one another, such as via another set of components.
- the terms “substantially” and “substantial” refer to a considerable degree or extent. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation, such as accounting for typical tolerance levels of the manufacturing operations described herein.
- electrically conductive and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically correspond to those materials that exhibit little or no opposition to flow of an electric current. One measure of electrical conductivity is in terms of Siemens per meter (“Sm.sup. ⁇ 1”). Typically, an electrically conductive material is one having a conductivity greater than about 10.sup.4 Sm.sup. ⁇ 1, such as at least about 10.sup.5 Sm.sup. ⁇ 1 or at least about 10.sup.6 Sm.sup. ⁇ 1. Electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, electrical conductivity of a material is defined at room temperature.
- FIG. 2 and FIG. 3 illustrate a stackable semiconductor device package 200 implemented in accordance with an embodiment of the invention.
- FIG. 2 illustrates a perspective view of the package 200
- FIG. 3 illustrates a cross-sectional view of the package 200 , taken along line A-A of FIG. 2 .
- sides of the package 200 are substantially planar and have a substantially orthogonal orientation so as to define a lateral profile that extends around substantially an entire periphery of the package 200 .
- the lateral profile of the package 200 in general, can be any of a number of shapes, such as curved, inclined, stepped, or roughly textured.
- the package 200 includes a substrate unit 202 , which includes an upper surface 204 , a lower surface 206 , and lateral surfaces, including lateral surfaces 242 and 244 , which are disposed adjacent to sides of the substrate unit 202 and extend between the upper surface 204 and the lower surface 206 .
- the lateral surfaces 242 and 244 are substantially planar and have a substantially orthogonal orientation with respect to the upper surface 204 or the lower surface 206 , although it is contemplated that the shapes and orientations of the lateral surfaces 242 and 244 can vary for other implementations.
- a thickness of the substrate unit 202 namely a vertical distance between the upper surface 204 and the lower surface 206 of the substrate unit 202 , can be in the range of about 0.1 millimeter (“mm”) to about 2 mm, such as from about 0.2 mm to about 1.5 mm or from about 0.4 mm to about 0.6 mm.
- the substrate unit 202 can be implemented in a number of ways, and includes electrical interconnect to provide electrical pathways between the upper surface 204 and the lower surface 206 of the substrate unit 202 .
- the substrate unit 202 includes contact pads 246 a , 246 b , 246 c , and 246 d , which are disposed adjacent to a peripheral portion of the upper surface 204 , and contact pads 248 a , 248 b , 248 c , 248 d , and 248 e , which are disposed adjacent to the lower surface 206 .
- the contact pads 246 a , 246 b , 246 c , and 246 d and the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e are implemented as conductive ball pads to allow mounting of conductive balls, although it is contemplated that their implementation can vary from that illustrated in FIG. 3 .
- the contact pads 246 a , 246 b , 246 c , and 246 d are distributed in the form of rows extending within and along the sides of the substrate unit 202 , while the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e are distributed in the form of an array.
- the distribution of the contact pads 246 a , 246 b , 246 c , and 246 d and the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e can vary for other implementations.
- the contact pads 246 a , 246 b , 246 c , and 246 d and the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e are connected to other electrical interconnect included in the substrate unit 202 , such as a set of electrically conductive layers that are incorporated within a set of dielectric layers.
- the electrically conductive layers can be connected to one another by internal vias, and can be implemented so as to sandwich a core formed from a suitable resin, such as one based on bismaleimide and triazine or based on epoxy and polyphenylene oxide.
- the substrate unit 202 can include a substantially slab-shaped core that is sandwiched by one set of electrically conductive layers disposed adjacent to an upper surface of the core and another set of electrically conductive layers disposed adjacent to a lower surface of the core. While not illustrated in FIG. 3 , it is contemplated that a solder mask layer can be disposed adjacent to either, or both, the upper surface 204 and the lower surface 206 of the substrate unit 202 .
- the package 200 also includes connecting elements 218 a . 218 b , 218 c , and 218 d that are disposed adjacent to the peripheral portion of the upper surface 204 .
- the connecting elements 218 a , 218 b , 218 c , and 218 d are electrically connected to and extend upwardly from respective ones of the contact pads 246 a , 246 b , 246 c , and 246 d and, accordingly, are distributed in the form of rows extending within and along the sides of the substrate unit 202 .
- the connecting elements 218 a , 218 b , 218 c , and 218 d provide electrical pathways between the package 200 and another package within a stacked package assembly.
- the connecting elements 218 a , 218 b , 218 c , and 218 d are implemented as conductive balls and, more particularly, as conductive balls that are reflowed to form conductive bumps in accordance with manufacturing operations further described below.
- the connecting elements 218 a , 218 b , 218 c , and 218 d are formed from a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. As illustrated in FIG.
- a size of each connecting element 218 a , 218 b , 218 c , or 218 d can be specified in accordance with a height H C of the connecting element 218 a , 218 b , 218 c , or 218 d , namely a maximum vertical extent of the connecting element 218 a , 218 b , 218 c , or 218 d , and a width W e of the connecting element 218 a , 218 b , 218 c , or 218 d , namely a maximum lateral extent of the connecting element 218 a , 218 b , 218 c , or 218 d .
- each connecting element 218 a , 218 b , 218 c , or 218 d can be in the range of about 50 micrometer (“ ⁇ m”) to about 450 ⁇ m, such as from about 100 ⁇ m to about 400 ⁇ m or from about 150 ⁇ m to about 350 ⁇ m
- the width W C of each connecting element 218 a , 218 b , 218 c , or 218 d can be in the range of about 100 ⁇ m to about 500 ⁇ m, such as from about 150 ⁇ m to about 450 ⁇ m or from about 200 ⁇ m to about 400 ⁇ m.
- the package 200 also includes a semiconductor device 208 , which is disposed adjacent to the upper surface 204 of the substrate unit 202 , and connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e , which are disposed adjacent to the lower surface 206 of the substrate unit 202 .
- the semiconductor device 208 is a semiconductor chip, such as a processor or a memory device.
- the semiconductor device 208 is wire-bonded to the substrate unit 202 via a set of wires 212 , which are formed from gold, copper, or another suitable electrically conductive material.
- the wires 212 is desirably formed from copper, since, as compared to gold, copper has a superior electrical conductivity and a lower cost, while allowing the wires 212 to be formed with reduced diameters.
- the wires 212 can be coated with a suitable metal, such as palladium, as a protection against oxidation and other environmental conditions.
- the connecting elements 210 a , 210 , 210 c , 210 d , and 210 e provide input and output electrical connections for the package 200 , and are electrically connected to and extend downwardly from respective ones of the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e .
- the connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e are implemented as conductive balls and, more particularly, as conductive balls that are reflowed to form conductive bumps in accordance with manufacturing operations further described below.
- the connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e are formed from a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material.
- At least a subset of the connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e is electrically connected to the semiconductor device 208 via electrical interconnect included in the substrate unit 202 , and at least the same or a different subset of the connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e is electrically connected to the connecting elements 218 a , 218 b , 218 c , and 218 d via electrical interconnect included in the substrate unit 202 .
- the single semiconductor device 208 is illustrated in FIG. 3 , it is contemplated that additional semiconductor devices can be included for other implementations, and that semiconductor devices, in general, can be any active devices, any passive devices, or combinations thereof.
- the package 200 also includes a package body 214 that is disposed adjacent to the upper surface 204 of the substrate unit 202 .
- the package body 214 substantially covers or encapsulates the semiconductor device 208 and the wires 212 to provide structural rigidity as well as protection against oxidation, humidity, and other environmental conditions.
- the package body 214 extends to the sides of the substrate unit 202 and partially covers or encapsulates the connecting elements 218 a , 218 b , 218 c , and 218 d along the peripheral portion of the upper surface 204 so as to provide improved structural rigidity and reduced tendency towards bending or warping.
- the package body 214 is formed from a molding material, and includes an upper surface 224 and lateral surfaces, including lateral surfaces 220 and 222 , which are disposed adjacent to sides of the package body 214 .
- the upper surface 224 is substantially planar and has a substantially parallel orientation with respect to the upper surface 204 or the lower surface 206 of the substrate unit 202 .
- a thickness H P of the package body 214 namely a vertical distance between the upper surface 224 of the package body 214 and the upper surface 204 of the substrate unit 202 , is substantially uniform across the upper surface 204 of the substrate unit 202 , thereby allowing the package body 214 to provide a more uniform coverage of the upper surface 204 and improved structural rigidity.
- the upper surface 224 can be curved, inclined, stepped, or roughly textured for other implementations.
- the thickness H P of the package body 214 can be in the range of about 100 ⁇ m to about 600 ⁇ m, such as from about 150 ⁇ m to about 550 ⁇ m or from about 200 ⁇ m to about 500 ⁇ m.
- Disposed adjacent to a peripheral portion of the upper surface 224 and extending downwardly from the upper surface 224 are depressions, including depressions 226 a , 226 b , 226 c , and 226 d , which define apertures or openings corresponding to respective ones of the connecting elements 218 a , 218 b , 218 c , and 218 d .
- the openings at least partially expose the connecting elements 218 a , 218 b , 218 c , and 218 d for stacking another package on top of the package 200 .
- the openings are distributed in the form of rows, with each row extending along four sides of a substantially rectangular pattern or a substantially square-shaped pattern. While two rows of openings are illustrated in FIG. 2 and FIG. 3 , it is contemplated that more or less rows of openings can be included for other implementations, and that openings, in general, can be distributed in any one-dimensional pattern or any two-dimensional pattern.
- the lateral surfaces 220 and 222 of the package body 214 are substantially planar and have a substantially orthogonal orientation with respect to the upper surface 204 or the lower surface 206 of the substrate unit 202 , although it is contemplated that the lateral surfaces 220 and 222 can be curved, inclined, stepped, or roughly textured for other implementations. Also, the lateral surfaces 220 and 222 are substantially aligned or co-planar with the lateral surfaces 242 and 244 of the substrate unit 202 , respectively, such that, in conjunction with the lateral surfaces 242 and 244 , the lateral surfaces 220 and 222 define the orthogonal lateral profile of the package 200 .
- this alignment is accomplished such that a lateral extent of the package body 214 substantially corresponds to that of the substrate unit 202 , thereby allowing the package body 214 to provide a more uniform coverage of the upper surface 204 and improved structural rigidity.
- the shapes of the lateral surfaces 220 and 222 and their alignment with the lateral surfaces 242 and 244 can be varied from that illustrated in FIG. 2 and FIG. 3 , while providing sufficient structural rigidity and allowing the connecting elements 218 a , 218 b , 218 c , and 218 d to be at least partially exposed.
- FIG. 4 illustrates an enlarged, cross-sectional view of a portion of the package 200 of FIG. 2 and FIG. 3 .
- FIG. 4 illustrates a particular implementation of the package body 214 and the connecting elements 218 a and 218 b , while certain other details of the package 200 are omitted for ease of presentation.
- the package body 214 is formed with the depressions 226 a and 226 b , which define openings 400 a and 400 b that are sized to expose connection surfaces S a and S b of the connecting elements 218 a and 218 b .
- a size of each opening 400 a or 400 b can be specified in accordance with a width and a depth of the opening 400 a or 400 b .
- a number of advantages can be achieved by suitable selection and control over shapes and sizes of the openings 400 a and 400 b , shapes and sizes of the connecting elements 218 a and 218 b , or a combination of these characteristics.
- connection surfaces S a and S b by exposing the connection surfaces S a and S b , the connecting elements 218 a and 218 b , in effect, can serve as a pre-solder for improved adherence and wetting with respect to connecting elements of another package when stacking that package on top of the package 200 . Also, the relatively large areas of the connection surfaces S a and S b can enhance reliability and efficiency of electrical connections, thereby improving stacking yields.
- the package body 214 can have a tendency to expand towards and apply stresses onto the connecting elements 218 a and 218 b , and, if not sufficiently relieved, these expansion stresses can push portions of the connecting elements 218 a and 218 b , in a molten form, in a generally vertical direction and away from the contact pads 246 a and 246 b .
- Suitably sizing the openings 400 a and 400 b to expose the connection surfaces S a and S b can yield a reduction in contact areas between the connecting elements 218 a and 218 b and the package body 214 , thereby relieving expansion stresses that can otherwise lead to connection failure.
- the openings 400 a and 400 b can accommodate connecting elements of another package and can avoid or reduce instances of overflow of a conductive material during stacking operations, thereby allowing stacking elements to be formed with a reduced distance with respect to one another.
- an opening such as the opening 400 a or 400 b
- an opening is shaped in the form of a circular cone or a circular funnel, including a substantially circular cross-section with a width that varies along a vertical direction.
- a lateral boundary of an opening such as defined by the depression 226 a or 226 b
- tapers towards a respective connecting element such as the connecting element 218 a or 218 b
- contacts the connecting element to define a boundary between an uncovered, upper portion of the connecting element and a covered, lower portion of the connecting element.
- the shape of an opening in general, can be any of a number of shapes.
- an opening can have another type of tapered shape, such as an elliptical cone shape, a square cone shape, or a rectangular cone shape, a non-tapered shape, such as a circular cylindrical shape, an elliptic cylindrical shape, a square cylindrical shape, or a rectangular cylindrical shape, or another regular or irregular shape. It is also contemplated that a lateral boundary of an opening, such as defined by the depression 226 a or 226 b , can be curved in a convex fashion, curved in a concave fashion, or roughly textured.
- an upper width W U of each opening 400 a or 400 b namely a lateral extent adjacent to an upper end of the opening 400 a or 400 b and adjacent to the upper surface 224 of the package body 214 , can be in the range of about 250 ⁇ m to about 650 ⁇ m, such as from about 300 ⁇ m to about 600 ⁇ m or from about 350 ⁇ m to about 550 ⁇ m, and a lower width W L of each opening 400 a or 400 b , namely a lateral extent adjacent to a lower end of the opening 400 a or 400 b and adjacent to the boundary between covered and uncovered portions of a respective connecting element 218 a or 218 b , can be in the range of about 90 ⁇ m to about 500 ⁇ m, such as from about 135 ⁇ m to about 450 ⁇ m or from about 180 ⁇ m to about 400 ⁇ m.
- the upper width W U or the lower width W L can correspond to, for example, an average of lateral extents along orthogonal directions.
- the upper width W U and the lower width W L can be represented relative to the width W C of a respective connecting element 218 a or 218 b as follows: W U >W C and W C ⁇ W L ⁇ W C , where b sets a lower bound for the lower width W L , and can be, for example, about 0.8, about 0.85, or about 0.9.
- an upper bound for the upper width W U can be represented as follows: P ⁇ W U ⁇ W C , where P corresponds to a distance between centers of nearest-neighbor connecting elements, such as the connecting elements 218 a and 218 b , which distance is also sometimes referred as a connecting element pitch.
- the connecting element pitch P can be in the range of about 300 ⁇ m to about 800 ⁇ m, such as from about 350 ⁇ m to about 650 ⁇ m or from about 400 ⁇ m to about 600 ⁇ m.
- the openings 400 a and 400 b can be sufficiently sized, while retaining a lateral wall 402 that is disposed between the connecting elements 218 a and 218 b , as well as lateral walls between other connecting elements.
- the lateral wall 402 can serve as a barrier to avoid or reduce instances of overflow of an electrically conductive material during stacking operations, thereby allowing stacking elements to be formed with a reduced distance with respect to one another.
- a connecting element such as the connecting element 218 a or 218 b
- a connecting element is sized relative to the thickness H P of the package body 214 , such that an upper end of the connecting element is recessed below the upper surface 224 of the package body 214 , namely such that the height H C of the connecting element is less than the thickness H P of the package body 214 .
- an upper end of a connecting element can be substantially aligned or co-planar with the upper surface 224 or can protrude above the upper surface 224 . As illustrated in FIG.
- an opening such as the opening 400 a or 400 b
- a central depth D C of each opening 400 a or 400 b namely a vertical distance between the upper surface 224 of the package body 214 and an upper end of a respective connecting element 218 a or 218 b
- a peripheral depth D P adjacent to a lower end of each opening 400 a or 400 b namely a vertical distance between the upper surface 224 of the package body 214 and a boundary between covered and uncovered portions of a respective connecting element 218 a or 218 b corresponds to a maximum depth of the opening 400 a or 400 b .
- the central depth D C of each opening 400 a or 400 b can be in the range of about 20 ⁇ m to about 400 ⁇ m, such as from about 20 ⁇ m to about 180 ⁇ m, from about 50 ⁇ m to about 150 ⁇ m, or from about 80 ⁇ m to about 120 ⁇ m, and the peripheral depth D P of each opening 400 a or 400 b can be in the range of about 100 ⁇ m to about 500 ⁇ m, such as from about 150 ⁇ m to about 450 ⁇ m or from about 200 ⁇ m to about 400 ⁇ m.
- the peripheral depth D P can be represented relative to the thickness H P of the package body 214 and the width W C of a respective connecting element 218 a or 218 b as follows: H P ⁇ D P ⁇ dW C , where d sets a lower bound for the peripheral depth D P , and can be, for example, about 0.4, about 0.45, or about 0.5.
- FIG. 5 illustrates a cross-sectional view of a stacked package assembly 500 implemented in accordance with an embodiment of the invention.
- FIG. 5 illustrates a particular implementation of the assembly 500 that is formed using the package 200 of FIG. 2 through FIG. 4 .
- the assembly 500 includes a semiconductor device package 502 , which corresponds to a top package that is disposed above and electrically connected to the package 200 that corresponds to a bottom package.
- the package 502 is implemented as a ball grid array (“BGA”) package, although it is contemplated that a number of other package types can be used, including a land grid array (“LGA”) package, a quad flat no-lead (“QFN”) package, an advanced QFN (“aQFN”) package, and other types of BGA package, such as a window BGA package. While the two stacked packages 200 and 502 are illustrated in FIG. 5 , it is contemplated that additional packages can be included for other implementations. Certain aspects of the package 502 can be implemented in a similar fashion as previously described for the package 200 and, thus, are not further described herein.
- the package 502 includes a substrate unit 504 , which includes an upper surface 506 , a lower surface 508 , and lateral surfaces, including lateral surfaces 510 and 512 , which are disposed adjacent to sides of the substrate unit 504 and extend between the upper surface 506 and the lower surface 508 .
- the substrate unit 504 also includes contact pads 514 a , 514 b , 514 c , and 514 d , which are disposed adjacent to the lower surface 508 .
- the contact pads 514 a , 514 b , 514 c , and 514 d are implemented as conductive ball pads that are distributed in the form of rows, although it is contemplated that their implementation and distribution can vary from that illustrated in FIG. 5 .
- the package 502 also includes a semiconductor device 516 , which is a semiconductor chip that is disposed adjacent to the upper surface 506 of the substrate unit 504 .
- the semiconductor device 516 is wire-bonded to the substrate unit 504 via a set of wires 518 , although it is contemplated that the semiconductor device 516 can be electrically connected to the substrate unit 504 in another fashion, such as by flip chip-bonding. While the single semiconductor device 516 is illustrated within the package 502 , it is contemplated that additional semiconductor devices can be included for other implementations.
- a package body 520 Disposed adjacent to the upper surface 506 of the substrate unit 504 is a package body 520 , which substantially covers or encapsulates the semiconductor device 516 and the wires 518 to provide structural rigidity as well as protection against environmental conditions.
- the package body 520 includes an upper surface 522 and lateral surfaces, including lateral surfaces 524 and 526 , which are disposed adjacent to sides of the package body 520 .
- the lateral surfaces 524 and 526 are substantially aligned or co-planar with the lateral surfaces 510 and 512 of the substrate unit 504 , respectively, such that, in conjunction with the lateral surfaces 510 and 512 , the lateral surfaces 524 and 526 define an orthogonal lateral profile of the package 502 . Referring to FIG.
- a lateral extent of the package 502 substantially corresponds to that of the package 200 , although it is contemplated that the package 502 can be implemented with a greater or a smaller lateral extent relative to the package 200 .
- a thickness T of the package 502 namely a vertical distance between the upper surface 522 of the package body 520 and the lower surface 508 of the substrate unit 504 , substantially corresponds to that of the package 200 , although it is contemplated that the package 502 can be implemented with a greater or a smaller thickness relative to the package 200 .
- the package 502 also includes connecting elements 528 a . 528 b , 528 c , and 528 d , which are disposed adjacent to the lower surface 508 of the substrate unit 504 .
- the connecting elements 528 a , 528 b , 528 c , and 528 d provide input and output electrical connections for the package 502 , and are electrically connected to and extend downwardly from respective ones of the contact pads 514 a , 514 b , 514 c , and 514 d .
- the connecting elements 528 a , 528 b , 528 c , and 528 d are implemented as conductive balls and, more particularly, as conductive balls that are reflowed to form conductive bumps.
- the connecting elements 528 a , 528 b , 528 c , and 528 d are distributed in the form of rows, with each row extending along four sides of a substantially rectangular pattern or a substantially square-shaped pattern.
- the connecting elements 528 a , 528 b , 528 c , and 528 d of the package 502 are reflowed and undergo metallurgical bonding with the connecting elements 218 a , 218 b , 218 c , and 218 d of the package 200 .
- the connecting elements 528 a , 528 b , 528 c , and 528 d fuse or merge with respective ones of the connecting elements 218 a , 218 b , 218 c , and 218 d to form stacking elements 530 a , 530 b , 530 c , and 530 d , which provide electrical pathways between the packages 200 and 502 .
- each stacking element such as the stacking element 530 a , extends and spans a distance between the packages 200 and 502 , such as corresponding to a vertical distance between the contact pad 246 a of the package 200 and the contact pad 514 a of the package 502 .
- the stacking elements 530 a , 530 b , 530 c , and 530 d retain the packages 200 and 502 so as to be spaced apart from one another by a substantially uniform gap G, which corresponds to a vertical distance between the lower surface 508 of the package 502 and the upper surface 224 of the package 200 .
- the gap G can be in the range of about 10 ⁇ m to about 100 ⁇ m, such as from about 20 ⁇ m to about 80 ⁇ m or from about 30 ⁇ m to about 70 ⁇ m. Suitable selection and control over sizes of the connecting elements 528 a , 528 b , 528 c , and 528 d and sizes of the connecting elements 218 a , 218 b , 218 c , and 218 d allow the gap G to be varied, and, in some implementations, the gap G can be reduced such that the lower surface 508 of the package 502 is in contact with the upper surface 224 of the package 200 .
- a number of advantages can be achieved by stacking the packages 200 and 502 in the fashion illustrated in FIG. 5 .
- a pair of connecting elements such as the connecting elements 218 a and 528 b
- each of the pair of connecting elements can have a reduced size, relative to a conventional implementation using a single, relatively large solder ball to span that distance.
- a resulting stacking element such as the stacking element 530 a
- the distance between adjacent stacking elements can be specified in accordance with a stacking element pitch P′, which corresponds to a distance between centers of nearest-neighbor stacking elements, such as the stacking elements 530 a and 530 b .
- the stacking element pitch P′ can substantially correspond to the connecting element pitch P, which was previously described with reference to FIG. 4 .
- the stacking element pitch P′ can be reduced relative to a conventional implementation, and, in some implementations, the stacking element pitch P′ (and the connecting element pitch P) can be in the range of about 300 ⁇ m to about 800 ⁇ m, such as from about 300 ⁇ m to about 500 ⁇ m or from about 300 ⁇ m to about 400 ⁇ m.
- FIG. 6A through FIG. 6C illustrate enlarged, cross-sectional views of a portion of the assembly 500 of FIG. 5 .
- FIG. 6A through FIG. 6C illustrate particular implementations of the opening 400 a and the stacking element 530 a , while certain other details of the assembly 500 are omitted for ease of presentation.
- the stacking element 530 a is implemented as an elongated structure and, more particularly, as a conductive post that is formed as a result of fusing or merging of the connecting elements 218 a and 528 a .
- the stacking element 530 a is shaped in the form of a dumbbell, and includes an upper portion 600 and a lower portion 604 , which are relatively larger than a middle portion 602 that is disposed between the upper portion 600 and the lower portion 604 .
- the shape of the stacking element 530 a in general, can be any of a number of shapes.
- the upper portion 600 substantially corresponds to, or is formed from, the connecting element 528 a
- the lower portion 604 substantially corresponds to, or is formed from, the connecting element 218 a
- the middle portion 602 substantially corresponds to, or is formed from, an interface between the connecting elements 218 a and 528 a .
- a lateral boundary of the lower portion 604 is substantially covered or encapsulated by the package body 214
- a lateral boundary of the upper portion 600 is at least partially disposed within the opening 400 a and is spaced apart from the package body 214 so as to remain exposed.
- the extent of coverage of the upper portion 600 and the lower portion 604 can be varied for other implementations.
- a size of the stacking element 530 a can be specified in accordance with its height H S , namely a vertical extent of the stacking element 530 a , a width W SU of the upper portion 600 , namely a maximum lateral extent of the upper portion 600 , a width W SL of the lower portion 604 , namely a maximum lateral extent of the lower portion 604 , and a width W SM of the middle portion 602 , namely a minimum lateral extent of the middle portion 602 .
- the height H S of the stacking element 530 a can substantially correspond to a sum of the thickness H P of the package body 214 and the gap G between the packages 200 and 502 , which were previously described with reference to FIG. 3 through FIG. 5 , and, as illustrated in FIG. 6A through FIG. 6C , the stacking element 530 a protrudes above the upper surface 224 of the package body 214 to an extent corresponding to the gap G.
- the width W SL of the lower portion 604 can substantially correspond to the width W C of the connecting element 218 a , which was previously described with reference to FIG. 3 and FIG. 4 .
- the width W SM of the middle portion 602 can correspond to a minimum lateral extent of the stacking element 530 a
- a ratio of the width W SM relative to the width W SU or the width W SL can correspond to an extent of inward tapering of the middle portion 602 , relative to the upper portion 600 or the lower portion 604 .
- the width W SM can be represented relative to the smaller of the width W SU and the width W SL as follows: W SM ⁇ e ⁇ min(W SU , W SL ), where e sets a lower bound on the extent of inward tapering and is less than or equal to 1.
- the shape and size of the stacking element 530 a can be controlled by suitable selection and control over the shape and size of the opening 400 a , the shapes and sizes of the connecting elements 218 a and 528 a , or a combination of these characteristics.
- reducing the extent of inward tapering can improve structural rigidity of the stacking element 530 a , thereby enhancing reliability and efficiency of electrical connections between the packages 200 and 502 .
- the width W SU is greater than the width W SL , such as by sizing the connecting element 528 a to be greater than the connecting element 218 a .
- suitably sizing the opening 400 a allows accommodation of the greater sized connecting element 528 a and control over the extent of inward tapering.
- the width W SU is substantially the same as the width W SL , such as by similarly sizing the connecting elements 218 a and 528 a .
- suitably sizing the opening 400 a allows control over the extent of inward tapering.
- e according to the second implementation can be, for example, about 0.8, about 0.85, or about 0.9.
- the width W SU in accordance with a third implementation of FIG. 6C is substantially the same as the width W SL , such as by similarly sizing the connecting elements 218 a and 528 a .
- the extent of inward tapering is more pronounced in the third implementation, and, thus, the first and second implementations can be more desirable from the standpoint of improved structural rigidity and enhanced reliability and efficiency of electrical connections.
- FIG. 7 illustrates a cross-sectional view of a stackable semiconductor device package 700 implemented in accordance with another embodiment of the invention. Certain aspects of the package 700 can be implemented in a similar fashion as previously described for the package 200 of FIG. 2 through FIG. 4 and, thus, are not further described herein.
- the package 700 includes multiple semiconductor devices, namely a semiconductor device 700 , which is disposed adjacent to the upper surface 204 of the substrate unit 202 , and a semiconductor device 702 , which is disposed adjacent to the semiconductor device 700 .
- the semiconductor devices 700 and 702 are semiconductor chips, and are secured to one another in a suitable fashion, such as using a die attach film or an adhesive.
- stacking of the semiconductor devices 700 and 702 within the package 700 achieves a higher density of semiconductor devices for a given footprint area, beyond that achieved by stacking multiple semiconductor device packages each including a single semiconductor device. While the two semiconductor devices 700 and 702 are illustrated in FIG. 7 , it is contemplated that additional semiconductor devices can be included within the package 700 to achieve an even higher density of semiconductor devices.
- the semiconductor device 700 is wire-bonded to the substrate unit 202 via a set of wires 704
- the semiconductor device 702 is wire-bonded to the substrate unit 202 via a set of wires 706 and a set of wires 708 , the latter of which electrically connect the semiconductor device 702 to the substrate unit 202 via the semiconductor device 700
- the wires 704 , 706 , and 708 are formed from gold, copper, or another suitable electrically conductive material.
- at least a subset of the wires 704 , 706 , and 708 is desirably formed from copper, and can be coated with a suitable metal, such as palladium, as a protection against oxidation and other environmental conditions.
- FIG. 8 illustrates a cross-sectional view of a stackable semiconductor device package 800 implemented in accordance with another embodiment of the invention. Certain aspects of the package 800 can be implemented in a similar fashion as previously described for the package 200 of FIG. 2 through FIG. 4 and, thus, are not further described herein.
- the package 800 includes a semiconductor device 800 , which is a semiconductor chip that is disposed adjacent to the upper surface 204 of the substrate unit 202 .
- the semiconductor device 800 is flip chip-bonded to the substrate unit 202 via a set of conductive bumps 802 , which are formed from solder, copper, nickel, or another suitable electrically conductive material.
- a subset of the conductive bumps 802 is desirably fowled as a multi-layer bumping structure, including a copper post disposed adjacent to the semiconductor device 800 , a solder layer disposed adjacent to the substrate unit 202 , and a nickel barrier layer disposed between the copper post and the solder layer to suppress diffusion and loss of copper.
- the semiconductor device 800 is secured to the substrate unit 202 using an underfill material 804 , which is formed from an adhesive or another suitable material, although it is contemplated that the underfill material 804 can be omitted for other implementations. It is also contemplated that the semiconductor device 800 can be electrically connected to the substrate unit 202 in another fashion, such as by wire-bonding. Moreover, while the single semiconductor device 800 is illustrated in FIG. 8 , it is contemplated that additional semiconductor devices can be included within the package 800 to achieve a higher density of semiconductor devices for a given footprint area.
- FIG. 9A through FIG. 9G illustrate a manufacturing method of forming a stackable semiconductor device package and a stacked package assembly, according to an embodiment of the invention.
- the following manufacturing operations are described with reference to the package 200 of FIG. 2 through FIG. 4 and with reference to the assembly 500 of FIG. 5 through FIG. 6C .
- the manufacturing operations can be similarly carried out to form other stackable semiconductor device packages and other stacked package assemblies, such as the package 700 of FIG. 7 and the package 800 of FIG. 8 .
- the substrate 900 includes multiple substrate units, including the substrate unit 202 and an adjacent substrate unit 202 ′, thereby allowing certain of the manufacturing operations to be readily performed in parallel or sequentially.
- the substrate 900 can be implemented in a strip fashion, in which the multiple substrate units are arranged sequentially in an one-dimensional pattern, or in an array fashion, in which the multiple substrate units are arranged in a two-dimensional pattern.
- the following manufacturing operations are primarily described with reference to the substrate unit 202 and related components, although the manufacturing operations can be similarly carried for other substrate units and related components.
- multiple contact pads are disposed adjacent to an upper surface 902 of the substrate 900 , and multiple contact pads are disposed adjacent to a lower surface 904 of the substrate 900 .
- the contact pads 246 a , 246 b , 246 c , and 246 d are disposed adjacent to the upper surface 902
- the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e are disposed adjacent to the lower surface 904 .
- conductive bumps are subsequently disposed adjacent to respective ones of the contact pads 246 a , 246 b , 246 c , and 246 d and the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e , which serve to electrically connect the conductive bumps to electrical interconnect included in the substrate 900 .
- the contact pads 246 a , 246 b , 246 c , and 246 d and the contact pads 248 a , 248 b , 248 c , 248 d , and 248 e can be formed in any of a number of ways, such as photolithography, chemical etching, laser ablation or drilling, or mechanical drilling to form openings, along with plating of the openings using a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. While not illustrated in FIG. 9A , it is contemplated that a tape can be used to secure the lower surface 904 of the substrate 900 during subsequent operations.
- the tape can be implemented as a single-sided adhesive tape or a double-sided adhesive tape.
- an electrically conductive material 906 is applied to the upper surface 902 of the substrate 900 and disposed adjacent to the contact pads 246 a , 246 b , 246 c , and 246 d .
- the electrically conductive material 906 includes a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material.
- the electrically conductive material 906 can include a solder, which can be formed from any of a number of fusible metal alloys having melting points in the range of about 90° C. to about 450° C.
- the electrically conductive material 906 can include a solid core formed from a metal, a metal alloy, or a resin, which solid core can be coated with a solder.
- the electrically conductive material 906 can include an electrically conductive adhesive, which can be formed from any of a number of resins having an electrically conductive filler dispersed therein. Examples of suitable resins include epoxy-based resins and silicone-based resins, and examples of suitable fillers include silver fillers and carbon fillers.
- a dispenser 908 is laterally positioned with respect to the substrate 900 and is used to apply the electrically conductive material 906 .
- the dispenser 908 is substantially aligned with the contact pads 246 a , 246 b , 246 c , and 246 d , thereby allowing the electrically conductive material 906 to be selectively applied to the contact pads 246 a , 246 b , 246 c , and 246 d .
- the single dispenser 908 is illustrated in FIG. 9A , it is contemplated that multiple dispersers can be used to further enhance manufacturing throughput. Still referring to FIG.
- the dispenser 908 applies the electrically conductive material 906 in the form of conductive balls each having a substantially spherical or substantially spheroidal shape, although it is contemplated that the shapes of the conductive balls can vary for other implementations.
- the electrically conductive material 906 is reflowed, such as by raising the temperature to near or above a melting point of the electrically conductive material 906 .
- the electrically conductive material 906 is drawn downwardly towards the contact pads 246 a , 246 b , 246 c , and 246 d , as illustrated in FIG. 9B , thereby enhancing reliability and efficiency of electrical connections with the contact pads 246 a , 246 b , 246 c , and 246 d .
- the electrically conductive material 906 is hardened or solidified, such as by lowering the temperature to below the melting point of the electrically conductive material 906 .
- This solidification operation forms conductive bumps, which correspond to the connecting elements 218 a , 218 b , 218 c , and 218 d that are disposed adjacent to respective ones of the contact pads 246 a , 246 b , 246 c , and 246 d.
- the semiconductor device 208 is disposed adjacent to the upper surface 902 of the substrate 900 , and is electrically connected to the substrate unit 202 .
- the semiconductor device 208 is wire-bonded to the substrate unit 202 via the wires 212 . It is contemplated that the ordering of operations by which the connecting elements 218 a , 218 b , 218 c , and 218 d and the semiconductor device 208 are disposed adjacent to the substrate 900 can be varied for other implementations.
- the semiconductor device 208 can be disposed adjacent to the substrate 900 , and, subsequently, the electrically conductive material 906 can be applied to the substrate 900 to form the connecting elements 218 a , 218 b , 218 c , and 218 d.
- a molding material 910 is applied to the upper surface 902 of the substrate 900 so as to substantially cover or encapsulate the connecting elements 218 a , 218 b , 218 c , and 218 d , the semiconductor device 208 , and the wires 212 .
- the molding material 910 is applied across substantially an entire area of the upper surface 902 , thereby providing improved structural rigidity and avoiding or reducing issues related to overflowing and contamination for a conventional implementation. Also, manufacturing cost is reduced by simplifying molding operations as well as reducing the number of those molding operations.
- the molding material 910 can include, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO 2 .
- the molding material 910 can be applied using any of a number of molding techniques, such as compression molding, injection molding, and transfer molding. Once applied, the molding material 910 is hardened or solidified, such as by lowering the temperature to below a melting point of the molding material 910 , thereby forming a molded structure 912 .
- fiducial marks can be formed in the molded structure 912 , such as using laser marking. Alternatively, or in conjunction, fiducial marks can be formed adjacent to a periphery of the substrate 900 .
- Laser ablation or drilling is next carried out with respect to an upper surface 914 of the molded structure 912 .
- laser ablation is carried out using a laser 916 , which applies a laser beam or another form of optical energy to remove portions of the molded structure 912 .
- the laser 916 is laterally positioned and substantially aligned with each connecting element 218 a , 218 b , 218 c , or 218 d , such that the applied laser beam forms the depressions 226 a , 226 b , 226 c , and 226 d that expose respective ones of the connecting elements 218 a , 218 b , 218 c , and 218 d .
- the alignment of the laser 916 during laser ablation can be aided by fiducial marks, which allow proper positioning of the laser 916 when forming the depressions 226 a , 226 b , 226 c , and 226 d.
- the laser 916 can be implemented in a number of ways, such as a green laser, an infrared laser, a solid-state laser, or a CO 2 laser.
- the laser 916 can be implemented as a pulsed laser or a continuous wave laser. Suitable selection and control over operating parameters of the laser 916 allow control over sizes and shapes of the depressions 226 a , 226 b , 226 c , and 226 d as well as sizes and shapes of resulting openings, including the openings 400 a and 400 b .
- a peak output wavelength of the laser 916 can be selected in accordance with a particular composition of the molded structure 912 , and, for some implementations, the peak output wavelength can be in the visible range or the infrared range.
- an operating power of the laser 916 can be in the range of about 3 Watts (“W”) to about 20 W, such as from about 3 W to about 15 W or from about 3 W to about 10 W.
- W Power of the laser 916
- a pulse frequency and a pulse duration are additional examples of operating parameters that can be suitably selected and controlled. While the single laser 916 is illustrated in FIG. 9E , it is contemplated that multiple lasers can be used to further enhance manufacturing throughput. Also, it is contemplated that another suitable technique can be used in place of, or in conjunction with, laser ablation, such as chemical etching or mechanical drilling.
- exposed connection surfaces of the connecting elements 218 a , 218 b , 218 c , and 218 d sometimes can be roughly textured or contaminated with residues.
- the exposed connection surfaces can be subjected to cleaning operations to smooth those surfaces, such as by applying an alkaline solution or another basic solution.
- singulation is carried out with respect to the upper surface 914 of the molded structure 912 .
- Such manner of singulation can be referred as “front-side” singulation.
- singulation can be carried out with respect to the lower surface 904 of the substrate 900 , and can be referred as “back-side” singulation.
- the “front-side” singulation is carried out using a saw 920 , which forms cutting slits, including a cutting slit 922 .
- the cutting slits extend downwardly and completely through the substrate 900 and the molded structure 912 , thereby sub-dividing the substrate 900 and the molded structure 912 into discrete units, including the substrate unit 202 and the package body 214 .
- the package 200 is formed.
- the alignment of the saw 920 during the “front-side” singulation can be aided by fiducial marks, which allow proper positioning of the saw 920 when forming the cutting slits.
- the connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e are disposed adjacent to the lower surface 206 of the substrate unit 202 .
- the connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e can be formed in a similar fashion as described above for the connecting elements 218 a , 218 b , 218 c , and 218 d , such as by applying an electrically conductive material and reflowing and solidifying that material to form conductive bumps.
- the connecting elements 210 a , 210 b , 210 c , 210 d , and 210 e can be disposed adjacent to the lower surface 206 of the substrate unit 202 prior to or subsequent to the “front-side” singulation.
- Stacking is next carried out with respect to the package 502 to form the assembly 500 , as illustrated in FIG. 5 and FIG. 9G .
- the package 502 is positioned with respect to the package 200 , such that the connecting elements 528 a , 528 b , 528 c , and 528 d of the package 502 are substantially aligned with and adjacent to respective ones of the connecting elements 218 a , 218 b , 218 c , and 218 d of the package 200 .
- the connecting elements 218 a , 218 b , 218 c , and 218 d and the connecting elements 528 a , 528 b , 528 c , and 528 d are reflowed and solidified, such that metallurgical bonding takes place to form the stacking elements 530 a , 530 b , 530 c , and 530 d.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.
Description
- This application is a continuation of co-pending U.S. patent application Ser. No. 12/507,305, filed on Jul. 22, 2009, which claims the benefit of Taiwan Application Serial No. 98100325, filed on Jan. 7, 2009. The disclosures of both priority applications are incorporated herein by reference in their entireties.
- The present invention relates generally to semiconductor device packages. More particularly, the invention relates to stackable semiconductor device packages.
- Electronic products have become progressively more complex, driven at least in part by the demand for enhanced functionality and smaller sizes. While the benefits of enhanced functionality and smaller sizes are apparent, achieving these benefits also can create problems. In particular, electronic products typically have to accommodate a high density of semiconductor devices in a limited space. For example, the space available for processors, memory devices, and other active or passive devices can be rather limited in cell phones, personal digital assistants, laptop computers, and other portable consumer products. In conjunction, semiconductor devices are typically packaged in a fashion to provide protection against environmental conditions as well as to provide input and output electrical connections. Packaging of semiconductor devices within semiconductor device packages can take up additional valuable space within electronic products. As such, there is a strong drive towards reducing footprint areas taken up by semiconductor device packages. One approach along this regard is to stack semiconductor device packages on top of one another to form a stacked package assembly, which is also sometimes referred as a package-on-package (“PoP”) assembly.
-
FIG. 1 illustrates astacked package assembly 100 implemented in accordance with a conventional approach, in which atop package 102 is disposed above and electrically connected to abottom package 104. Thetop package 102 includes asubstrate unit 106 and asemiconductor device 108, which is disposed on anupper surface 118 of thesubstrate unit 106. Thetop package 102 also includes apackage body 110 that covers thesemiconductor device 108. Similarly, thebottom package 104 includes asubstrate unit 112, asemiconductor device 114, which is disposed on anupper surface 120 of thesubstrate unit 112, and apackage body 116, which covers thesemiconductor device 114. Referring toFIG. 1 , a lateral extent of thepackage body 116 is less than that of thesubstrate unit 112, such that a peripheral portion of theupper surface 120 remains exposed. Extending between this peripheral portion and alower surface 122 of thesubstrate unit 106 are solder balls, includingsolder balls top package 102 and are reflowed during stacking operations to electrically connect thetop package 102 to thebottom package 104. As illustrated inFIG. 1 , thebottom package 104 also includessolder balls lower surface 128 of thesubstrate unit 112 and provide input and output electrical connections for theassembly 100. - While a higher density of the
semiconductor devices assembly 100 can suffer from a number of disadvantages. In particular, the relatively large solder balls, such as thesolder balls top package 102 and thebottom package 104 take up valuable area on theupper surface 120 of thesubstrate unit 112, thereby hindering the ability to reduce a distance between adjacent ones of the solder balls as well as hindering the ability to increase a total number of the solder balls. Also, manufacturing of theassembly 100 can suffer from undesirably low stacking yields, as thesolder balls substrate unit 112 of thebottom package 104 during reflow. This inadequate adherence can be exacerbated by molding operations used to form thepackage body 116, as a molding material can be prone to overflowing onto and contaminating the peripheral portion of theupper surface 120. Moreover, because of the reduced lateral extent of thepackage body 116, theassembly 100 can be prone to bending or warping, which can create sufficient stresses on thesolder balls - It is against this background that a need arose to develop the stackable semiconductor device packages and related stacked package assemblies and methods described herein.
- One aspect of the invention relates to semiconductor device packages. In one embodiment, a semiconductor device package includes: (1) a substrate unit including an upper surface, a lower surface, and a lateral surface disposed adjacent to a periphery of the substrate unit and extending between the upper surface and the lower surface of the substrate unit; (2) connecting elements disposed adjacent to the periphery of the substrate unit and extending upwardly from the upper surface of the substrate unit, at least one of the connecting elements having a width WC; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and a lateral surface, the lateral surface of the package body being substantially aligned with the lateral surface of the substrate unit, the package body defining openings disposed adjacent to the upper surface of the package body, the openings at least partially exposing respective ones of the connecting elements, at least one of the openings having a width WU adjacent to the upper surface of the package body, such that WU>WC.
- Another aspect of the invention relates to stacked package assemblies. In one embodiment, a stacked package assembly includes: (1) a first semiconductor device package including (a) a substrate unit including an upper surface, (b) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit, and (c) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and defining openings disposed adjacent to the upper surface of the package body; (2) a second semiconductor device package disposed adjacent to the upper surface of the package body, the second semiconductor device package including a lower surface; and (3) stacking elements extending through respective ones of the openings of the package body and electrically connecting the first semiconductor device package and the second semiconductor device package, at least one of the stacking elements corresponding to a pair of fused conductive bumps and including (a) an upper portion disposed adjacent to the lower surface of the second semiconductor device package and having a width WSU, (b) a lower portion having a lateral boundary that is at least partially covered by the package body and having a width WSL, and (c) a middle portion disposed between the upper portion and the lower portion and having a width WSM, such that WS.gtoreq.0.8.times.min (WSU, WSL).
- A further aspect of the invention relates to manufacturing methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including an upper surface and contact pads disposed adjacent to the upper surface of the substrate; (2) applying an electrically conductive material to the upper surface of the substrate to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to the upper surface of the substrate to form a molded structure covering the conductive bumps and the semiconductor device, the molded structure including an upper surface; (5) forming openings adjacent to the upper surface of the molded structure, the openings partially exposing respective ones of the conductive bumps to define covered portions and uncovered portions of the conductive bumps, at least one of the openings having a central depth DC and a peripheral depth DP, the central depth DC corresponding to a distance between the upper surface of the molded structure and an upper end of a respective one of the conductive bumps, the peripheral depth DP corresponding to a distance between the upper surface of the molded structure and a boundary between a covered portion and an uncovered portion of the respective one of the conductive bumps, the peripheral depth DP being greater than the central depth DC, such that DP=cDC, and c.gtoreq.1.5; and (6) forming cutting slits extending through the molded structure and the substrate.
- Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.
- For a better understanding of the nature and objects of some embodiments of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, like reference numbers denote like elements, unless the context clearly dictates otherwise.
-
FIG. 1 illustrates a stacked package assembly implemented in accordance with a conventional approach. -
FIG. 2 illustrates a perspective view of a stackable semiconductor device package implemented in accordance with an embodiment of the invention. -
FIG. 3 illustrates a cross-sectional view of the package ofFIG. 2 , taken along line A-A ofFIG. 2 . -
FIG. 4 illustrates an enlarged, cross-sectional view of a portion of the package ofFIG. 2 . -
FIG. 5 illustrates a cross-sectional view of a stacked package assembly formed using the package ofFIG. 2 , according to an embodiment of the invention. -
FIG. 6A throughFIG. 6C illustrate enlarged, cross-sectional views of a portion of the assembly ofFIG. 5 . -
FIG. 7 illustrates a cross-sectional view of a stackable semiconductor device package implemented in accordance with another embodiment of the invention. -
FIG. 8 illustrates a cross-sectional view of a stackable semiconductor device package implemented in accordance with another embodiment of the invention. -
FIG. 9A throughFIG. 9G illustrate a manufacturing method of forming the package ofFIG. 2 and the assembly ofFIG. 5 , according to an embodiment of the invention. - The following definitions apply to some of the aspects described with respect to some embodiments of the invention. These definitions may likewise be expanded upon herein.
- As used herein, the singular terms “a,”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a semiconductor device can include multiple semiconductor devices unless the context clearly dictates otherwise.
- As used herein, the term “set” refers to a collection of one or more components. Thus, for example, a set of layers can include a single layer or multiple layers. Components of a set also can be referred as members of the set. Components of a set can be the same or different. In some instances, components of a set can share one or more common characteristics.
- As used herein, the term “adjacent” refers to being near or adjoining Adjacent components can be spaced apart from one another or can be in actual or direct contact with one another. In some instances, adjacent components can be connected to one another or can be formed integrally with one another.
- As used herein, relative terms, such as “inner,” “interior,” “outer,” “exterior,” “top,” “bottom,” “upper,” “upwardly,” “lower,” “downwardly,” “vertical,” “vertically,” “lateral,” “laterally,” “above,” and “below,” refer to an orientation of a set of components with respect to one another, such as in accordance with the drawings, but do not require a particular orientation of those components during manufacturing or use.
- As used herein, the terms “connect,” “connected,” “connecting,” and “connection” refer to an operational coupling or linking. Connected components can be directly coupled to one another or can be indirectly coupled to one another, such as via another set of components.
- As used herein, the terms “substantially” and “substantial” refer to a considerable degree or extent. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation, such as accounting for typical tolerance levels of the manufacturing operations described herein.
- As used herein, the terms “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically correspond to those materials that exhibit little or no opposition to flow of an electric current. One measure of electrical conductivity is in terms of Siemens per meter (“Sm.sup.−1”). Typically, an electrically conductive material is one having a conductivity greater than about 10.sup.4 Sm.sup.−1, such as at least about 10.sup.5 Sm.sup.−1 or at least about 10.sup.6 Sm.sup.−1. Electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, electrical conductivity of a material is defined at room temperature.
- Attention first turns to
FIG. 2 andFIG. 3 , which illustrate a stackablesemiconductor device package 200 implemented in accordance with an embodiment of the invention. In particular,FIG. 2 illustrates a perspective view of thepackage 200, whileFIG. 3 illustrates a cross-sectional view of thepackage 200, taken along line A-A ofFIG. 2 . In the illustrated embodiment, sides of thepackage 200 are substantially planar and have a substantially orthogonal orientation so as to define a lateral profile that extends around substantially an entire periphery of thepackage 200. However, it is contemplated that the lateral profile of thepackage 200, in general, can be any of a number of shapes, such as curved, inclined, stepped, or roughly textured. - Referring to
FIG. 2 andFIG. 3 , thepackage 200 includes asubstrate unit 202, which includes anupper surface 204, alower surface 206, and lateral surfaces, includinglateral surfaces substrate unit 202 and extend between theupper surface 204 and thelower surface 206. In the illustrated embodiment, the lateral surfaces 242 and 244 are substantially planar and have a substantially orthogonal orientation with respect to theupper surface 204 or thelower surface 206, although it is contemplated that the shapes and orientations of thelateral surfaces substrate unit 202, namely a vertical distance between theupper surface 204 and thelower surface 206 of thesubstrate unit 202, can be in the range of about 0.1 millimeter (“mm”) to about 2 mm, such as from about 0.2 mm to about 1.5 mm or from about 0.4 mm to about 0.6 mm. - The
substrate unit 202 can be implemented in a number of ways, and includes electrical interconnect to provide electrical pathways between theupper surface 204 and thelower surface 206 of thesubstrate unit 202. As illustrated inFIG. 3 , thesubstrate unit 202 includescontact pads upper surface 204, andcontact pads lower surface 206. In the illustrated embodiment, thecontact pads contact pads FIG. 3 . Thecontact pads substrate unit 202, while thecontact pads contact pads contact pads contact pads contact pads substrate unit 202, such as a set of electrically conductive layers that are incorporated within a set of dielectric layers. The electrically conductive layers can be connected to one another by internal vias, and can be implemented so as to sandwich a core formed from a suitable resin, such as one based on bismaleimide and triazine or based on epoxy and polyphenylene oxide. For example, thesubstrate unit 202 can include a substantially slab-shaped core that is sandwiched by one set of electrically conductive layers disposed adjacent to an upper surface of the core and another set of electrically conductive layers disposed adjacent to a lower surface of the core. While not illustrated inFIG. 3 , it is contemplated that a solder mask layer can be disposed adjacent to either, or both, theupper surface 204 and thelower surface 206 of thesubstrate unit 202. - As illustrated in
FIG. 3 , thepackage 200 also includes connectingelements 218 a. 218 b, 218 c, and 218 d that are disposed adjacent to the peripheral portion of theupper surface 204. The connectingelements contact pads substrate unit 202. As further described below, the connectingelements package 200 and another package within a stacked package assembly. In the illustrated embodiment, the connectingelements elements FIG. 3 , a size of each connectingelement element element element element element element - Referring to
FIG. 3 , thepackage 200 also includes asemiconductor device 208, which is disposed adjacent to theupper surface 204 of thesubstrate unit 202, and connectingelements lower surface 206 of thesubstrate unit 202. In the illustrated embodiment, thesemiconductor device 208 is a semiconductor chip, such as a processor or a memory device. Thesemiconductor device 208 is wire-bonded to thesubstrate unit 202 via a set ofwires 212, which are formed from gold, copper, or another suitable electrically conductive material. For certain implementations, at least a subset of thewires 212 is desirably formed from copper, since, as compared to gold, copper has a superior electrical conductivity and a lower cost, while allowing thewires 212 to be formed with reduced diameters. Thewires 212 can be coated with a suitable metal, such as palladium, as a protection against oxidation and other environmental conditions. The connectingelements package 200, and are electrically connected to and extend downwardly from respective ones of thecontact pads elements elements elements semiconductor device 208 via electrical interconnect included in thesubstrate unit 202, and at least the same or a different subset of the connectingelements elements substrate unit 202. While thesingle semiconductor device 208 is illustrated inFIG. 3 , it is contemplated that additional semiconductor devices can be included for other implementations, and that semiconductor devices, in general, can be any active devices, any passive devices, or combinations thereof. - Referring to
FIG. 2 andFIG. 3 , thepackage 200 also includes apackage body 214 that is disposed adjacent to theupper surface 204 of thesubstrate unit 202. In conjunction with thesubstrate unit 202, thepackage body 214 substantially covers or encapsulates thesemiconductor device 208 and thewires 212 to provide structural rigidity as well as protection against oxidation, humidity, and other environmental conditions. Advantageously, thepackage body 214 extends to the sides of thesubstrate unit 202 and partially covers or encapsulates the connectingelements upper surface 204 so as to provide improved structural rigidity and reduced tendency towards bending or warping. - The
package body 214 is formed from a molding material, and includes anupper surface 224 and lateral surfaces, includinglateral surfaces package body 214. In the illustrated embodiment, theupper surface 224 is substantially planar and has a substantially parallel orientation with respect to theupper surface 204 or thelower surface 206 of thesubstrate unit 202. Accordingly, a thickness HP of thepackage body 214, namely a vertical distance between theupper surface 224 of thepackage body 214 and theupper surface 204 of thesubstrate unit 202, is substantially uniform across theupper surface 204 of thesubstrate unit 202, thereby allowing thepackage body 214 to provide a more uniform coverage of theupper surface 204 and improved structural rigidity. However, it is contemplated that theupper surface 224 can be curved, inclined, stepped, or roughly textured for other implementations. For certain implementations, the thickness HP of thepackage body 214 can be in the range of about 100 μm to about 600 μm, such as from about 150 μm to about 550 μm or from about 200 μm to about 500 μm. Disposed adjacent to a peripheral portion of theupper surface 224 and extending downwardly from theupper surface 224 are depressions, includingdepressions elements elements package 200. Like the connectingelements FIG. 2 andFIG. 3 , it is contemplated that more or less rows of openings can be included for other implementations, and that openings, in general, can be distributed in any one-dimensional pattern or any two-dimensional pattern. - Referring to
FIG. 2 andFIG. 3 , the lateral surfaces 220 and 222 of thepackage body 214 are substantially planar and have a substantially orthogonal orientation with respect to theupper surface 204 or thelower surface 206 of thesubstrate unit 202, although it is contemplated that thelateral surfaces lateral surfaces substrate unit 202, respectively, such that, in conjunction with thelateral surfaces package 200. More particularly, this alignment is accomplished such that a lateral extent of thepackage body 214 substantially corresponds to that of thesubstrate unit 202, thereby allowing thepackage body 214 to provide a more uniform coverage of theupper surface 204 and improved structural rigidity. For other implementations, it is contemplated that the shapes of thelateral surfaces lateral surfaces FIG. 2 andFIG. 3 , while providing sufficient structural rigidity and allowing the connectingelements - Attention next turns to
FIG. 4 , which illustrates an enlarged, cross-sectional view of a portion of thepackage 200 ofFIG. 2 andFIG. 3 . In particular,FIG. 4 illustrates a particular implementation of thepackage body 214 and the connectingelements package 200 are omitted for ease of presentation. - As illustrated in
FIG. 4 , thepackage body 214 is formed with thedepressions openings elements openings elements elements package 200. Also, the relatively large areas of the connection surfaces Sa and Sb can enhance reliability and efficiency of electrical connections, thereby improving stacking yields. During stacking operations, thepackage body 214 can have a tendency to expand towards and apply stresses onto the connectingelements elements contact pads openings elements package body 214, thereby relieving expansion stresses that can otherwise lead to connection failure. Moreover, theopenings - In the illustrated embodiment, an opening, such as the opening 400 a or 400 b, is shaped in the form of a circular cone or a circular funnel, including a substantially circular cross-section with a width that varies along a vertical direction. In particular, a lateral boundary of an opening, such as defined by the
depression element depression - For certain implementations, an upper width WU of each opening 400 a or 400 b, namely a lateral extent adjacent to an upper end of the opening 400 a or 400 b and adjacent to the
upper surface 224 of thepackage body 214, can be in the range of about 250 μm to about 650 μm, such as from about 300 μm to about 600 μm or from about 350 μm to about 550 μm, and a lower width WL of each opening 400 a or 400 b, namely a lateral extent adjacent to a lower end of the opening 400 a or 400 b and adjacent to the boundary between covered and uncovered portions of a respective connectingelement opening element elements openings lateral wall 402 that is disposed between the connectingelements lateral wall 402 can serve as a barrier to avoid or reduce instances of overflow of an electrically conductive material during stacking operations, thereby allowing stacking elements to be formed with a reduced distance with respect to one another. - Still referring to
FIG. 4 , a connecting element, such as the connectingelement package body 214, such that an upper end of the connecting element is recessed below theupper surface 224 of thepackage body 214, namely such that the height HC of the connecting element is less than the thickness HP of thepackage body 214. However, it is also contemplated that an upper end of a connecting element can be substantially aligned or co-planar with theupper surface 224 or can protrude above theupper surface 224. As illustrated inFIG. 4 , an opening, such as the opening 400 a or 400 b, has a depth that varies along a lateral direction or along a radial direction relative to a center of the opening. In the illustrated embodiment, a central depth DC of each opening 400 a or 400 b, namely a vertical distance between theupper surface 224 of thepackage body 214 and an upper end of a respective connectingelement upper surface 224 of thepackage body 214 and a boundary between covered and uncovered portions of a respective connectingelement package body 214 and the width WC of a respective connectingelement -
FIG. 5 illustrates a cross-sectional view of a stackedpackage assembly 500 implemented in accordance with an embodiment of the invention. In particular.FIG. 5 illustrates a particular implementation of theassembly 500 that is formed using thepackage 200 ofFIG. 2 throughFIG. 4 . - As illustrated in
FIG. 5 , theassembly 500 includes asemiconductor device package 502, which corresponds to a top package that is disposed above and electrically connected to thepackage 200 that corresponds to a bottom package. In the illustrated embodiment, thepackage 502 is implemented as a ball grid array (“BGA”) package, although it is contemplated that a number of other package types can be used, including a land grid array (“LGA”) package, a quad flat no-lead (“QFN”) package, an advanced QFN (“aQFN”) package, and other types of BGA package, such as a window BGA package. While the twostacked packages FIG. 5 , it is contemplated that additional packages can be included for other implementations. Certain aspects of thepackage 502 can be implemented in a similar fashion as previously described for thepackage 200 and, thus, are not further described herein. - Referring to
FIG. 5 , thepackage 502 includes asubstrate unit 504, which includes anupper surface 506, alower surface 508, and lateral surfaces, includinglateral surfaces substrate unit 504 and extend between theupper surface 506 and thelower surface 508. Thesubstrate unit 504 also includescontact pads lower surface 508. In the illustrated embodiment, thecontact pads FIG. 5 . - The
package 502 also includes asemiconductor device 516, which is a semiconductor chip that is disposed adjacent to theupper surface 506 of thesubstrate unit 504. In the illustrated embodiment, thesemiconductor device 516 is wire-bonded to thesubstrate unit 504 via a set ofwires 518, although it is contemplated that thesemiconductor device 516 can be electrically connected to thesubstrate unit 504 in another fashion, such as by flip chip-bonding. While thesingle semiconductor device 516 is illustrated within thepackage 502, it is contemplated that additional semiconductor devices can be included for other implementations. - Disposed adjacent to the
upper surface 506 of thesubstrate unit 504 is apackage body 520, which substantially covers or encapsulates thesemiconductor device 516 and thewires 518 to provide structural rigidity as well as protection against environmental conditions. Thepackage body 520 includes anupper surface 522 and lateral surfaces, includinglateral surfaces package body 520. In the illustrated embodiment, the lateral surfaces 524 and 526 are substantially aligned or co-planar with thelateral surfaces substrate unit 504, respectively, such that, in conjunction with thelateral surfaces package 502. Referring toFIG. 5 , a lateral extent of thepackage 502 substantially corresponds to that of thepackage 200, although it is contemplated that thepackage 502 can be implemented with a greater or a smaller lateral extent relative to thepackage 200. Also, a thickness T of thepackage 502, namely a vertical distance between theupper surface 522 of thepackage body 520 and thelower surface 508 of thesubstrate unit 504, substantially corresponds to that of thepackage 200, although it is contemplated that thepackage 502 can be implemented with a greater or a smaller thickness relative to thepackage 200. - Referring to
FIG. 5 , thepackage 502 also includes connectingelements 528 a. 528 b, 528 c, and 528 d, which are disposed adjacent to thelower surface 508 of thesubstrate unit 504. The connectingelements package 502, and are electrically connected to and extend downwardly from respective ones of thecontact pads elements elements elements - During stacking operations, the connecting
elements package 502 are reflowed and undergo metallurgical bonding with the connectingelements package 200. In particular, the connectingelements elements elements packages FIG. 5 , each stacking element, such as the stackingelement 530 a, extends and spans a distance between thepackages contact pad 246 a of thepackage 200 and thecontact pad 514 a of thepackage 502. In conjunction, the stackingelements packages lower surface 508 of thepackage 502 and theupper surface 224 of thepackage 200. For certain implementations, the gap G can be in the range of about 10 μm to about 100 μm, such as from about 20 μm to about 80 μm or from about 30 μm to about 70 μm. Suitable selection and control over sizes of the connectingelements elements lower surface 508 of thepackage 502 is in contact with theupper surface 224 of thepackage 200. - A number of advantages can be achieved by stacking the
packages FIG. 5 . In particular, because a pair of connecting elements, such as the connectingelements packages element 530 a, can have a reduced lateral extent and can take up less valuable area, thereby allowing the ability to reduce a distance between adjacent stacking elements as well as the ability to increase a total number of stacking elements. In the illustrated embodiment, the distance between adjacent stacking elements can be specified in accordance with a stacking element pitch P′, which corresponds to a distance between centers of nearest-neighbor stacking elements, such as the stackingelements 530 a and 530 b. For certain implementations, the stacking element pitch P′ can substantially correspond to the connecting element pitch P, which was previously described with reference toFIG. 4 . By suitable selection and control over sizes of the connectingelements elements - Certain aspects of stacking elements can be further appreciated with reference to
FIG. 6A throughFIG. 6C , which illustrate enlarged, cross-sectional views of a portion of theassembly 500 ofFIG. 5 . In particular,FIG. 6A throughFIG. 6C illustrate particular implementations of the opening 400 a and the stackingelement 530 a, while certain other details of theassembly 500 are omitted for ease of presentation. - As illustrated in
FIG. 6A throughFIG. 6C , the stackingelement 530 a is implemented as an elongated structure and, more particularly, as a conductive post that is formed as a result of fusing or merging of the connectingelements element 530 a is shaped in the form of a dumbbell, and includes anupper portion 600 and alower portion 604, which are relatively larger than amiddle portion 602 that is disposed between theupper portion 600 and thelower portion 604. However, it is contemplated that the shape of the stackingelement 530 a, in general, can be any of a number of shapes. Theupper portion 600 substantially corresponds to, or is formed from, the connectingelement 528 a, thelower portion 604 substantially corresponds to, or is formed from, the connectingelement 218 a, and themiddle portion 602 substantially corresponds to, or is formed from, an interface between the connectingelements FIG. 6A throughFIG. 6C , a lateral boundary of thelower portion 604 is substantially covered or encapsulated by thepackage body 214, and a lateral boundary of theupper portion 600 is at least partially disposed within the opening 400 a and is spaced apart from thepackage body 214 so as to remain exposed. However, it is contemplated that the extent of coverage of theupper portion 600 and thelower portion 604 can be varied for other implementations. - Referring to
FIG. 6A throughFIG. 6C , a size of the stackingelement 530 a can be specified in accordance with its height HS, namely a vertical extent of the stackingelement 530 a, a width WSU of theupper portion 600, namely a maximum lateral extent of theupper portion 600, a width WSL of thelower portion 604, namely a maximum lateral extent of thelower portion 604, and a width WSM of themiddle portion 602, namely a minimum lateral extent of themiddle portion 602. As can be appreciated, the height HS of the stackingelement 530 a can substantially correspond to a sum of the thickness HP of thepackage body 214 and the gap G between thepackages FIG. 3 throughFIG. 5 , and, as illustrated inFIG. 6A throughFIG. 6C , the stackingelement 530 a protrudes above theupper surface 224 of thepackage body 214 to an extent corresponding to the gap G. Also, the width WSL of thelower portion 604 can substantially correspond to the width WC of the connectingelement 218 a, which was previously described with reference toFIG. 3 andFIG. 4 . In addition, the width WSM of themiddle portion 602 can correspond to a minimum lateral extent of the stackingelement 530 a, and a ratio of the width WSM relative to the width WSU or the width WSL can correspond to an extent of inward tapering of themiddle portion 602, relative to theupper portion 600 or thelower portion 604. For certain implementations, the width WSM can be represented relative to the smaller of the width WSU and the width WSL as follows: WSM≧e×min(WSU, WSL), where e sets a lower bound on the extent of inward tapering and is less than or equal to 1. - The shape and size of the stacking
element 530 a can be controlled by suitable selection and control over the shape and size of the opening 400 a, the shapes and sizes of the connectingelements upper portion 600 and thelower portion 604 in terms of a ratio of their widths WSU and WSL, such as by selection and control over the relative sizes of the connectingelements middle portion 602, such as by selection and control over the size of the opening 400 a. In particular, because excessive inward tapering can lead to cracking, reducing the extent of inward tapering can improve structural rigidity of the stackingelement 530 a, thereby enhancing reliability and efficiency of electrical connections between thepackages - In accordance with a first implementation of
FIG. 6A , the width WSU is greater than the width WSL, such as by sizing the connectingelement 528 a to be greater than the connectingelement 218 a. More particularly, a ratio of the width WSU and the width WSL can be represented as follows: WSU=fWSL, where f is in the range of about 1.05 to about 1.7, such as from about 1.1 to about 1.6 or from about 1.2 to about 1.5. In addition, suitably sizing the opening 400 a allows accommodation of the greater sized connectingelement 528 a and control over the extent of inward tapering. In particular, the width WSM can be represented as follows: WSM≧e×min(WSU, WSL)=eWSL, where e can be, for example, about 0.8, about 0.85, or about 0.9. It is also contemplated that the width WSL can be greater than the width WSU, such as by sizing the connectingelement 218 a to be greater than the connectingelement 528 a, and that a ratio of the width WSL and the width WSU can be represented as follows: WSL=gWSU, where g is in the range of about 1.05 to about 1.7, such as from about 1.1 to about 1.6 or from about 1.2 to about 1.5. In the case that the width WSL is greater than the width WSU, the width WSL can be represented as follows: WSM≧e×min(WSU, WSL)=eWSU, where e can be, for example, about 0.8, about 0.85, or about 0.9. - In accordance with a second implementation of
FIG. 6B , the width WSU is substantially the same as the width WSL, such as by similarly sizing the connectingelements - Like the second implementation, the width WSU in accordance with a third implementation of
FIG. 6C is substantially the same as the width WSL, such as by similarly sizing the connectingelements -
FIG. 7 illustrates a cross-sectional view of a stackablesemiconductor device package 700 implemented in accordance with another embodiment of the invention. Certain aspects of thepackage 700 can be implemented in a similar fashion as previously described for thepackage 200 ofFIG. 2 throughFIG. 4 and, thus, are not further described herein. - Referring to
FIG. 7 , thepackage 700 includes multiple semiconductor devices, namely asemiconductor device 700, which is disposed adjacent to theupper surface 204 of thesubstrate unit 202, and asemiconductor device 702, which is disposed adjacent to thesemiconductor device 700. In the illustrated embodiment, thesemiconductor devices semiconductor devices package 700 achieves a higher density of semiconductor devices for a given footprint area, beyond that achieved by stacking multiple semiconductor device packages each including a single semiconductor device. While the twosemiconductor devices FIG. 7 , it is contemplated that additional semiconductor devices can be included within thepackage 700 to achieve an even higher density of semiconductor devices. - As illustrated in
FIG. 7 , thesemiconductor device 700 is wire-bonded to thesubstrate unit 202 via a set ofwires 704, and thesemiconductor device 702 is wire-bonded to thesubstrate unit 202 via a set ofwires 706 and a set ofwires 708, the latter of which electrically connect thesemiconductor device 702 to thesubstrate unit 202 via thesemiconductor device 700. Thewires wires -
FIG. 8 illustrates a cross-sectional view of a stackablesemiconductor device package 800 implemented in accordance with another embodiment of the invention. Certain aspects of thepackage 800 can be implemented in a similar fashion as previously described for thepackage 200 ofFIG. 2 throughFIG. 4 and, thus, are not further described herein. - Referring to
FIG. 8 , thepackage 800 includes asemiconductor device 800, which is a semiconductor chip that is disposed adjacent to theupper surface 204 of thesubstrate unit 202. In the illustrated embodiment, thesemiconductor device 800 is flip chip-bonded to thesubstrate unit 202 via a set ofconductive bumps 802, which are formed from solder, copper, nickel, or another suitable electrically conductive material. For certain implementations, at least a subset of theconductive bumps 802 is desirably fowled as a multi-layer bumping structure, including a copper post disposed adjacent to thesemiconductor device 800, a solder layer disposed adjacent to thesubstrate unit 202, and a nickel barrier layer disposed between the copper post and the solder layer to suppress diffusion and loss of copper. Certain aspects of such a multi-layer bumping structure is described in the co-pending and co-owned Patent Application Publication No. 2006/0094224, the disclosure of which is incorporated herein by reference in its entirety. As illustrated inFIG. 8 , thesemiconductor device 800 is secured to thesubstrate unit 202 using anunderfill material 804, which is formed from an adhesive or another suitable material, although it is contemplated that theunderfill material 804 can be omitted for other implementations. It is also contemplated that thesemiconductor device 800 can be electrically connected to thesubstrate unit 202 in another fashion, such as by wire-bonding. Moreover, while thesingle semiconductor device 800 is illustrated inFIG. 8 , it is contemplated that additional semiconductor devices can be included within thepackage 800 to achieve a higher density of semiconductor devices for a given footprint area. -
FIG. 9A throughFIG. 9G illustrate a manufacturing method of forming a stackable semiconductor device package and a stacked package assembly, according to an embodiment of the invention. For ease of presentation, the following manufacturing operations are described with reference to thepackage 200 ofFIG. 2 throughFIG. 4 and with reference to theassembly 500 ofFIG. 5 throughFIG. 6C . However, it is contemplated that the manufacturing operations can be similarly carried out to form other stackable semiconductor device packages and other stacked package assemblies, such as thepackage 700 ofFIG. 7 and thepackage 800 ofFIG. 8 . - Referring first to
FIG. 9A , asubstrate 900 is provided. To enhance manufacturing throughput, thesubstrate 900 includes multiple substrate units, including thesubstrate unit 202 and anadjacent substrate unit 202′, thereby allowing certain of the manufacturing operations to be readily performed in parallel or sequentially. Thesubstrate 900 can be implemented in a strip fashion, in which the multiple substrate units are arranged sequentially in an one-dimensional pattern, or in an array fashion, in which the multiple substrate units are arranged in a two-dimensional pattern. For ease of presentation, the following manufacturing operations are primarily described with reference to thesubstrate unit 202 and related components, although the manufacturing operations can be similarly carried for other substrate units and related components. - As illustrated in
FIG. 9A , multiple contact pads are disposed adjacent to anupper surface 902 of thesubstrate 900, and multiple contact pads are disposed adjacent to alower surface 904 of thesubstrate 900. In particular, thecontact pads upper surface 902, while thecontact pads lower surface 904. In the illustrated embodiment, conductive bumps are subsequently disposed adjacent to respective ones of thecontact pads contact pads substrate 900. Thecontact pads contact pads FIG. 9A , it is contemplated that a tape can be used to secure thelower surface 904 of thesubstrate 900 during subsequent operations. The tape can be implemented as a single-sided adhesive tape or a double-sided adhesive tape. - Once the
substrate 900 is provided, an electricallyconductive material 906 is applied to theupper surface 902 of thesubstrate 900 and disposed adjacent to thecontact pads conductive material 906 includes a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. For example, the electricallyconductive material 906 can include a solder, which can be formed from any of a number of fusible metal alloys having melting points in the range of about 90° C. to about 450° C. Examples of such fusible metal alloys include tin-lead alloys, copper-zinc alloys, copper-silver alloys, tin-silver-copper alloys, bismuth-containing alloys, indium-containing alloys, and antimony-containing alloys. As another example, the electricallyconductive material 906 can include a solid core formed from a metal, a metal alloy, or a resin, which solid core can be coated with a solder. As a further example, the electricallyconductive material 906 can include an electrically conductive adhesive, which can be formed from any of a number of resins having an electrically conductive filler dispersed therein. Examples of suitable resins include epoxy-based resins and silicone-based resins, and examples of suitable fillers include silver fillers and carbon fillers. - In the illustrated embodiment, a
dispenser 908 is laterally positioned with respect to thesubstrate 900 and is used to apply the electricallyconductive material 906. In particular, thedispenser 908 is substantially aligned with thecontact pads conductive material 906 to be selectively applied to thecontact pads single dispenser 908 is illustrated inFIG. 9A , it is contemplated that multiple dispersers can be used to further enhance manufacturing throughput. Still referring toFIG. 9A , thedispenser 908 applies the electricallyconductive material 906 in the form of conductive balls each having a substantially spherical or substantially spheroidal shape, although it is contemplated that the shapes of the conductive balls can vary for other implementations. - Once applied, the electrically
conductive material 906 is reflowed, such as by raising the temperature to near or above a melting point of the electricallyconductive material 906. As a result of gravity and other effects, the electricallyconductive material 906 is drawn downwardly towards thecontact pads FIG. 9B , thereby enhancing reliability and efficiency of electrical connections with thecontact pads conductive material 906 is hardened or solidified, such as by lowering the temperature to below the melting point of the electricallyconductive material 906. This solidification operation forms conductive bumps, which correspond to the connectingelements contact pads - Next, as illustrated in
FIG. 9C , thesemiconductor device 208 is disposed adjacent to theupper surface 902 of thesubstrate 900, and is electrically connected to thesubstrate unit 202. In particular, thesemiconductor device 208 is wire-bonded to thesubstrate unit 202 via thewires 212. It is contemplated that the ordering of operations by which the connectingelements semiconductor device 208 are disposed adjacent to thesubstrate 900 can be varied for other implementations. For example, thesemiconductor device 208 can be disposed adjacent to thesubstrate 900, and, subsequently, the electricallyconductive material 906 can be applied to thesubstrate 900 to form the connectingelements - Referring next to
FIG. 9D , amolding material 910 is applied to theupper surface 902 of thesubstrate 900 so as to substantially cover or encapsulate the connectingelements semiconductor device 208, and thewires 212. In particular, themolding material 910 is applied across substantially an entire area of theupper surface 902, thereby providing improved structural rigidity and avoiding or reducing issues related to overflowing and contamination for a conventional implementation. Also, manufacturing cost is reduced by simplifying molding operations as well as reducing the number of those molding operations. Themolding material 910 can include, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO2. Themolding material 910 can be applied using any of a number of molding techniques, such as compression molding, injection molding, and transfer molding. Once applied, themolding material 910 is hardened or solidified, such as by lowering the temperature to below a melting point of themolding material 910, thereby forming a moldedstructure 912. To facilitate proper positioning of thesubstrate 900 during subsequent operations, fiducial marks can be formed in the moldedstructure 912, such as using laser marking. Alternatively, or in conjunction, fiducial marks can be formed adjacent to a periphery of thesubstrate 900. - Laser ablation or drilling is next carried out with respect to an
upper surface 914 of the moldedstructure 912. Referring toFIG. 9E , laser ablation is carried out using alaser 916, which applies a laser beam or another form of optical energy to remove portions of the moldedstructure 912. In particular, thelaser 916 is laterally positioned and substantially aligned with each connectingelement depressions elements laser 916 during laser ablation can be aided by fiducial marks, which allow proper positioning of thelaser 916 when forming thedepressions - The
laser 916 can be implemented in a number of ways, such as a green laser, an infrared laser, a solid-state laser, or a CO2 laser. Thelaser 916 can be implemented as a pulsed laser or a continuous wave laser. Suitable selection and control over operating parameters of thelaser 916 allow control over sizes and shapes of thedepressions openings laser 916 can be selected in accordance with a particular composition of the moldedstructure 912, and, for some implementations, the peak output wavelength can be in the visible range or the infrared range. Also, an operating power of thelaser 916 can be in the range of about 3 Watts (“W”) to about 20 W, such as from about 3 W to about 15 W or from about 3 W to about 10 W. In the case of a pulsed laser implementation, a pulse frequency and a pulse duration are additional examples of operating parameters that can be suitably selected and controlled. While thesingle laser 916 is illustrated inFIG. 9E , it is contemplated that multiple lasers can be used to further enhance manufacturing throughput. Also, it is contemplated that another suitable technique can be used in place of, or in conjunction with, laser ablation, such as chemical etching or mechanical drilling. - As a result of laser ablation, exposed connection surfaces of the connecting
elements - Next, as illustrated in
FIG. 9F , singulation is carried out with respect to theupper surface 914 of the moldedstructure 912. Such manner of singulation can be referred as “front-side” singulation. However, it is contemplated that singulation can be carried out with respect to thelower surface 904 of thesubstrate 900, and can be referred as “back-side” singulation. Referring toFIG. 9F , the “front-side” singulation is carried out using asaw 920, which forms cutting slits, including acutting slit 922. In particular, the cutting slits extend downwardly and completely through thesubstrate 900 and the moldedstructure 912, thereby sub-dividing thesubstrate 900 and the moldedstructure 912 into discrete units, including thesubstrate unit 202 and thepackage body 214. In such manner, thepackage 200 is formed. The alignment of thesaw 920 during the “front-side” singulation can be aided by fiducial marks, which allow proper positioning of thesaw 920 when forming the cutting slits. - Still referring to
FIG. 9F , the connectingelements lower surface 206 of thesubstrate unit 202. The connectingelements elements elements lower surface 206 of thesubstrate unit 202 prior to or subsequent to the “front-side” singulation. - Stacking is next carried out with respect to the
package 502 to form theassembly 500, as illustrated inFIG. 5 andFIG. 9G . In particular, thepackage 502 is positioned with respect to thepackage 200, such that the connectingelements package 502 are substantially aligned with and adjacent to respective ones of the connectingelements package 200. Once thepackages elements elements elements - While the invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. In particular, while the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.
Claims (21)
1.-20. (canceled)
21. A semiconductor package, comprising:
a substrate including an upper surface;
a plurality of connecting elements disposed adjacent to a periphery of the substrate and extending upwardly from the upper surface of the substrate;
a package body disposed adjacent to the upper surface of the substrate; and
a plurality of openings in the package body, the openings at least partially exposing respective ones of the connecting elements, at least one of the openings having a width WU adjacent to an upper surface of the package body, such that WU is in the range of about 250 μm to about 650 μm.
22. The semiconductor package of claim 21 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 300 μm to about 350 μm prior to reflow.
23. The semiconductor package of claim 21 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 200 μm to about 300 μm after reflow.
24. The semiconductor package of claim 21 , wherein the package body has a height HP, such that HP is in the range of about 100 μm to about 600 μm.
25. The semiconductor package of claim 24 , wherein WU>HP.
26. The semiconductor package of claim 21 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm.
27. The semiconductor package of claim 21 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package.
28. A semiconductor package, comprising:
a substrate including an upper surface;
a plurality of connecting elements disposed on the upper surface of the substrate;
a package body disposed on the upper surface of the substrate; and
a plurality of conical openings in the package body, the conical openings exposing respective portions of the connecting elements, at least one of the conical openings having a maximum diameter in the range of about 250 μm to about 650 μm.
29. The semiconductor package of claim 28 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 300 μm to about 350 μm prior to reflow.
30. The semiconductor package of claim 28 , wherein at least one of the connecting elements has a height HC, such that HC is in the range of about 200 μm to about 300 μm after reflow.
31. The semiconductor package of claim 28 , wherein the package body has a height HP, such that HP is in the range of about 100 μm to about 600 μm.
32. The semiconductor package of claim 31 , wherein the maximum diameter of the at least one of the openings is greater than HP.
33. The semiconductor package of claim 28 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm.
34. The semiconductor package of claim 28 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package.
35. A semiconductor package, comprising:
a substrate including an upper surface;
a plurality of connecting elements disposed on the upper surface of the substrate;
a package body disposed on the upper surface of the substrate wherein the package body has a thickness HP; and
a plurality of openings in the package body, each of the openings exposing a respective portion of the connecting elements, wherein a maximum width of each of the openings is greater than the thickness H.
36. The semiconductor package of claim 35 , wherein at least one of the connecting elements has a height that is in the range of about 300 μm to about 350 μm prior to reflow.
37. The semiconductor package of claim 35 , wherein at least one of the connecting elements has a height that is in the range of about 200 μm to about 300 μm after reflow.
38. The semiconductor package of claim 35 , wherein HP is in the range of about 100 μm to about 600 μm.
39. The semiconductor package of claim 35 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm.
40. The semiconductor package of claim 35 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/290,819 US20120049338A1 (en) | 2009-01-07 | 2011-11-07 | Stackable semiconductor device packages |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW98100325 | 2009-01-07 | ||
TW098100325A TWI499024B (en) | 2009-01-07 | 2009-01-07 | Package-on-package device, semiconductor package and method for manufacturing the same |
US12/507,305 US8076765B2 (en) | 2009-01-07 | 2009-07-22 | Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors |
US13/290,819 US20120049338A1 (en) | 2009-01-07 | 2011-11-07 | Stackable semiconductor device packages |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/507,305 Continuation US8076765B2 (en) | 2009-01-07 | 2009-07-22 | Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors |
Publications (1)
Publication Number | Publication Date |
---|---|
US20120049338A1 true US20120049338A1 (en) | 2012-03-01 |
Family
ID=42311157
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/507,305 Active 2029-10-26 US8076765B2 (en) | 2009-01-07 | 2009-07-22 | Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors |
US13/290,819 Abandoned US20120049338A1 (en) | 2009-01-07 | 2011-11-07 | Stackable semiconductor device packages |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/507,305 Active 2029-10-26 US8076765B2 (en) | 2009-01-07 | 2009-07-22 | Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors |
Country Status (2)
Country | Link |
---|---|
US (2) | US8076765B2 (en) |
TW (1) | TWI499024B (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130200509A1 (en) * | 2012-02-02 | 2013-08-08 | Samsung Electronics Co., Ltd. | Semiconductor package |
US8546932B1 (en) | 2012-08-15 | 2013-10-01 | Apple Inc. | Thin substrate PoP structure |
US8902352B2 (en) | 2012-06-08 | 2014-12-02 | Apple Inc. | Lens barrel mechanical interference prevention measures for camera module voice coil motor design |
CN104241215A (en) * | 2013-06-14 | 2014-12-24 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and semiconductor process |
US8963311B2 (en) | 2012-09-26 | 2015-02-24 | Apple Inc. | PoP structure with electrically insulating material between packages |
US9077878B2 (en) | 2012-04-17 | 2015-07-07 | Apple Inc. | Alternative lens insertion methods and associated features for camera modules |
US20160276325A1 (en) * | 2014-09-18 | 2016-09-22 | Intel Corporation | Method of embedding wlcsp components in e-wlb and e-plb |
CN107104055A (en) * | 2016-02-22 | 2017-08-29 | 日月光半导体制造股份有限公司 | Semiconductor device and its manufacture method |
US20190013299A1 (en) * | 2017-07-05 | 2019-01-10 | Sang-won Lee | Semiconductor packages |
US20200273718A1 (en) * | 2019-02-25 | 2020-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and manufacturing method thereof |
TWI703704B (en) * | 2014-12-05 | 2020-09-01 | 南韓商三星電子股份有限公司 | Package on packages, mobile computing device and electronic device |
US20210288010A1 (en) * | 2015-03-24 | 2021-09-16 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and manufacturing method thereof |
EP3951870A1 (en) * | 2016-02-22 | 2022-02-09 | MEDIATEK Inc. | Method for forming a fan-out package structure |
Families Citing this family (113)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
TWI335070B (en) * | 2007-03-23 | 2010-12-21 | Advanced Semiconductor Eng | Semiconductor package and the method of making the same |
TWI473553B (en) * | 2008-07-03 | 2015-02-11 | Advanced Semiconductor Eng | Chip package structure |
US8183677B2 (en) * | 2008-11-26 | 2012-05-22 | Infineon Technologies Ag | Device including a semiconductor chip |
US9082806B2 (en) | 2008-12-12 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US7642128B1 (en) | 2008-12-12 | 2010-01-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US9293401B2 (en) | 2008-12-12 | 2016-03-22 | Stats Chippac, Ltd. | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) |
US9064936B2 (en) | 2008-12-12 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US8592992B2 (en) | 2011-12-14 | 2013-11-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP |
US20100171206A1 (en) * | 2009-01-07 | 2010-07-08 | Chi-Chih Chu | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same |
US8012797B2 (en) * | 2009-01-07 | 2011-09-06 | Advanced Semiconductor Engineering, Inc. | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries |
TWI469283B (en) * | 2009-08-31 | 2015-01-11 | Advanced Semiconductor Eng | Package structure and package process |
US8264091B2 (en) * | 2009-09-21 | 2012-09-11 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulated via and method of manufacture thereof |
US9941195B2 (en) * | 2009-11-10 | 2018-04-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical metal insulator metal capacitor |
US8198131B2 (en) * | 2009-11-18 | 2012-06-12 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor device packages |
US8508954B2 (en) | 2009-12-17 | 2013-08-13 | Samsung Electronics Co., Ltd. | Systems employing a stacked semiconductor package |
TWI408785B (en) * | 2009-12-31 | 2013-09-11 | Advanced Semiconductor Eng | Semiconductor package |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US20110175218A1 (en) * | 2010-01-18 | 2011-07-21 | Shiann-Ming Liou | Package assembly having a semiconductor substrate |
US20110186960A1 (en) | 2010-02-03 | 2011-08-04 | Albert Wu | Techniques and configurations for recessed semiconductor substrates |
TWI419283B (en) * | 2010-02-10 | 2013-12-11 | Advanced Semiconductor Eng | Package structure |
TWI411075B (en) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8742603B2 (en) | 2010-05-20 | 2014-06-03 | Qualcomm Incorporated | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
US8482111B2 (en) * | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US8304900B2 (en) | 2010-08-11 | 2012-11-06 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked lead and method of manufacture thereof |
US20120080787A1 (en) * | 2010-10-05 | 2012-04-05 | Qualcomm Incorporated | Electronic Package and Method of Making an Electronic Package |
KR101712043B1 (en) * | 2010-10-14 | 2017-03-03 | 삼성전자주식회사 | Stacked semiconductor package, Semiconductor device including the stacked semiconductor package and Method of manufacturing the stacked semiconductor package |
TWI451546B (en) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package |
US9202715B2 (en) * | 2010-11-16 | 2015-12-01 | Stats Chippac Ltd. | Integrated circuit packaging system with connection structure and method of manufacture thereof |
US8421203B2 (en) | 2010-11-17 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit packaging system with foldable substrate and method of manufacture thereof |
US8372695B2 (en) | 2010-11-19 | 2013-02-12 | Stats Chippac Ltd. | Integrated circuit packaging system with stack interconnect and method of manufacture thereof |
US8557629B1 (en) * | 2010-12-03 | 2013-10-15 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US8502387B2 (en) | 2010-12-09 | 2013-08-06 | Stats Chippac Ltd. | Integrated circuit packaging system with vertical interconnection and method of manufacture thereof |
US9093392B2 (en) | 2010-12-10 | 2015-07-28 | Stats Chippac Ltd. | Integrated circuit packaging system with vertical interconnection and method of manufacture thereof |
TWI445155B (en) | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | Stacked semiconductor package and method for making the same |
KR20120089150A (en) * | 2011-02-01 | 2012-08-09 | 삼성전자주식회사 | Pakage On Pakage |
KR101828386B1 (en) * | 2011-02-15 | 2018-02-13 | 삼성전자주식회사 | Stacked package and method of manufacturing the same |
US9171792B2 (en) | 2011-02-28 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages having a side-by-side device arrangement and stacking functionality |
KR101740483B1 (en) * | 2011-05-02 | 2017-06-08 | 삼성전자 주식회사 | Stack Packages having a Fastening Element and a Halogen-free inter-packages connector |
KR101128063B1 (en) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | Package-on-package assembly with wire bonds to encapsulation surface |
KR101811301B1 (en) * | 2011-05-24 | 2017-12-26 | 삼성전자주식회사 | Semiconductor package |
US9252172B2 (en) | 2011-05-31 | 2016-02-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region |
JP2013021237A (en) * | 2011-07-13 | 2013-01-31 | Apic Yamada Corp | Semiconductor device and method of manufacturing the same |
US8461676B2 (en) | 2011-09-09 | 2013-06-11 | Qualcomm Incorporated | Soldering relief method and semiconductor device employing same |
US9564413B2 (en) * | 2011-09-15 | 2017-02-07 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus |
US9553162B2 (en) | 2011-09-15 | 2017-01-24 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9105552B2 (en) * | 2011-10-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9679836B2 (en) * | 2011-11-16 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods for forming the same |
US8912651B2 (en) | 2011-11-30 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) structure including stud bulbs and method |
US8546194B2 (en) | 2011-12-14 | 2013-10-01 | Stats Chippac Ltd. | Integrated circuit packaging system with interconnects and method of manufacture thereof |
US8823180B2 (en) * | 2011-12-28 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9460972B2 (en) * | 2012-01-09 | 2016-10-04 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9842798B2 (en) | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
US10049964B2 (en) | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
US8810024B2 (en) | 2012-03-23 | 2014-08-19 | Stats Chippac Ltd. | Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units |
US9837303B2 (en) | 2012-03-23 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9171790B2 (en) | 2012-05-30 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9331007B2 (en) | 2012-10-16 | 2016-05-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages |
US9385098B2 (en) * | 2012-11-21 | 2016-07-05 | Nvidia Corporation | Variable-size solder bump structures for integrated circuit packaging |
CN103165484B (en) * | 2013-03-29 | 2016-09-07 | 日月光半导体制造股份有限公司 | Stacking type encapsulation and manufacture method thereof |
KR20140139332A (en) * | 2013-05-27 | 2014-12-05 | 삼성전자주식회사 | A semiconductor package and method of fabricating the same |
CN104347557A (en) * | 2013-07-26 | 2015-02-11 | 日月光半导体制造股份有限公司 | Semiconductor packaging member and manufacturing method thereof |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9299650B1 (en) | 2013-09-25 | 2016-03-29 | Stats Chippac Ltd. | Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof |
KR102229202B1 (en) | 2013-11-07 | 2021-03-17 | 삼성전자주식회사 | Semicondcutor packages having trench type opening and methods for fabricating the same |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9559064B2 (en) | 2013-12-04 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in package-on-package structures |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9343434B2 (en) * | 2014-02-27 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser marking in packages |
KR102214508B1 (en) * | 2014-04-28 | 2021-02-09 | 삼성전자 주식회사 | Method for fabricating of stacked semiconductor package |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9666522B2 (en) | 2014-05-29 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark design for packages |
JP2016526306A (en) * | 2014-07-11 | 2016-09-01 | インテル コーポレイション | Scalable package architecture and related techniques and structures |
US10319607B2 (en) * | 2014-08-22 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with organic interposer |
US9373585B2 (en) * | 2014-09-17 | 2016-06-21 | Invensas Corporation | Polymer member based interconnect |
CN105659381A (en) * | 2014-09-26 | 2016-06-08 | 英特尔公司 | Integrated circuit package having wire-bonded multi-die stack |
US10032652B2 (en) * | 2014-12-05 | 2018-07-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having improved package-on-package interconnection |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US10002843B2 (en) * | 2015-03-24 | 2018-06-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate structure, semiconductor package and method of manufacturing the same |
US9666514B2 (en) | 2015-04-14 | 2017-05-30 | Invensas Corporation | High performance compliant substrate |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
JP2017024281A (en) * | 2015-07-23 | 2017-02-02 | セイコーエプソン株式会社 | Joint structure, piezoelectric device, liquid jetting head, and method for inspecting joint structure |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US10872879B2 (en) | 2015-11-12 | 2020-12-22 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor package and manufacturing method thereof |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US10276402B2 (en) * | 2016-03-21 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing process thereof |
US20170338204A1 (en) * | 2016-05-17 | 2017-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device and Method for UBM/RDL Routing |
KR20170129983A (en) | 2016-05-17 | 2017-11-28 | 삼성전자주식회사 | Led lighting device package, display apparatus using the same and method of manufacuring process the same |
US10121766B2 (en) * | 2016-06-30 | 2018-11-06 | Micron Technology, Inc. | Package-on-package semiconductor device assemblies including one or more windows and related methods and packages |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
WO2018067578A1 (en) | 2016-10-04 | 2018-04-12 | Skyworks Solutions, Inc. | Dual-sided radio-frequency package with overmold structure |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
US9818736B1 (en) * | 2017-03-03 | 2017-11-14 | Tdk Corporation | Method for producing semiconductor package |
KR102358323B1 (en) | 2017-07-17 | 2022-02-04 | 삼성전자주식회사 | Semiconductor package |
TWI800591B (en) * | 2018-01-15 | 2023-05-01 | 美商艾馬克科技公司 | Semiconductor package and manufacturing method thereof |
US10573573B2 (en) * | 2018-03-20 | 2020-02-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package and package-on-package structure having elliptical conductive columns |
US11735530B2 (en) | 2021-08-25 | 2023-08-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of integrating RF antenna interposer with semiconductor package |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060244117A1 (en) * | 2005-04-29 | 2006-11-02 | Stats Chippac, Ltd. | Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides |
US7777351B1 (en) * | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
Family Cites Families (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5128831A (en) * | 1991-10-31 | 1992-07-07 | Micron Technology, Inc. | High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias |
JPH06103707B2 (en) * | 1991-12-26 | 1994-12-14 | インターナショナル・ビジネス・マシーンズ・コーポレイション | How to replace semiconductor chip |
US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
JPH06268101A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate |
KR970000214B1 (en) * | 1993-11-18 | 1997-01-06 | 삼성전자 주식회사 | Semiconductor device and method of producing the same |
JPH07335783A (en) * | 1994-06-13 | 1995-12-22 | Fujitsu Ltd | Semiconductor device and semiconductor device unit |
JP2780649B2 (en) * | 1994-09-30 | 1998-07-30 | 日本電気株式会社 | Semiconductor device |
US5579207A (en) * | 1994-10-20 | 1996-11-26 | Hughes Electronics | Three-dimensional integrated circuit stacking |
US5861666A (en) * | 1995-08-30 | 1999-01-19 | Tessera, Inc. | Stacked chip assembly |
US5892290A (en) * | 1995-10-28 | 1999-04-06 | Institute Of Microelectronics | Highly reliable and planar ball grid array package |
US5714800A (en) * | 1996-03-21 | 1998-02-03 | Motorola, Inc. | Integrated circuit assembly having a stepped interposer and method |
US5844315A (en) * | 1996-03-26 | 1998-12-01 | Motorola Corporation | Low-profile microelectronic package |
JP2806357B2 (en) * | 1996-04-18 | 1998-09-30 | 日本電気株式会社 | Stack module |
US5859475A (en) * | 1996-04-24 | 1999-01-12 | Amkor Technology, Inc. | Carrier strip and molded flex circuit ball grid array |
US5748452A (en) * | 1996-07-23 | 1998-05-05 | International Business Machines Corporation | Multi-electronic device package |
US5973393A (en) * | 1996-12-20 | 1999-10-26 | Lsi Logic Corporation | Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits |
US6195268B1 (en) * | 1997-06-09 | 2001-02-27 | Floyd K. Eide | Stacking layers containing enclosed IC chips |
KR100260997B1 (en) * | 1998-04-08 | 2000-07-01 | 마이클 디. 오브라이언 | Semiconductor package |
US6451624B1 (en) * | 1998-06-05 | 2002-09-17 | Micron Technology, Inc. | Stackable semiconductor package having conductive layer and insulating layers and method of fabrication |
US6194250B1 (en) * | 1998-09-14 | 2001-02-27 | Motorola, Inc. | Low-profile microelectronic package |
JP2000294720A (en) | 1999-04-07 | 2000-10-20 | Sharp Corp | Semiconductor integrated circuit package |
JP2000323623A (en) * | 1999-05-13 | 2000-11-24 | Mitsubishi Electric Corp | Semiconductor device |
JP2001298115A (en) | 2000-04-13 | 2001-10-26 | Seiko Epson Corp | Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment |
US6642613B1 (en) * | 2000-05-09 | 2003-11-04 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
JP2002158312A (en) * | 2000-11-17 | 2002-05-31 | Oki Electric Ind Co Ltd | Semiconductor package for three-dimensional mounting, its manufacturing method and semiconductor device |
JP3798620B2 (en) | 2000-12-04 | 2006-07-19 | 富士通株式会社 | Manufacturing method of semiconductor device |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
US7034386B2 (en) * | 2001-03-26 | 2006-04-25 | Nec Corporation | Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same |
US6930256B1 (en) * | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
KR100690999B1 (en) | 2001-06-28 | 2007-03-08 | 주식회사 하이닉스반도체 | Method for mounting ball grid array package |
SG121707A1 (en) * | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
US6740546B2 (en) * | 2002-08-21 | 2004-05-25 | Micron Technology, Inc. | Packaged microelectronic devices and methods for assembling microelectronic devices |
US6787392B2 (en) * | 2002-09-09 | 2004-09-07 | Semiconductor Components Industries, L.L.C. | Structure and method of direct chip attach |
KR20040026530A (en) * | 2002-09-25 | 2004-03-31 | 삼성전자주식회사 | Semiconductor package and stack package using the same |
TW567601B (en) * | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
TWI285421B (en) * | 2002-11-05 | 2007-08-11 | Advanced Semiconductor Eng | Packaging structure having connector |
US6798057B2 (en) * | 2002-11-05 | 2004-09-28 | Micron Technology, Inc. | Thin stacked ball-grid array package |
TWI283473B (en) * | 2002-11-08 | 2007-07-01 | Advanced Semiconductor Eng | Stack package structure and electrically-connected board for stack package |
US20040191955A1 (en) * | 2002-11-15 | 2004-09-30 | Rajeev Joshi | Wafer-level chip scale package and method for fabricating and using the same |
TWI290757B (en) * | 2002-12-30 | 2007-12-01 | Advanced Semiconductor Eng | Thermal enhance MCM package and the manufacturing method thereof |
TWI284395B (en) * | 2002-12-30 | 2007-07-21 | Advanced Semiconductor Eng | Thermal enhance MCM package |
US6861288B2 (en) * | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
US6815254B2 (en) * | 2003-03-10 | 2004-11-09 | Freescale Semiconductor, Inc. | Semiconductor package with multiple sides having package contacts |
JP3917946B2 (en) * | 2003-03-11 | 2007-05-23 | 富士通株式会社 | Multilayer semiconductor device |
TWI311353B (en) * | 2003-04-18 | 2009-06-21 | Advanced Semiconductor Eng | Stacked chip package structure |
JP2004327855A (en) | 2003-04-25 | 2004-11-18 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
US6888255B2 (en) * | 2003-05-30 | 2005-05-03 | Texas Instruments Incorporated | Built-up bump pad structure and method for same |
TWI297938B (en) * | 2003-07-15 | 2008-06-11 | Advanced Semiconductor Eng | Semiconductor package |
KR100493063B1 (en) * | 2003-07-18 | 2005-06-02 | 삼성전자주식회사 | BGA package with stacked semiconductor chips and manufacturing method thereof |
US7015571B2 (en) * | 2003-11-12 | 2006-03-21 | Advanced Semiconductor Engineering, Inc. | Multi-chips module assembly package |
TWI227555B (en) * | 2003-11-17 | 2005-02-01 | Advanced Semiconductor Eng | Structure of chip package and the process thereof |
US7345361B2 (en) * | 2003-12-04 | 2008-03-18 | Intel Corporation | Stackable integrated circuit packaging |
US7187068B2 (en) * | 2004-08-11 | 2007-03-06 | Intel Corporation | Methods and apparatuses for providing stacked-die devices |
US20060073635A1 (en) | 2004-09-28 | 2006-04-06 | Chao-Yuan Su | Three dimensional package type stacking for thinner package application |
JP4409455B2 (en) * | 2005-01-31 | 2010-02-03 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
US7408244B2 (en) * | 2005-03-16 | 2008-08-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and stack arrangement thereof |
TWI257135B (en) * | 2005-03-29 | 2006-06-21 | Advanced Semiconductor Eng | Thermally enhanced three dimension package and method for manufacturing the same |
US7364945B2 (en) * | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
TWI442520B (en) * | 2005-03-31 | 2014-06-21 | Stats Chippac Ltd | Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides |
KR101172527B1 (en) * | 2005-03-31 | 2012-08-10 | 스태츠 칩팩, 엘티디. | Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides |
US7354800B2 (en) * | 2005-04-29 | 2008-04-08 | Stats Chippac Ltd. | Method of fabricating a stacked integrated circuit package system |
JP4322844B2 (en) * | 2005-06-10 | 2009-09-02 | シャープ株式会社 | Semiconductor device and stacked semiconductor device |
TWI267967B (en) * | 2005-07-14 | 2006-12-01 | Chipmos Technologies Inc | Chip package without a core and stacked chip package structure using the same |
US20070108583A1 (en) * | 2005-08-08 | 2007-05-17 | Stats Chippac Ltd. | Integrated circuit package-on-package stacking system |
TWI285423B (en) * | 2005-12-14 | 2007-08-11 | Advanced Semiconductor Eng | System-in-package structure |
TWI281236B (en) * | 2005-12-16 | 2007-05-11 | Advanced Semiconductor Eng | A package structure with a plurality of chips stacked each other |
US7288835B2 (en) * | 2006-03-17 | 2007-10-30 | Stats Chippac Ltd. | Integrated circuit package-in-package system |
TWI301315B (en) * | 2006-04-13 | 2008-09-21 | Advanced Semiconductor Eng | Substrate structure having solder mask layer and process for making the same |
US7498667B2 (en) * | 2006-04-18 | 2009-03-03 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
TWI309079B (en) * | 2006-04-21 | 2009-04-21 | Advanced Semiconductor Eng | Stackable semiconductor package |
US7242081B1 (en) * | 2006-04-24 | 2007-07-10 | Advanced Semiconductor Engineering Inc. | Stacked package structure |
US7714453B2 (en) * | 2006-05-12 | 2010-05-11 | Broadcom Corporation | Interconnect structure and formation for package stacking of molded plastic area array package |
TWI298198B (en) * | 2006-05-30 | 2008-06-21 | Advanced Semiconductor Eng | Stackable semiconductor package |
US8581381B2 (en) * | 2006-06-20 | 2013-11-12 | Broadcom Corporation | Integrated circuit (IC) package stacking and IC packages formed by same |
KR100800478B1 (en) * | 2006-07-18 | 2008-02-04 | 삼성전자주식회사 | Stack type semiconductor package and method of fabricating the same |
TWI317993B (en) * | 2006-08-18 | 2009-12-01 | Advanced Semiconductor Eng | Stackable semiconductor package |
TWI335658B (en) * | 2006-08-22 | 2011-01-01 | Advanced Semiconductor Eng | Stacked structure of chips and wafer structure for making same |
TWI336502B (en) * | 2006-09-27 | 2011-01-21 | Advanced Semiconductor Eng | Semiconductor package and semiconductor device and the method of making the same |
TWI312561B (en) * | 2006-10-27 | 2009-07-21 | Advanced Semiconductor Eng | Structure of package on package and method for fabricating the same |
TW200828528A (en) * | 2006-12-19 | 2008-07-01 | Advanced Semiconductor Eng | Structure for packaging electronic components |
JP5114130B2 (en) | 2007-08-24 | 2013-01-09 | 新光電気工業株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE |
TWI356482B (en) * | 2007-09-20 | 2012-01-11 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method the |
TWI473553B (en) * | 2008-07-03 | 2015-02-11 | Advanced Semiconductor Eng | Chip package structure |
US7750455B2 (en) * | 2008-08-08 | 2010-07-06 | Stats Chippac Ltd. | Triple tier package on package system |
TW201023308A (en) * | 2008-12-01 | 2010-06-16 | Advanced Semiconductor Eng | Package-on-package device, semiconductor package and method for manufacturing the same |
US20100171206A1 (en) * | 2009-01-07 | 2010-07-08 | Chi-Chih Chu | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same |
US8012797B2 (en) * | 2009-01-07 | 2011-09-06 | Advanced Semiconductor Engineering, Inc. | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries |
TWI469283B (en) * | 2009-08-31 | 2015-01-11 | Advanced Semiconductor Eng | Package structure and package process |
US8198131B2 (en) * | 2009-11-18 | 2012-06-12 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor device packages |
-
2009
- 2009-01-07 TW TW098100325A patent/TWI499024B/en active
- 2009-07-22 US US12/507,305 patent/US8076765B2/en active Active
-
2011
- 2011-11-07 US US13/290,819 patent/US20120049338A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060244117A1 (en) * | 2005-04-29 | 2006-11-02 | Stats Chippac, Ltd. | Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides |
US7777351B1 (en) * | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130200509A1 (en) * | 2012-02-02 | 2013-08-08 | Samsung Electronics Co., Ltd. | Semiconductor package |
US9077878B2 (en) | 2012-04-17 | 2015-07-07 | Apple Inc. | Alternative lens insertion methods and associated features for camera modules |
US8902352B2 (en) | 2012-06-08 | 2014-12-02 | Apple Inc. | Lens barrel mechanical interference prevention measures for camera module voice coil motor design |
US8546932B1 (en) | 2012-08-15 | 2013-10-01 | Apple Inc. | Thin substrate PoP structure |
US8766424B2 (en) | 2012-08-15 | 2014-07-01 | Apple Inc. | Thin substrate PoP structure |
US9263426B2 (en) | 2012-09-26 | 2016-02-16 | Apple Inc. | PoP structure with electrically insulating material between packages |
US8963311B2 (en) | 2012-09-26 | 2015-02-24 | Apple Inc. | PoP structure with electrically insulating material between packages |
US9978715B2 (en) | 2013-06-14 | 2018-05-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor process |
CN104241215A (en) * | 2013-06-14 | 2014-12-24 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and semiconductor process |
US10229894B2 (en) | 2013-06-14 | 2019-03-12 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor process |
US20160276325A1 (en) * | 2014-09-18 | 2016-09-22 | Intel Corporation | Method of embedding wlcsp components in e-wlb and e-plb |
US9991239B2 (en) * | 2014-09-18 | 2018-06-05 | Intel Corporation | Method of embedding WLCSP components in e-WLB and e-PLB |
US10147710B2 (en) | 2014-09-18 | 2018-12-04 | Intel Corporation | Method of embedding WLCSP components in E-WLB and E-PLB |
TWI703704B (en) * | 2014-12-05 | 2020-09-01 | 南韓商三星電子股份有限公司 | Package on packages, mobile computing device and electronic device |
US20210288010A1 (en) * | 2015-03-24 | 2021-09-16 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and manufacturing method thereof |
CN107104055A (en) * | 2016-02-22 | 2017-08-29 | 日月光半导体制造股份有限公司 | Semiconductor device and its manufacture method |
EP3951870A1 (en) * | 2016-02-22 | 2022-02-09 | MEDIATEK Inc. | Method for forming a fan-out package structure |
US20190013299A1 (en) * | 2017-07-05 | 2019-01-10 | Sang-won Lee | Semiconductor packages |
US20200273718A1 (en) * | 2019-02-25 | 2020-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and manufacturing method thereof |
US11081369B2 (en) * | 2019-02-25 | 2021-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
US8076765B2 (en) | 2011-12-13 |
US20100171205A1 (en) | 2010-07-08 |
TW201027693A (en) | 2010-07-16 |
TWI499024B (en) | 2015-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8076765B2 (en) | Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors | |
US8012797B2 (en) | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries | |
US8198131B2 (en) | Stackable semiconductor device packages | |
US8278746B2 (en) | Semiconductor device packages including connecting elements | |
TWI474414B (en) | Stackable semiconductor device packages and semiconductor process | |
US7879653B2 (en) | Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same | |
US20100171206A1 (en) | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same | |
US8373277B2 (en) | Stacked die in die BGA package | |
US7709935B2 (en) | Reversible leadless package and methods of making and using same | |
US8659151B2 (en) | Semiconductor device and manufacturing method thereof | |
US20180114782A1 (en) | Manufacturing method of package-on-package structure | |
TWI495082B (en) | Multi-layer semiconductor package | |
TWI355034B (en) | Wafer level package structure and fabrication meth | |
US7132738B2 (en) | Semiconductor device having multiple semiconductor chips stacked in layers and method for manufacturing the same, circuit substrate and electronic apparatus | |
TWI469301B (en) | Semiconductor multi-package module having wire bond interconnection between stacked packages | |
US20070158809A1 (en) | Multi-chip package system | |
US20070141761A1 (en) | Method for fabricating semiconductor packages, and structure and method for positioning semiconductor components | |
TW201804575A (en) | Integrated fan-out package | |
JP2008277569A (en) | Semiconductor device and manufacturing method therefor | |
US20100052148A1 (en) | Package structure and package substrate | |
US11410935B2 (en) | Semiconductor package using cavity substrate and manufacturing methods | |
KR20020058208A (en) | Semiconductor package and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |