TWI283473B - Stack package structure and electrically-connected board for stack package - Google Patents

Stack package structure and electrically-connected board for stack package Download PDF

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Publication number
TWI283473B
TWI283473B TW091132911A TW91132911A TWI283473B TW I283473 B TWI283473 B TW I283473B TW 091132911 A TW091132911 A TW 091132911A TW 91132911 A TW91132911 A TW 91132911A TW I283473 B TWI283473 B TW I283473B
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Taiwan
Prior art keywords
package
electrical connection
pads
connection board
solder joint
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TW091132911A
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Chinese (zh)
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TW200408102A (en
Inventor
Bo-Ren Jeng
Shr-Jang Li
Yau-Shin Feng
Chi-Sheng Jung
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Advanced Semiconductor Eng
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Priority to TW091132911A priority Critical patent/TWI283473B/en
Publication of TW200408102A publication Critical patent/TW200408102A/en
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Publication of TWI283473B publication Critical patent/TWI283473B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The present invention relates to an electrically-connected board for stack package, which is disposed between the first package and the second package for electrically connecting with the first package and the second package. The electrically-connected board for stack package comprises: a top surface, a bottom surface, plural upper bonding pads and plural lower bonding pads. The upper bonding pads are formed on the top surface, and the surface of each upper bonding pad has a tin-lead metal layer. Each upper bonding pad is electrically connected to the bonding pad of the first package disposed on the top surface of the electrically-connected board through a soldering contact. The surface of the lower bonding pad has a tin-lead metal layer, and each lower bonding pad is electrically connected to the bonding pad of the second package disposed on the bottom surface of the electrically-connected board through a soldering contact. Therefore, there is no gold-tin-nickel metal layer formed on the electrically-connected board of the present invention, the lifetime of the soldering contact is increased, and the electrical characteristics are better.

Description

12834731283473

免明背景 1 ·發明領域 本發明係關於一種堆疊封裝結構，詳言之，係關於一種 利用電性連接板之堆疊封裝結構及用於堆疊封裝之電性連 接板。 2 ·先前技術說明 參考圖1，習用之堆疊封裝結構包括一第一封裝體 II、 一電性連接板12及一第二封裝體13 ^該第一封裝體u 可為一薄型球閘封裝體（VFBGA)，其具有複數個銲墊 III、 112。該電性連接板12具有一頂面121及一底面 122。該頂面121形成有複數個上銲墊123等。該底面ι22 形成有複數個下銲墊124等。該等上銲墊123與該等下銲墊 1 2 4係透過基板中之電跡線與導孔以電氣連接。該第二封裝 體13具有一晶片及複數個銲墊13ι、132。 利用一銲接點1 4 1，使該第一封裝體1 1之銲塾丨丨1與該電 性連接板12之上銲墊123電氣連接。再利用一銲接點丨42 , 使該電性連接板12之下銲墊124與該第二封裝體13之銲墊 131電氣連接。該第一封裝體丨丨與該第二封裝體13係藉由 電性連接板12以電氣連接。 參考圖2，該電性連接板12之下銲墊124之材質通常為銅 (Cu)，在該下銲墊丨24上會有一鎳（Ni)層125及一金 (Au)層126。同樣地，該第二封裝體13之銲墊131之材 質亦為銅（Cu)，在該鋅墊131上會有一鎳（Ni)層133及 一金（Au)層134。該銲接點142係為錫鉛（Sn/Pb)材 L___-5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 1283473 A7 B7 五、發明説明（ 料。 參考圖3，上述之結構經過迴焊（R e f 1 〇 w )製程後，最 表面之金層126及134以極快之速度進入銲接點142内反 應，其底下之鎳（Ni)層125及133則開始與銲接點142進 行反應’並生成Ni3Sn4介金屬層128及136 進入銲接點 142之金，則於銲接點H2内形成（AUbxNidSr^介金屬 129及137。然而，（Au^xNDSru會隨運作時間的增長而 回到銲接點142之介面，形成一連續之（Au1-xNix)Sn4介金 屬層129及137。（AUhNidSiu介金屬層129及137性質 不但極脆，且與NhSn4介金屬層128之介面強度不佳， 容易形成斷裂，使得銲接點之壽命縮短，且易造成電氣 特性不佳’甚至於造成可能無法達成電氣連接之問題。 因此，有必要提供一創新且富進步性的堆叠封裝結構， 以解決上述問題。 發明概述 本發明之目的在於提供一種用於堆疊封裝之電性連接 板，其係設置於一第一封裝體與一第二封裝體之間，用以 電性連接該第一封裝體與該第二封裝體，該用於堆叠封裝 之電性連接板包括：一頂面、一底面、複數個上錦塾及複 數個下銲墊。該等上銲墊係形成於該頂面，各該上銲整之 表面具有一錫鉛金屬層，各該上銲墊係利用一銲接點，俾 與設置於該電性連接板頂面上之該第一封裝體之銲塾電氣 連接。該等下銲墊係形成於該底面，各該下銲塾之表面具 有一錫錯金屬層’各該下銲塾係利用一銲接點，與設置於BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked package structure, and more particularly to a stacked package structure using an electrical connection board and an electrical connection board for stacking packages. 2. Prior art description Referring to FIG. 1, a conventional stacked package structure includes a first package body II, an electrical connection board 12, and a second package body 13. The first package body u can be a thin ball gate package. (VFBGA) having a plurality of pads III, 112. The electrical connecting plate 12 has a top surface 121 and a bottom surface 122. The top surface 121 is formed with a plurality of upper pads 123 and the like. The bottom surface ι22 is formed with a plurality of lower pads 124 and the like. The upper pads 123 and the lower pads 1 24 are electrically connected to the vias and vias in the substrate. The second package 13 has a wafer and a plurality of pads 131, 132. The solder bump 1 of the first package body 1 is electrically connected to the solder pad 123 of the electrical connection board 12 by a solder joint 141. Then, a solder pad 42 is used to electrically connect the pad 124 under the electrical connection board 12 to the pad 131 of the second package 13. The first package body 丨丨 and the second package body 13 are electrically connected by an electrical connection plate 12. Referring to FIG. 2, the material of the solder pad 124 under the electrical connection board 12 is usually copper (Cu). On the lower pad 24, a nickel (Ni) layer 125 and a gold (Au) layer 126 are provided. Similarly, the pad 131 of the second package 13 is also made of copper (Cu). On the zinc pad 131, a nickel (Ni) layer 133 and a gold (Au) layer 134 are present. The solder joint 142 is tin-lead (Sn/Pb) material L___-5- This paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 1283473 A7 B7 V. Description of invention (Material. Refer to Figure 3 After the above structure is subjected to the reflow process (R ef 1 〇w ), the outermost gold layers 126 and 134 enter the solder joint 142 at a very fast rate, and the underlying nickel (Ni) layers 125 and 133 start. The reaction with the solder joint 142 and the formation of the Ni3Sn4 intermetallic layer 128 and 136 into the solder joint 142 is formed in the solder joint H2 (AUbxNidSr^Metal 129 and 137. However, (Au^xNDSru will follow the operation time) The interface is grown back to solder joint 142 to form a continuous (Au1-xNix)Sn4 intermetallic layer 129 and 137. (The properties of AUhNidSiu intermetallic layers 129 and 137 are not only extremely brittle, but also interface strength with NhSn4 intermetallic layer 128. Poor, easy to form fractures, shortening the life of solder joints, and easily causing poor electrical characteristics' even causing problems that may not be able to achieve electrical connection. Therefore, it is necessary to provide an innovative and progressive stacking package structure, Solve the above problem. SUMMARY OF THE INVENTION An object of the present invention is to provide an electrical connection board for a package, which is disposed between a first package and a second package for electrically connecting the first package and the first The second package body comprises: a top surface, a bottom surface, a plurality of upper koi and a plurality of lower pads. The upper pads are formed on the top surface, each of the upper pads The surface of the soldered surface has a tin-lead metal layer, and each of the upper pads is electrically connected to the solder bump of the first package disposed on the top surface of the electrical connection board by a solder joint. a pad is formed on the bottom surface, and each of the lower soldering pads has a tin-staggered metal layer on the surface of each of the lower pads; each of the lower soldering systems utilizes a solder joint and is disposed on

1283473 A71283473 A7

該電性連接板底面下之該第二封裝體之銲墊電氣連接。 各該上銲墊及下銲墊表面之錫鉛金屬層，可置換為貴金 屬（例如：金）或是有機層。因此，利用本發明之該電性 連接板，不會形成（Au^xN^Sri4介金屬層，故可使得銲 接點之壽命提高，並具有較佳之電氣特性。 圖式簡述 圖1為習用堆疊封裝結構之示意圖； 圖2為習用堆疊封裝結構中電性連接板與第二封裝體連 接之局部放大示意圖； 圖3為習用堆疊封裝結構中電性連接板與第二封裝體連 接經迴銲後產生裂鍵之局部放大示意圖； 圖4為本發明之堆疊封裝結構之示意圖；及 圖5為本發明之堆疊封裝結構中電性連接板與第二封裝 體連接之局部放大示意圖。 圖式元件符號說明 10 :習知堆疊封裝結構 11 :第一封裝體 1 1 1、1 12 :銲墊 12 :電性連接板 121 :頂面 122 :底面 123 :上銲墊 124 :下銲墊 125 :鎳層 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1283473 A7 B7 五、發明説明（4 ) 126 :金層 128 :錫鎳層 129 :金錫鎳層 13 :第二封裝體 13 1、132 :銲墊 133 :鎳層 134 :金層 136 :錫鎳層 137 :金錫鎳層 141、142 :銲接點 20 :本發明堆疊封裝結構 21 :第一封裝體 21 1、212 :銲墊 22 :電性連接板 2 2 1 :頂面 222 ·•底面 22 3 ··上銲墊 224 :下銲墊 226 :鉛錫金屬層 23 :第二封裝體 23 1、232 :銲墊 2 4 1、2 4 2 :銲接點 發明詳述 請參閱圖4，其顯示本發明之堆疊封裝結構20。該堆疊 _-JB-___ 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 1283473 A7 B7 五、發明説明（5 ) 封裝結構2 0包括一第一封裝體21、一電性連接板22及一第 二封裝體23。該第一封裝體21可為一薄型球閘封裝體 (VFBGA)，其具有一晶片及複數個銲墊211、212。該電 性連接板22具有一頂面221及一底面222。該頂面221形成 有複數個上銲塾223等。該底面222形成有複數個下銲整 224等。該第二封裝體23具有一晶片及複數個銲塾231、 232 ° 利用一銲接點241，如錫球（solder ball)，使該第一封 裝體21之銲墊211與該電性連接板22之上銲墊223電氣連 接。再利用一銲接點242，使與該電性連接板22之下銲勢 224與該第二封裝體23之銲墊231電氣連接。此電性連接板 22可使第一封裝體21與第二封裝體23電性連接。 參考圖5，該電性連接板22之下銲墊224之材質通常為銅 (Cu)，本發明之該電性連接板22於該下銲墊224上形成一 錫錯（Sn/Pb )金屬層226作為表面處理層，例如以預銲 (presolder)方式形成，以防下銲墊224氧化。同樣地，該 電性連接板22之該上銲墊223上形成一錫鉛（Sn/Pb)金屬 層（圖未示出）。由於該銲接點242亦為錫鉛（Sn/Pb )材 料’因此，當本發明之堆疊封裝結構經過迴銲（Refl〇w) 製程後，該錫鉛金屬層226易於與該銲接點結合，且由於沒 有習知結構中之（Au^xNMSru介金屬層形成，故可使得 銲接點2 4 2之壽命提高，並具有較佳之電氣特性。 各該上銲墊223及下銲墊224之表面不限於僅能形成該錫 錯金屬層。該錫鉛金屬層可置換為貴金屬（例如：金）或 Ϊ紙張尺度適用中國國家標準(CNS) A4規格(210X297公董）9 -- 1283473 A7 B7 五、發明說明（6 ) 是有機層。當各該上銲墊223及下銲墊224之表面形成一貴 金屬層（例如：金）時，經過迴銲製程後，該銲墊上亦不 會有習知結構中之（Au^xNidSru介金屬層，故亦不會產 生有裂鍵之問題，同樣地可達到使得銲接點之壽命提 南’及具有較佳之電氣特性之功效。 另外，當各該上銲墊223及下銲墊224之表面形成一有機 層時，經過迴銲製程後，該有機層會揮發消失，因此不會 有習知結構中之（Au^NDSii4介金屬層存在，可解決習 知結構中因該（Aui-xNix)Sn4介金屬層所導致之問題。此 外，第一封裝體21之銲墊211及第二封裝體23之銲墊231 之表面仍可為鍵有錄金之處理層，或於與電性連接板22電 性連接之銲墊處，其表面處理層改為鉛錫金屬層、貴金屬 層、或有機層。 利用該電性連接板，本發明堆疊封裝結構之電氣特性 可以大幅地改善，使得第一封裝體與第二封裝體間具有 良好的電氣連接特性。並使得該第一封裝體與該電性連 接板，以及該電性連接板與該第二封裝體間之銲接點壽 命提高。 惟上述實施例僅為說明本發明之原理及其功效，而非限 制本發明。因此，習於此技術之人士可在不達背本發明之 精神對上述實施例進行修改及變化。本發明之權利範圍應 如後述之申請專利範圍所列^The pads of the second package under the bottom surface of the electrical connection board are electrically connected. The tin-lead metal layer on the surface of each of the upper and lower pads may be replaced by a noble metal (for example, gold) or an organic layer. Therefore, with the electrical connecting plate of the present invention, the metal layer is not formed (Au^xN^Sri4 metal layer), so that the life of the solder joint can be improved and the electrical characteristics are better. FIG. 1 is a conventional stacking. FIG. 2 is a partially enlarged schematic view showing the connection between the electrical connection board and the second package body in the conventional stacked package structure; FIG. 3 is a view showing the connection between the electrical connection board and the second package body in the conventional stacked package structure after reflow soldering FIG. 4 is a schematic view showing a portion of the stacked package structure of the present invention; and FIG. 5 is a partially enlarged schematic view showing the connection of the electrical connection plate and the second package in the stacked package structure of the present invention. Description 10: conventional stacked package structure 11: first package body 1 1 1 , 1 12 : pad 12 : electrical connection plate 121 : top surface 122 : bottom surface 123 : upper pad 124 : lower pad 125 : nickel layer This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1283473 A7 B7 V. Invention description (4) 126: Gold layer 128: tin-nickel layer 129: gold-tin-nickel layer 13: second package 13 1 , 132: pad 133: nickel 134: gold layer 136: tin-nickel layer 137: gold-tin-nickel layer 141, 142: solder joint 20: stacked package structure 21 of the present invention: first package body 21 1, 212: pad 22: electrical connection plate 2 2 1 : top Surface 222 ·•Back surface 22 3 ··Upper pad 224 : Lower pad 226 : Lead-tin metal layer 23 : Second package 23 1 , 232 : Pad 2 4 1 , 2 4 2 : Soldering point Details of the invention Referring to Figure 4, there is shown a stacked package structure 20 of the present invention. The stack _-JB-___ This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1283473 A7 B7 V. Description of the invention (5) Package structure The second package body 21 includes a first package body 21, an electrical connection board 22, and a second package body 23. The first package body 21 can be a thin ball gate package (VFBGA) having a wafer and a plurality of solders. Pads 211, 212. The electrical connecting plate 22 has a top surface 221 and a bottom surface 222. The top surface 221 is formed with a plurality of upper soldering 223, etc. The bottom surface 222 is formed with a plurality of lower soldering 224, etc. The second package 23 has a wafer and a plurality of soldering pads 231, 232 ° using a solder joint 241, such as a solder ball, to make the first seal The solder pad 211 of the body 21 is electrically connected to the solder pad 223 of the electrical connecting board 22. The soldering point 242 is used to solder the soldering potential 224 and the second package 23 below the electrical connecting board 22. Pad 231 is electrically connected. The electrical connection board 22 can electrically connect the first package body 21 and the second package body 23. Referring to FIG. 5, the material of the solder pad 224 under the electrical connection board 22 is usually copper (Cu). The electrical connection board 22 of the present invention forms a tin (Pn/Pb) metal on the lower pad 224. Layer 226 is formed as a surface treatment layer, for example, in a presolder manner to prevent oxidation of lower pad 224. Similarly, a tin-lead (Sn/Pb) metal layer (not shown) is formed on the upper pad 223 of the electrical connection board 22. Since the solder joint 242 is also a tin-lead (Sn/Pb) material, the tin-lead metal layer 226 is easily bonded to the solder joint after the stacked package structure of the present invention is subjected to a reflow process. Since there is no conventional structure (Au^xNMSru metal layer is formed, the life of the solder joint 24 2 2 is improved, and the electrical characteristics are better. The surfaces of the upper solder pad 223 and the lower solder pad 224 are not limited. Only the tin metal layer can be formed. The tin-lead metal layer can be replaced with a precious metal (for example: gold) or a paper scale applicable to the Chinese National Standard (CNS) A4 specification (210X297 public) 9 -- 1283473 A7 B7 V. Invention (6) is an organic layer. When a surface of each of the upper pad 223 and the lower pad 224 forms a precious metal layer (for example, gold), after the reflow process, the pad does not have a conventional structure. (Au^xNidSru is a metal layer, so there is no problem of cracking bonds, and the effect of making the soldering point life up to the south and having better electrical characteristics can be achieved. In addition, when each of the upper pads 223 And when the surface of the lower pad 224 forms an organic layer After the reflow process, the organic layer will volatilize and disappear, so there is no known structure (Au^NDSii4 intermetallic layer exists, which can solve the (Aui-xNix) Sn4 intermetallic layer in the conventional structure. The surface of the pad 211 of the first package 21 and the pad 231 of the second package 23 can still be a processing layer with a gold-plated bond or electrically connected to the electrical connection board 22. At the pad, the surface treatment layer is changed to a lead-tin metal layer, a precious metal layer, or an organic layer. With the electrical connection plate, the electrical characteristics of the stacked package structure of the present invention can be greatly improved, so that the first package and the second package The package has good electrical connection characteristics, and the solder joint life between the first package and the electrical connection board, and between the electrical connection board and the second package is improved. The present invention may be modified and changed without departing from the spirit and scope of the invention, and the scope of the present invention should be applied as described below. patent Wai listed ^

Claims (1)

1283473 A8 B81283473 A8 B8 •-種用於堆叠封裝之電性連接板，係設置於_第一封裝 體與-第二封裝體之間，用以電性連接該第一封裝體與 該第一封裝體，該用於堆疊封裝之電性連接板包括： 一頂面及一底面； 複數個上銲墊，形成於該頂面，各該上銲墊之表面具 有一錫鉛金屬層，各該上銲墊係利用一銲接點，與設置 於該電性連接板頂面上之該第一封裝體電氣連接；及 複數個下銲墊，形成於該底面，各該下銲墊之表面具 有一錫鉛金屬層，各該下銲墊係利用一銲接點，與設置 於該電性連接板底面下之該第二封裝體電氣連接。 2·如申請專利範圍第”頁之電性連接板，纟中該銲接點為 一锡球。 3 ·如申請專利範圍第丨項之電性連接板，其中該第一封裝 to為球閘型封裝體（BGA)，具有與該銲接點接合之一銲 塾。 4.如申請專利範圍第丨項之電性連接板，其中該第二封裝 體為球閘型封裝體（BGA)，具有與該銲接點接合之一銲 墊。 5· —種用於堆疊封裝之電性連接板，係設置於一第一封裝 體與一第二封裝體之間，用以電性連接該第一封裝體與 該第一封裝體，該用於堆叠封裝之電性連接板包括： 一頂面及一底面； •複數個上銲塾，形成於該頂面，各該上銲墊之表面具 有一貴金屬層，各該上銲墊係利用一銲接點，與設置於 -11 -An electrical connection board for the package is disposed between the first package and the second package for electrically connecting the first package and the first package. The electrical connection board of the stacked package comprises: a top surface and a bottom surface; a plurality of upper pads formed on the top surface, each of the upper pads has a tin-lead metal layer, and each of the upper pads uses one a solder joint electrically connected to the first package disposed on a top surface of the electrical connection board; and a plurality of lower pads formed on the bottom surface, each of the lower pads having a tin-lead metal layer on each surface The lower pad is electrically connected to the second package disposed under the bottom surface of the electrical connection board by a solder joint. 2. If the electrical connection plate of the patent application page is applied, the solder joint is a solder ball. 3 · The electrical connection plate according to the scope of the patent application, wherein the first package is a ball gate type A package (BGA) having a solder joint bonded to the solder joint. 4. The electrical connection board according to claim 2, wherein the second package is a ball gate type package (BGA) having The solder joint is bonded to one of the solder pads. The electrical connection board for stacking is disposed between a first package and a second package for electrically connecting the first package And the first package, the electrical connection board for the package includes: a top surface and a bottom surface; • a plurality of upper soldering pads formed on the top surface, each of the upper pads has a precious metal layer Each of the upper pads is utilized with a solder joint, and is placed at -11 - 1283473 、申請專利範園 孩電性連接板頂面上之該第一封裝體電氣連接；及 魏個下鮮墊，形成於該底面，各該下銲塾之表面且 有:貴金屬層，各該下_係利用_銲接點，與設置於 该电性連接板底面下之該第二封裝體電氣連接。 6.如申請專利第5項之電性連接板，其中該貴金屬為 金。 t請㈣_第5項之電性連接板’纟中該鲜接點為 一錫球。 8. 如申請專利範圍第5項之電性連接板，纟中該第一封裝 體為球閘型封裝體(BGA) ’具有與該銲接點接合之一銲 墊。 9. 如申請專利範圍第5項之電性連接板，其中該第二封裝 Sa為球閘型封裝髏（BGA)，具有與該銲接點接合之一銲 塾。 10· —種用於堆疊封裝之電性連接板，係設置於一第一封裝 體與一第二封裝體之間，用以電性連接該第一封裝體與 該第二封裝體，該用於堆疊封裝之電性連接板，包括： 一頂面及一底面； 複數個上銲墊，形成於該頂面，各該上銲墊之表面具 有一有機層，各該上銲墊係利用一銲接點，與設置於該 電性連接板頂面上之該第一封裝體電氣連接；及 複數個下銲墊，形成於該底面，各該下銲墊之表面具 有一有機層，各該下銲墊係利用一銲接點，與設置於該 電性連接板底面下之該第二封裝體電氣連接。 -12- 本紙張尺度逋用中國國家標準(CNS) A4規格(21〇Χ297公釐） 12834731283473, the first package body electrical connection on the top surface of the patented electrical connection plate of the patent garden; and the Wei fresh underlying pad are formed on the bottom surface, and the surface of each of the lower soldering pads has: a precious metal layer, each of which The lower layer is electrically connected to the second package disposed under the bottom surface of the electrical connection board by using a solder joint. 6. The electrical connecting plate of claim 5, wherein the precious metal is gold. t Please (4) _ the electrical connection plate of item 5, the fresh contact is a solder ball. 8. The electrical connection plate of claim 5, wherein the first package is a ball gate type package (BGA)' having one of the pads bonded to the solder joint. 9. The electrical connection plate of claim 5, wherein the second package Sa is a ball gate type package (BGA) having a solder joint bonded to the solder joint. An electrical connection board for a stacked package is disposed between a first package and a second package for electrically connecting the first package and the second package. The electrical connection board of the stacked package comprises: a top surface and a bottom surface; a plurality of upper pads formed on the top surface, each of the upper pads has an organic layer, and each of the upper pads uses one a solder joint electrically connected to the first package disposed on a top surface of the electrical connection board; and a plurality of lower pads formed on the bottom surface, each of the lower pads having an organic layer, each of the lower layers The pad is electrically connected to the second package disposed under the bottom surface of the electrical connection board by a solder joint. -12- The paper size is based on the Chinese National Standard (CNS) A4 specification (21〇Χ297 mm) 1283473 u·如申請專利範圍第10項之電性連接板，其中該銲接點為 一踢球。 12·如申請專利範圍第1〇項之電性連接板，其中該第一封裝 體為球閘型封裝體（BGA)，具有與該銲接點接合之一銲 墊〇 13·如申請專利範圍第1〇項之電性連接板，其中該第二封裝 體為球閘型封裝體（BGA)，具有與該銲接點接合之一銲 墊。 14· 一種堆疊封裝之結構，由上而下依序包括： 一第一封裝體，具有一晶片及複數個銲墊； 一如申請專利範圍第1項所記載之電性連接板；及 一第二封裝體，具有一晶片及複數個銲墊。 15· —種堆疊封裝之結構，由上而下依序包括： 一第一封裝體，具有一晶片及複數個銲墊； 一如申請專利範圍第5項所記載之電性連接板；及 一第二封裝體，具有一晶片及複數個銲塾。 16· —種堆疊封裝之結構，由上而下依序包括： 一第一封裝體，具有一晶片及複數個銲墊； 一如申請專利範圍第10項所記載之電性連接板；及 一第二封裝體，具有一晶片及複數個銲墊。 -13- 本纸張尺度咖t S國家標準(CNS) A4規格(21GX297公釐)u. The electrical connecting plate of claim 10, wherein the welding point is a kick. 12. The electrical connection plate of claim 1, wherein the first package is a ball gate type package (BGA) having a solder pad 接合 13 bonded to the solder joint. The electrical connection board of the first aspect, wherein the second package is a ball gate type package (BGA) having a pad bonded to the solder joint. A stacking package structure comprising: a first package body having a wafer and a plurality of solder pads; and an electrical connection board as described in claim 1; The second package has a wafer and a plurality of pads. The structure of the stacked package comprises, in order from top to bottom, a first package having a wafer and a plurality of pads; an electrical connection board as described in claim 5; The second package has a wafer and a plurality of solder bumps. The structure of the stacked package comprises: a first package having a wafer and a plurality of pads; and an electrical connection board as described in claim 10; The second package has a wafer and a plurality of pads. -13- This paper scale coffee t S national standard (CNS) A4 specification (21GX297 mm)
TW091132911A 2002-11-08 2002-11-08 Stack package structure and electrically-connected board for stack package TWI283473B (en)

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Publication number Priority date Publication date Assignee Title
TWI499024B (en) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same

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Publication number Priority date Publication date Assignee Title
TWI480989B (en) * 2012-10-02 2015-04-11 矽品精密工業股份有限公司 Semiconductor package and fabrication method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI499024B (en) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same

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