TWI224376B - Flip-chip bonding process - Google Patents
Flip-chip bonding process Download PDFInfo
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- TWI224376B TWI224376B TW092116215A TW92116215A TWI224376B TW I224376 B TWI224376 B TW I224376B TW 092116215 A TW092116215 A TW 092116215A TW 92116215 A TW92116215 A TW 92116215A TW I224376 B TWI224376 B TW I224376B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
1224376 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種覆晶接合製程，且特別是有關於 一種利用金屬導電柱（conductive metal column)作為 接合晶片與承載器之覆晶接合製程。 【先前技術】 覆晶接合技術（F 1 i p C h i p I n t e r c ο η n e c t Technology ，簡稱FC)乃是利用面陣列（area array)的 方式，將多個晶片塾（die pad)配置於晶片（die)之主 動表面（active surface)上，並在晶片墊上形成凸塊 (bump )，接著將晶片翻覆（f 1 i p )之後，再利用這些凸 塊來分別電性及機械性連接晶片之晶片墊至承載器 φ (carrier )上的接合墊（contact)，使得晶片可經由凸 塊而電性連接至承載器，並經由承載器之内部線路而電性 連接至外界之電子裝置。值得注意的是，由於覆晶接合技 術（F C )係可適用於高腳數（H i g h P i n C 〇 u n t )之晶片封 裝結構，並同時具有縮小晶片封裝面積及縮短訊號傳輸路 徑等諸多優點，所以覆晶接合技術目前已經廣泛地應用於 晶片封裝領域，常見應用覆晶接合技術之晶片封裝結構例 如有覆晶球格陣列型（F 1 i p C h i p B a 1 1 G r i d A r r a y， F C / B G A )及覆晶針格陣列型（F 1 i p C h i p P i n G r i d A r~ r a y ，F C / P G A )等型態之晶片封裝結構。 就覆晶接合技術而言，常見之凸塊包括錫鉛凸塊 · (solder bump )、金球凸塊（gold bump)、銅凸塊 (copper bump )、導電膠凸塊(conductive polymer1224376 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a flip-chip bonding process, and more particularly, to a flip-chip using a conductive metal column as a bonding wafer and a carrier. Bonding process. [Previous Technology] F 1 ip C hip I nterc ο n nect Technology (FC for short) is a method of using an area array to place multiple die pads on a die. ) On the active surface, and form bumps on the wafer pad, and then flip the wafer (f 1 ip), and then use these bumps to electrically and mechanically connect the wafer pad of the wafer to The contact pads on the carrier φ (carrier) enable the chip to be electrically connected to the carrier via the bumps, and to be electrically connected to the external electronic device via the internal circuit of the carrier. It is worth noting that because the flip-chip bonding technology (FC) is applicable to high pin count (H igh P in Count) chip packaging structures, and has many advantages such as reducing chip packaging area and shortening signal transmission paths, Therefore, the flip-chip bonding technology has been widely used in the field of chip packaging. Common chip packaging structures to which flip-chip bonding technology is applied include, for example, a flip-chip ball grid array type (F 1 ip C hip B a 1 1 G rid A rray, FC / BGA) and flip-chip pin array array (F 1 ip C hip P in Grid Array ~ FC / PGA) and other types of chip package structure. In terms of flip-chip bonding technology, common bumps include tin-lead bumps, gold bumps, copper bumps, and conductive polymer bumps.
11008twf.ptd 第6頁 1224376 五、發明說明（2) bump )以及高分子凸塊（polymer bump)等型態，其中又 以錫鉛凸塊應用最為廣泛，但相對地其製造過程也相當複 雜而繁瑣。由於晶片之晶片墊通常為鋁墊，而形成錫鉛凸 塊於晶片塾的表面之前，係先形成一凸塊底金屬層 (Under Bump Metallurgy， UBM)於晶片塾上，ώ 塊底金 屬層的製程非常冗長，其係由多層金屬依序形成，包括一 黏著層(adhesion layer )、 一 阻絕層(barrier layer ) 以及一沾錫層 （wetting layer)，用以防止錫錯凸塊 與晶片的銲墊接合性不佳而脫離，其中黏著層之材質例如 為鈦、鐫，而阻絕層之材質例如為絡，而沾錫層之材質例 如為銅、錄、金。然而，錫錯凸塊與晶片墊之間還是會| 生接合性不佳之介金屬化合物（Inter-Metallic Compound，I MC )，而降低晶片封裝結構的可靠度。此 外，錫鉛凸塊由於含有重金屬鉛，這對環境之衝擊較大， 且錫錯凸塊會產生α粒子，其對銲塾之接合性亦會造成負 面影響。 第1圖繪示習知一種利用銅柱作為晶片與承載器之凸 塊的覆晶封裝結構的示意圖。請參照第1圖，晶片1 〇 〇具有 多個晶片墊1 0 2 ，且晶片1 0 0之表面上利用電鍍銅的方式形 成多個銅柱104 (即銅凸塊）於晶片塾1 0 2上。此外’承載 器1 1 0具有多個接合墊1 1 2 ，其分別對應連接至晶片墊 1 0 2，且接合墊1 1 2上例如配置一預銲塊（銲料）1 1 4。當· 晶片1 0 0以覆晶接合的方式配置於承載器1 1 0上時，晶片墊 1 0 2之銅柱1 0 4的頂端藉由預銲塊1 1 4而間接接合於承載器11008twf.ptd Page 6 1224376 V. Description of the invention (2) bumps and polymer bumps, of which tin-lead bumps are the most widely used, but the manufacturing process is relatively complicated and relatively Tedious. Because the wafer pad of the wafer is usually an aluminum pad, before forming a tin-lead bump on the surface of the wafer, an under bump metallurgy (UBM) is first formed on the wafer. The process is very tedious. It is sequentially formed of multiple layers of metal, including an adhesion layer, a barrier layer, and a wetting layer to prevent solder bumps from soldering to the wafer. The pad has poor adhesion and is detached. The material of the adhesive layer is, for example, titanium, rhenium, the material of the barrier layer is, for example, copper, and the material of the tin layer is, for example, copper, copper, or gold. However, the inter-metallic compound (I MC) with poor bonding properties will still be produced between the tin bumps and the wafer pad, thereby reducing the reliability of the chip packaging structure. In addition, the tin-lead bumps contain heavy metal lead, which has a greater impact on the environment, and the tin bumps will generate alpha particles, which will also have a negative impact on the bonding properties of the solder. FIG. 1 is a schematic diagram showing a conventional flip-chip packaging structure using copper pillars as bumps of a wafer and a carrier. Please refer to FIG. 1. The wafer 100 has a plurality of wafer pads 102, and a plurality of copper pillars 104 (ie, copper bumps) are formed on the surface of the wafer 100 by electroplating copper on the wafer 100. on. In addition, the carrier 1 10 has a plurality of bonding pads 1 12 respectively connected to the wafer pads 102, and the bonding pads 1 12 are provided with, for example, a pre-soldering block (solder) 1 1 4. When the wafer 100 is arranged on the carrier 1 10 in a flip-chip bonding manner, the top end of the copper pillar 10 of the wafer pad 10 2 is indirectly bonded to the carrier by the pre-soldering block 1 1 4
11008twf.ptd 第7頁 1224376 五、發明說明（3) 1 1 ◦之接合墊1 1 2上，且於覆晶接合之後，更可填入一底膠 1 2 0至晶片1 0 0與承載器1 1 0之間，以緩衝晶片1 0 0與承載器 1 1 0之間因熱膨脹不匹配所產生之剪應力。此外，於覆晶 接合之前，銅柱104的表面可先鑛上一錄金層（未繪示）， 以避免銅柱104的表面與外界空氣接觸而氧化。由於銅柱 1 0 4之製程簡化，且相鄰二銅柱1 0 4之間的間距可小於習知 之球形凸塊，銅柱1 0 4之徑向尺寸亦可小於習知錫鉛凸塊 之徑向尺寸，因此可進一步增加晶片1 0 0與承載器1 1 0之間 的接點密度，以達到高接點數之晶片封裝結構。 值得注意的是，習知銅柱之端面與預銲塊之間係為一 平坦之接觸表面，其接合的可靠度將受到接觸面積的大# 而改變，因而如何提高銅柱之端面與預銲塊之間的接觸面 積，此乃是本發明首要克服之缺點。 【發明内容】 有鑑於此，本發明之目的就是在提供一種覆晶封裝製 程，其中晶片藉由金屬導電柱作為覆晶接合時之凸塊接 點，用以提升晶片與承載器之間的接點密度，並提高晶片 封裝結構之可靠度。 為達本發明之上述目的，本發明提出一種覆晶接合製 程，適用於將一第一晶片連接至一承載器，其中第一晶片 具有一主動表面及多個晶片墊，而這些晶片墊係配置於第 一晶片之主動表面，並且承載器具有一承載表面及多個Θ 合墊，而該些接合墊係配置於承載器之承載表面，此覆晶 接合製程至少包括下列步驟：首先，分別形成一第一金屬11008twf.ptd Page 7 1224376 V. Description of the invention (3) 1 1 ◦ on the bonding pad 1 1 2 and after the flip chip bonding, a primer 1 2 0 to the wafer 1 0 0 and the carrier can be filled. Between 1 1 0, the shear stress generated by the mismatch of thermal expansion between the wafer 1 0 0 and the carrier 1 1 0 is buffered. In addition, before the flip-chip bonding, a gold layer (not shown) may be deposited on the surface of the copper pillars 104 to avoid oxidation of the surface of the copper pillars 104 by contact with the outside air. Since the manufacturing process of the copper pillar 104 is simplified, and the distance between two adjacent copper pillars 104 can be smaller than the conventional spherical bump, the radial size of the copper pillar 104 can also be smaller than that of the conventional tin-lead bump. The radial size can further increase the contact density between the wafer 100 and the carrier 110 to achieve a chip package structure with a high number of contacts. It is worth noting that the end face of the copper pillar and the pre-soldering block are a flat contact surface. The reliability of the joint will be changed by the large contact area #, so how to improve the end face of the copper pillar and the pre-soldering. The contact area between the blocks is the first disadvantage overcome by the present invention. [Summary of the Invention] In view of this, the object of the present invention is to provide a flip-chip packaging process, in which the chip uses metal conductive posts as bump contacts when the flip-chip is bonded to improve the connection between the chip and the carrier. Dot density and improve the reliability of the chip package structure. In order to achieve the above object of the present invention, the present invention provides a flip-chip bonding process suitable for connecting a first wafer to a carrier, wherein the first wafer has an active surface and a plurality of wafer pads, and the wafer pads are configured On the active surface of the first chip, and the carrier has a carrier surface and a plurality of Θ pads, and the bonding pads are arranged on the carrier surface of the carrier, the flip-chip bonding process includes at least the following steps: first, forming a First metal
11008twf.ptd 第8頁 1224376 五、發明說明（4) 導電柱至第一晶片之這些晶片墊，其中這些第一金屬導電 柱之較遠離第一晶片的端面其表面積係形成大於第一金屬 導電柱之橫向截面積；接著分別形成一第一表面保護層於 這些第一金屬導電柱之表面；以及分別接合第一晶片之這 些第一金屬導電柱至承載器之接合墊。 基於上述，本發明因採用金屬導電柱作為晶片與承載 器之凸塊接點，且金屬導電柱之端面（頂端）其剖面輪廓 係呈增加表面接觸面積及結合力之不規則形狀，例如船錨 狀、曲面狀或階梯狀，使得金屬導電柱之端面與承載器之 接合墊之間的接觸面積增加，用以增加覆晶封裝結構之可 靠度。 φ 為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 【實施方式】 請參照第2〜4圖，其依序繪示本發明一較佳實施例之 一種覆晶接合製程的流程示意圖。首先，請參考第2圖， 晶片2 0 0具有一主動表面2 0 2以及多個晶片墊2 0 4 ，晶片墊 204配置於晶片200之主動表面202上，而晶片墊204之表面 上分別形成^一金屬導電柱’例如為銅柱2 0 6 ’以做為後續 覆晶接合之凸塊接點。其中，形成銅柱2 0 6的方法例如先 以無電解電鍍法，全面形成一種子層（未繪示）於主動表Λ 202上，接著再以電解電鍍法形成局部電鍍之銅層（即銅 柱）於晶片墊2 0 4之種子層之上，接著蝕刻任二相鄰之晶11008twf.ptd Page 8 1224376 V. Description of the invention (4) The wafer pads from the conductive pillars to the first wafer, wherein the surface areas of the first metal conductive pillars which are farther from the first wafer are larger than the first metal conductive pillars. A transverse cross-sectional area; then forming a first surface protection layer on the surfaces of the first metal conductive pillars; and respectively bonding the first metal conductive pillars of the first wafer to the bonding pads of the carrier. Based on the above, the present invention uses a metal conductive pillar as the bump contact between the wafer and the carrier, and the end surface (top end) of the metal conductive pillar has an irregular shape that increases the surface contact area and the bonding force, such as a ship anchor The shape, the curved shape or the step shape makes the contact area between the end surface of the metal conductive pillar and the bonding pad of the carrier increase, which is used to increase the reliability of the flip-chip packaging structure. φ In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Embodiment] Please refer to FIGS. 2 to 4 , Which sequentially shows a schematic flowchart of a flip-chip bonding process according to a preferred embodiment of the present invention. First, please refer to FIG. 2. The wafer 200 has an active surface 202 and a plurality of wafer pads 204. The wafer pad 204 is disposed on the active surface 202 of the wafer 200, and the wafer pad 204 is formed on the surface ^ A metal conductive pillar 'for example, a copper pillar 206' is used as a bump contact for subsequent flip-chip bonding. Among them, the method for forming the copper pillars 206 is, for example, firstly forming a sub-layer (not shown) on the active surface Λ 202 by electroless plating method, and then forming a locally plated copper layer (ie copper by electrolytic plating method). Pillar) on the seed layer of the wafer pad 204, and then etch any two adjacent crystals
11008twf.ptd 第9頁 1224376 五、發明說明（5) 片墊2 0 4之間的種子層，而保留覆蓋於晶片墊2 0 4上方的種 子層以及銅柱2 0 6 ，即形成第2圖之晶片結構。值得注意的 是，為增加銅柱206之端面206a的表面積，在電鍍的過程 中，銅柱2 0 6之端面2 0 6 a其剖面輪廓係呈增加表面接觸面 積及結合力之不規則形狀，例如呈船錫狀、曲面狀或階梯 狀，以增加後續覆晶接合之接觸面積。此外，當晶片2 0 0 之晶片墊204為銅墊時，不需先形成球底金屬層（UBM)， 即可進行電鍍銅柱（銅凸塊）之製程，以簡化製程之步 驟。 請參考第2圖，以船錨狀之銅柱2 0 6為例，銅柱2 0 6之 端面（頂端）206a其表面積大於銅柱206之橫向截面積# (即銅柱206之底端的橫向截面積）’因此當晶片200覆曰曰 接合至承載器2 1 0時（如第4圖所示），晶片墊2 0 4之銅柱 206的端面206a與承載器210之接合墊2 14可藉由較大的接 觸面積而增加其接合的可靠度。請參考第3圖，於覆晶接 合之前，晶片墊204之銅柱206的表面還形成一表面保護層 208，此表面保護層例如為錄金層，以避免銅柱206之表面 與外界空氣接觸而氧化。 接著請參考第4圖，承載器2 1 0例如為一線路基板 (circuit board )，其具有一承載表面212以及多個接合 墊214，接合墊214配置於承載器210之承載表面212上，且 晶片2 0 0之銅柱2 0 6以覆晶接合的方式分別接合至承載器φ 2 1 0之接合墊2 1 4。其中，於覆晶接合之前，更可分別形成 一預銲塊2 1 6至接合墊2 1 4之表面，或分別形成一預銲塊11008twf.ptd Page 9 1224376 V. Description of the invention (5) The seed layer between the wafer pad 2 0 4 and the seed layer covering the wafer pad 2 0 4 and the copper pillar 2 0 6 remain, that is to form the second figure Wafer structure. It is worth noting that in order to increase the surface area of the end surface 206a of the copper pillar 206, during the electroplating process, the cross-section profile of the copper pillar 206's end surface 2 06a has an irregular shape that increases the surface contact area and the bonding force. For example, it has a boat tin shape, a curved shape or a step shape to increase the contact area of subsequent flip-chip bonding. In addition, when the wafer pad 204 of the wafer 200 is a copper pad, the process of plating copper pillars (copper bumps) can be performed without first forming a ball-bottom metal layer (UBM) to simplify the manufacturing steps. Please refer to Figure 2. Taking the anchor-shaped copper pillar 206 as an example, the end surface (top end) 206a of the copper pillar 206 has a larger surface area than the lateral cross-sectional area of the copper pillar 206 # (that is, the bottom end of the copper pillar 206 is transverse (Cross-sectional area) 'Therefore, when the wafer 200 is bonded to the carrier 2 10 (as shown in FIG. 4), the end face 206a of the copper pillar 206 of the wafer pad 204 and the bonding pad 2 14 of the carrier 210 may Increases the reliability of its bonding with a larger contact area. Please refer to FIG. 3. Before the flip-chip bonding, a surface protective layer 208 is also formed on the surface of the copper pillars 206 of the wafer pad 204. This surface protective layer is, for example, a gold recording layer to prevent the surface of the copper pillars 206 from contacting the outside air And oxidation. Please refer to FIG. 4. The carrier 2 10 is, for example, a circuit board, which has a bearing surface 212 and a plurality of bonding pads 214. The bonding pads 214 are disposed on the bearing surface 212 of the carrier 210, and The copper pillars 2 0 6 of the wafer 2 0 are respectively bonded to the bonding pads 2 1 4 of the carrier φ 2 1 0 in a flip-chip bonding manner. Among them, before the flip-chip bonding, a pre-solder block 2 1 6 to a surface of the bonding pad 2 1 4 may be formed separately, or a pre-solder block may be separately formed.
11008twf.ptd 第10頁 1224376 五、發明說明（6) 216於銅柱206之端面，而銅柱206可藉由預銲塊216間接接 合至承載器2 1 0之接合墊2 1 4，其中預銲塊2 1 6之材質例如 為無錯銲料。當然，銅柱2 0 6亦可利用熱壓接合（t h e r m a 1 compression bonding )的方式，而連接至厚（載器210之接 合墊2 1 4上。此外，晶片2 0 0覆晶接合至承載器2 1 0之後， 更可填入一底膠2 2 0至晶片2 0 0與承載器21 0之間，用以緩 衝晶片2 0 0與承載器2 1 0之間因熱膨脹不匹配所產生之應力 集中的現象。 第5及6圖分別繪示兩種利用不同型態之銅柱之晶片封 裝結構的示意圖。請參考第5圖，銅柱2 0 7之端面2 0 7 a其剖 面輪廓例如為曲面狀，而銅柱207之端面207a其表面積大0 於銅柱207之橫向截面積，因此當晶片200與承載器210覆 晶接合時，銅柱2 0 7的端面2 0 7 a與承載器210之接合墊2 14 可藉由較大的接觸面積而增加其接合的可靠度。請參考第 6圖，銅柱2 0 9之端面2 0 9 a其剖面輪廓例如為階梯狀，而銅 柱209之端面209a其表面積大於銅柱209之橫向截面積，因 此當晶片2 0 0與承載器2 1 0覆晶接合時，銅柱2 0 9的端面 209a與承載器210之接合墊214可藉由較大的接觸面積而增 加其接合的可靠度。 請參考第7至9圖，其分別繪示三種利用不同型態之銅 柱之晶片封裝結構的示意圖。晶片封裝結構具有一第一晶· 片320以及一第二晶片330 ，其中第一晶片320堆疊於第 晶片3 3 0上，而第二晶片3 3 0配置於一線路基板3 1 0之承載 表面3 1 2上，且第二晶片3 3 0例如以導線接合（w i r e11008twf.ptd Page 10 1224376 V. Description of the invention (6) 216 is on the end face of the copper pillar 206, and the copper pillar 206 can be indirectly bonded to the bonding pad 2 1 4 of the carrier 2 1 0 through the pre-soldering block 216. The material of the solder bumps 2 1 6 is, for example, error-free solder. Of course, the copper pillar 2 0 6 can also be connected to the thick (the bonding pad 2 1 4 of the carrier 210 by means of thermo 1 compression bonding). In addition, the chip 2 0 chip is bonded to the carrier After 2 1 0, a primer 2 220 to wafer 2 0 and the carrier 2 0 can be filled to buffer the heat generated by the mismatch between the wafer 2 0 and the carrier 2 1 0. The phenomenon of stress concentration. Figures 5 and 6 respectively show two types of chip packaging structures using different types of copper pillars. Please refer to Figure 5, the copper pillar 2 0 7 end face 2 0 a a section profile example It is curved, and the end surface 207a of the copper pillar 207 has a larger surface area than the lateral cross-sectional area of the copper pillar 207. Therefore, when the wafer 200 is bonded to the carrier 210, the end surface 2 7 a of the copper pillar 207 and the bearing The bonding pad 2 14 of the device 210 can increase the reliability of its bonding by a larger contact area. Please refer to FIG. 6, the end surface 2 0 9 a of the copper pillar 2 0 9 has a step profile, for example, and the copper The end surface 209a of the pillar 209 has a larger surface area than the lateral cross-sectional area of the copper pillar 209, so when the wafer 2 0 and the carrier 2 1 0 cover When bonding, the end face 209a of the copper pillar 209 and the bonding pad 214 of the carrier 210 can increase the bonding reliability by a larger contact area. Please refer to Figures 7 to 9, which respectively show three different uses Schematic diagram of a chip package structure of a type of copper pillar. The chip package structure has a first wafer 320 and a second wafer 330, where the first wafer 320 is stacked on the third wafer 3 and the second wafer 3 3 0 is disposed on the load bearing surface 3 1 2 of a circuit substrate 3 1 0, and the second wafer 3 3 0 is, for example, wire-bonded (wire
11008twf.ptd 第11頁 1224376 五、發明說明（7) bonding )或覆晶接合的方式電性連接至線路基板3 1 0之接 合墊314。此外，第二晶片330之主動表面332還具有多個 晶片墊3 34，對應連接於第一晶片3 2 0之銅柱3 2 4，而銅柱 3 2 4之端面其剖面輪廓例如第7圖之船錨狀的銅柱3 2 4 ( a )、 第8圖之曲面狀的銅柱3 2 4 ( b )或第9圖之階梯狀的銅柱 324(c)。因此，銅柱324的端面與第二晶片330之晶片墊 3 3 4可藉由較大的接觸面積而增加其接合的可靠度。其 中，銅柱3 2 4於覆晶接合之前，其表面分別形成一表面保 護層（未繪示），此表面保護層例如為有機保護層（0SP )、無機保護層或鎳金層或其他具有氧化保護之金屬合金 層，用以避免金屬導電柱324之表面氧化。此外，於覆晶_ 接合之前，更可選擇性地形成一預銲塊3 3 6於晶片墊3 3 4之 上或金屬導電柱324之端面，且於覆晶接合之後，再填入 一底膠340至第一晶片320與第二晶片330之間。 請參考第1 〇至1 2圖，其分別繪示三種利用不同型態之 銅柱之晶片封裝結構的示意圖。晶片封裝結構具有一第一 晶片4 2 0以及一第二晶片4 3 0 ，其中第一晶片4 2 0堆疊於第 二晶片4 3 0上，且第二晶片4 3 0例如以導線接合或覆晶接合 的方式電性連接至一線路基板或導線架（未繪示）。此 外，第一晶片420之主動表面422具有多個第一銅柱424 ， 對應連接於第二晶片430之第二銅柱434 ，而第一晶片420 之第一銅柱424係分別經由第二銅柱434而電性連接至第 晶片4 3 0。另外，第一銅柱4 24與第二銅柱4 34之端面其剖 面輪廓例如第1 0圖之船錨狀的銅柱4 2 4 ( a )、4 3 4 ( a )、第1 111008twf.ptd Page 11 1224376 V. Description of the invention (7) Bonding) or flip-chip bonding is electrically connected to the bonding pad 314 of the circuit board 3 1 0. In addition, the active surface 332 of the second wafer 330 also has a plurality of wafer pads 3 34 corresponding to the copper pillars 3 2 4 connected to the first wafer 3 2 0, and the cross-sectional profile of the end face of the copper pillars 3 2 4 is shown in FIG. 7. An anchor-shaped copper pillar 3 2 4 (a), a curved copper pillar 3 2 4 (b) in FIG. 8 or a stepped copper pillar 324 (c) in FIG. 9. Therefore, the end face of the copper pillar 324 and the wafer pad 3 3 4 of the second wafer 330 can increase the reliability of their bonding by a larger contact area. Among them, before the bonding of the copper pillars 3 2 4, a surface protective layer (not shown) is respectively formed on the surface, and the surface protective layer is, for example, an organic protective layer (0SP), an inorganic protective layer or a nickel-gold layer or other An oxidation-protected metal alloy layer is used to prevent the surface of the metal conductive pillar 324 from being oxidized. In addition, before the flip-chip bonding, a pre-soldering block 3 3 6 can be selectively formed on the wafer pad 3 3 4 or the end surface of the metal conductive post 324, and after the flip-chip bonding, a bottom is filled. The glue 340 is between the first wafer 320 and the second wafer 330. Please refer to Fig. 10 to Fig. 12, which respectively show three types of chip packaging structures using different types of copper pillars. The chip package structure has a first chip 4 2 0 and a second chip 4 3 0, wherein the first chip 4 2 0 is stacked on the second chip 4 3 0 and the second chip 4 3 0 is bonded or covered with wires, for example. The crystal bonding method is electrically connected to a circuit substrate or a lead frame (not shown). In addition, the active surface 422 of the first wafer 420 has a plurality of first copper pillars 424 corresponding to the second copper pillars 434 connected to the second wafer 430, and the first copper pillars 424 of the first wafer 420 pass through the second copper, respectively. The pillar 434 is electrically connected to the third chip 430. In addition, the cross-sectional profiles of the end faces of the first copper pillar 4 24 and the second copper pillar 4 34 are, for example, the anchor-shaped copper pillars 4 2 4 (a), 4 3 4 (a), and 1 1 in FIG. 10.
11008twf.ptd 第12頁 1224376 五、發明說明（8) 圖之曲面狀的銅柱4 2 4 ( b )、4 3 4 ( b )或第1 2圖之階梯狀的銅 柱424(c) 、434(c)·，因此，第一銅柱424的端面與第二銅 柱434之端面可藉由較大的接觸面積而增加其接合的可靠 度。其中，第一銅柱424與第二銅柱434於覆晶接合之前， 兩者之表面分別形成一表面保護層（未纟會示），此表面保護 層例如為有機保護層或鎳金層，用以避免第一銅柱4 2 4以 及第二銅柱434之表面氧化。同樣，第一銅柱424與第二銅 柱4 34於覆晶接合之前，更可形成一預銲塊4 2 6於第一銅柱 424之端面或形成一預銲塊4 26於第二銅柱4 34之端面，且 於覆晶接合之後，再填入一底膠4 4 0至第一晶片4 2 0與第二 晶片4 3 ◦之間。 _ 再者，上述第7圖〜第12圖中，第一晶片420與第二晶 片430之接合方式可為第一銅柱4 24對應接合第二銅柱 434 ，或是第一晶片320之第一銅柱324對應接合第二晶片 3 3 0之晶片墊3 34 ，或是第二晶片4 3 0之第二銅柱4 3 4對應接 合第一晶片3 2 0之晶片墊3 2 4。 由上述說明可知，本發明之覆晶接合製程乃是先分別 形成一第一銅柱至第一晶片之晶片塾，其中第一銅柱之較 遠離第一晶片的端面其表面積係形成大於第一銅柱之橫向 截面積，用以增加後續覆晶接合之接觸面積；接著分別形 成一第一表面保護層於第一銅柱之表面，其中第一表面保 護層例如為有機保護層、無機保護層或鎳金層或其他具 氧化保護之金屬合金層，用以避免第一銅柱之表面氧化； 以及分別接合第一晶片之第一銅柱至承載器（或第二晶片11008twf.ptd Page 12 1224376 V. Description of the invention (8) Curved copper pillars 4 2 4 (b), 4 3 4 (b) or stepped copper pillars 424 (c) in Figure 12 434 (c). Therefore, the end surface of the first copper post 424 and the end surface of the second copper post 434 can increase the reliability of their joining by a larger contact area. Before the first copper pillar 424 and the second copper pillar 434 are bonded to each other, a surface protective layer (not shown) is formed on the surfaces of the two copper pillars 424, such as an organic protective layer or a nickel-gold layer. In order to avoid surface oxidation of the first copper pillar 4 2 4 and the second copper pillar 434. Similarly, before the first copper pillar 424 and the second copper pillar 4 34 are bonded together, a pre-solder block 4 2 6 can be formed on the end surface of the first copper pillar 424 or a pre-solder block 4 26 can be formed on the second copper. The end surface of the pillar 4 34 is filled with a primer 4 40 to the first wafer 4 2 0 and the second wafer 4 3 after the flip-chip bonding. _ Furthermore, in the above FIGS. 7 to 12, the bonding method of the first wafer 420 and the second wafer 430 may be the first copper pillar 4 24 corresponding to the second copper pillar 434 or the first wafer 320 A copper pillar 324 corresponds to the wafer pad 3 34 bonded to the second wafer 3 3 0, or a second copper pillar 4 3 4 of the second wafer 4 3 0 corresponds to the wafer pad 3 2 4 to be bonded to the first wafer 3 2 0. It can be known from the above description that the flip-chip bonding process of the present invention is to first form a wafer from a first copper pillar to a first wafer, wherein the surface area of the first copper pillar that is farther from the first wafer is larger than the first surface. The lateral cross-sectional area of the copper pillar is used to increase the contact area of the subsequent flip-chip bonding. Then, a first surface protective layer is formed on the surface of the first copper pillar, respectively. The first surface protective layer is, for example, an organic protective layer, an inorganic protective layer Or a nickel-gold layer or other metal alloy layer with oxidation protection to avoid surface oxidation of the first copper pillar; and respectively bonding the first copper pillar of the first wafer to the carrier (or the second wafer)
11008twf.ptd 第13頁 1224376 五、發明說明（9) )，而承載器之預銲塊（或是第二晶片之預銲塊及/或第 二銅柱）對應連接至第一銅柱。其中，第一晶片例如直接 連接至一線路基板，或是先堆疊於第二晶片上，而第二晶 片再配置於一線路基板上並與線路基板電性連接，以構成 單晶片之封裝結構或多晶片之封裝結構。 綜上所述，本發明之覆晶封裝製程具有下列優點： (1 )晶片可藉由金屬導電柱的端面所形成之增加表 面接觸面積及結合力之不規則形狀，例如呈船錨形、曲面 形或階梯形之較大表面積，來增加與承載器（或第二晶片 )之間的接觸面積，並增加覆晶接合的可靠度。 (2 )晶片可藉由金屬導電柱作為覆晶接合時之凸塊· 接點，以增加晶片與承載器之間的接點密度。 (3 )由於金屬導電柱之徑向尺寸可小於習知錫鉛凸 塊之徑向尺寸，因此填入底膠於金屬導電柱之間的空間 時，將使底膠之流動更為順暢以及快速。 (4 )金屬導電柱相對於錫鉛凸塊具有較佳之導電性 且與晶片墊或接合墊之接合性較佳，故可克服習知錫鉛凸 塊容易倒塌或接觸不良等缺點。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 ®11008twf.ptd Page 13 1224376 V. Description of the invention (9)), and the pre-solder block of the carrier (or the pre-solder block of the second wafer and / or the second copper pillar) is correspondingly connected to the first copper pillar. The first chip is, for example, directly connected to a circuit substrate, or is first stacked on a second chip, and the second chip is then disposed on a circuit substrate and electrically connected to the circuit substrate to form a single-chip package structure or Multi-chip packaging structure. In summary, the flip-chip packaging process of the present invention has the following advantages: (1) The wafer can be formed by the end face of the metal conductive pillar to increase the surface contact area and the irregular shape of the bonding force, such as a ship anchor shape, a curved surface Shape or stepped surface area to increase the contact area with the carrier (or the second wafer) and increase the reliability of flip-chip bonding. (2) The chip can use metal conductive pillars as bumps and contacts during flip-chip bonding to increase the density of the contacts between the chip and the carrier. (3) Since the radial size of the metal conductive pillar can be smaller than the radial size of the conventional tin-lead bumps, when filling the space between the primer and the metal conductive pillar, the flow of the primer will be smoother and faster. . (4) Metal conductive pillars have better conductivity than tin-lead bumps and better bonding with wafer pads or bonding pads, so it can overcome the shortcomings of conventional tin-lead bumps that are easy to collapse or have poor contact. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ®
11008twf.ptd 第14頁 1224376 圖式簡單說明 第1圖繪示習知一種利用銅柱作為晶片與承載器之凸 塊的覆晶封裝結構的示意圖。 第2〜4圖依序繪示本發明一較佳實施例之一種覆晶接 合製程的流程示意圖。 第5及6圖分別繪示兩種利用不同型態之銅柱之晶片封 裝結構的示意圖。 第7至9圖分別繪示三種利用不同型態之銅柱之晶片封 裝結構的示意圖。 第1 0至1 2圖分別繪示三種利用不同型態之銅柱之晶片 封裝結構的示意圖。 【圖式標示說明】 100 晶 片 102 晶 片 墊 1 04 銅 柱 110 承 載 器 112 接 合 墊 1 14 預 銲 塊 120 底 膠 200 晶 片 202 主 動 表 面 204 晶 片 墊 2 0 6、 ‘20 7， 、2 0 9 :銅柱 2 0 6 a >207 a 、2 0 9 a :端面 2 0 8 ： 表 面 保 2 10 承 載 器 212 ： :承 載 表 214 接 合 墊 216 : :預 銲 塊 220 底 膠 310 : :承 載 器 312 承 載 表 面 314 ： 接 合 墊 320 、33 0 •晶片 324(a) 、（b) 、（c):銅柱 332 :主動表面11008twf.ptd Page 14 1224376 Brief Description of Drawings Figure 1 shows a schematic diagram of a conventional flip-chip package structure using copper pillars as bumps of a wafer and a carrier. Figures 2 to 4 sequentially show the flow chart of a flip-chip bonding process according to a preferred embodiment of the present invention. Figures 5 and 6 respectively show two types of wafer packaging structures using different types of copper pillars. Figures 7 to 9 are schematic diagrams showing three types of wafer packaging structures using different types of copper pillars. Figures 10 to 12 are schematic diagrams showing three types of chip packaging structures using different types of copper pillars. [Illustration of Graphical Symbols] 100 wafers 102 wafer pads 1 04 copper pillars 110 carrier 112 bonding pads 1 14 pre-soldering blocks 120 primer 200 wafers 202 active surfaces 204 wafer pads 2 0 6, '20 7, 2, 20 9: Copper pillar 2 0 6 a > 207 a, 2 0 9 a: End surface 2 8: Surface protection 2 10 Carrier 212:: Carrying table 214 Joint pad 216:: Pre-solder block 220 Primer 310:: Carrier 312 Carrying surface 314: Bonding pads 320, 33 0 • Wafers 324 (a), (b), (c): Copper pillars 332: Active surface
11008twf.ptd 第15頁 1224376 圖式簡單說明 334 :晶片墊 340 :底膠 424(a) 、 （b) 、 （c) 424(a) 、（b) 、（c) 4 2 6 :預銲塊 3 3 6 :預銲塊 4 2 0 、4 3 0 ：晶片 :第一銅柱 :第二銅柱 440 :底膠11008twf.ptd Page 15 1224376 Brief description of the diagram 334: Wafer pad 340: Primer 424 (a), (b), (c) 424 (a), (b), (c) 4 2 6: Pre-soldering block 3 3 6: pre-solder block 4 2 0, 4 3 0: wafer: first copper pillar: second copper pillar 440: primer
1HBI1 11008twf.ptd 第16頁1HBI1 11008twf.ptd Page 16
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| US10636758B2 (en) * | 2017-10-05 | 2020-04-28 | Texas Instruments Incorporated | Expanded head pillar for bump bonds |
| TWI704659B (en) * | 2019-10-22 | 2020-09-11 | 樂鑫材料科技股份有限公司 | Wafer backside thin film structure, power module package including the same, manufacturing method of wafer backside thin film structure, and manufacturing method of power module package |
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| CN117219526A (en) * | 2023-11-09 | 2023-12-12 | 日月新半导体(昆山)有限公司 | Integrated circuit bonding process and integrated circuit structure |
| CN117219526B (en) * | 2023-11-09 | 2024-02-09 | 日月新半导体(昆山)有限公司 | Integrated circuit bonding process and integrated circuit structure |
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