TW486794B - A flip-chip mounting assembly without lead - Google Patents

Abstract

A flip-chip mounting assembly without lead containing comprises: a substrate, a chip, and a plurality of conductive bumps for mounting the chip with flip-chip configuration onto the substrate. The conductive bump is a lead-free gold alloy composed of between 15 and 25 mole percent tin, so that the chip rapidly mounts on the substrate with thermal-compression and has a nice durability.

Description

486794 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a lead-free flip-chip bonding structure, and more particularly to a flip-chip bonded ball grid array packaging structure. [Prior technology] The semiconductor chip of "flip-chip mounting" is a solder bump formed on a bonding pad of a semiconductor wafer for flipping. Bonded to a substrate, the conventional solder bump is a lead-tin alloy, such as 63 Sn / g7

The solder balls of Pb are reflowed together with flux such as rosin to join the substrates. Due to the phenomenon of lead coarsening or granulation, soldering is used for soldering = block: two; structural strength Gradually money, in addition, Lei Zao 错 f Γ Γ5, 410, 184 "Micro-binary method with tin-copper-tan bumps" Revealed-an error-free microelectronic The plate 44 and a plurality of electronic / electronic packages 40 include a base 56 which is error-free and contains a weight percentage of the core 56, and the substrate 44 is a j-junction bump 46 which is a pad ring formed on the wafer 42 Oxygen resin body 48 ^ = brush circuit board is reinforced with glass fiber, and board 44 = copper circuit, circuit 50 and _ pad bump 46 contains a very important solder mask Film 54, because the welding block 46 has a high surface tension of 2% to 8% of copper "makes the solder bump" for reflow [reflow] bonding, but the welding page 4 486794 V. Description of the invention (2) The melting point of the bump 4 6 is lower than that of the photo-selection:-the temperature is poor, and even the benefit is-140 degrees' its durability and High process to form the encapsulant. A Baidu loose baking [Objective and summary of the invention], dii ί :: It is to provide an error-free flip-chip combination to form gold ^^ 人 ^ = on-chip gold bumps and the plated tin layer of the substrate quickly del · · ，，，，. 乂, · '. Called 11 ^ ΐίί ft conductive bumps, the tin content of which is 15 ~ out, to form: effective. < Junction point 'to achieve lead-free and prevent metallographic structure deterioration-the purpose of human is to provide a packaging structure, when the frost pressure on the next day μ L human ball grid array fast belt ^ on the chip The gold bump and the electroplated tin layer of the substrate are almost conductive bumps, the tin content of which is 15 ~ 25%, the junction point of high durability, high melting point, so that the subsequent moon dagger is formed by automatic compression molding. colloid. j The lead-free flip-chip bonding structure of the present invention comprises: a substrate having a plurality of connection pads on one surface; a wafer having a plurality of pads on the same surface; and, a conductive bump, each conductive The bumps are located between the connection pads of the substrate and the pads. The conductive bumps are gold [Au] alloy, and the dagger contains tin with a mole percentage of 15% to 25%. [Details] [Details of the invention] [Explanation] Secondly, referring to the attached drawings, the present invention will be illustrated by the following embodiments: Figures 1 and 2 show the first specific embodiment of the present invention. As shown in Figure 1, a lead-free flip chip The combined structure mainly includes a wafer 486794 V. Description of the invention (3) " " 11, a substrate 12 and a plurality of conductive bumps 13, the structure of which is detailed as follows: ^ In this embodiment, the wafer 11 is For a display driving wafer or other, a plurality of bonding pads 14 are formed on one surface of the wafer 11, and the substrate 12 is a glass substrate or a ceramic substrate. A plurality of metal circuits 16 and a plurality of surfaces are formed on one surface of the substrate 12. Corresponding connection pads 丨 5 [That is, the metal circuit layer] In addition, the conductive bump 13 is between the wafer 丨 and the substrate 12, and the solder pad 14 of the wafer 11 and the connection pad 15 of the substrate 12 are welded. The conductive bump & is gold [ Au] alloy, which contains tin [Sn] i with a mole percentage of 15% to 25%, or a tin content with a weight percentage of about ~, preferably, the tin content should be 18% to 22% In the meantime, due to the action of tin on gold, the melting point of the conductive bumps W of these eutectic alloy alloys [eutectic alloys] can be controlled at about 500 degrees Celsius, and the temperature of the coarse changes of their metallographic structure is about 114 ° C, that is, at room temperature, the metallographic structure of the conductive bump 13 will not have a coarse deterioration transition to maintain a fixed structural strength. At the same time, the conductive bump 13 does not contain lead and does not need reflow flux In order to avoid polluting the environment, the flip-chip bonding structure 10 has the effects of lead-free and high durability [preventing metallographic structure deterioration]. As shown in FIG. 2, the structure of the conductive bump 13 of the gold-tin eutectic alloy is that a gold bump i 7 is formed on the pad 14 of the & 1 and a plating layer of tin is formed on the connection pad 15 of the substrate i 2. 18. The methods used to grow gold bumps 17 on the wafer u include electroplating, evaporation, screen printing, and wire bonding. Usually, a bump is first formed between the pad 14 on the wafer 11 and the gold bump 17. The bearing said [Under Bump Metallization, UBM], after the wafer u is turned over, the wafer 11 is subjected to a temperature of about 40 (TC to 550 ° C [preferably 50000:]) 486794

V. Description of the invention (4) Degree and an appropriate pressure for pressure welding to the substrate 12, since the gold bump π and the tin bond layer 18 have good bonding and diffusion, a pressure welding time of one to three seconds can be Rapid formation of a flip-chip bonding structure 10 'with a gold-tin eutectic alloy conductive bump 13 as shown in Fig. 1 and re-soldering of conventional ship tin bumps [refi0w] Compared to the joining process, re-soldering is not required Flux and high temperature for coarsening changes of metallographic structure. °

In the second specific embodiment of the present invention, FIG. 3 is a cross-sectional view of another error-free flip-chip bonding structure 20, which mainly includes a wafer 21, a substrate 22, a plurality of conductive bumps 23, and a bottom. Underfill 26, chip 21 is a memory chip, such as DRAM, SDR, AM, SRAM, flash, ROM, EPROM, Rambus, DDR memory

Etc. or other processor or logic chip, the chip 2 i has an integrated circuit forming surface, and a plurality of bonding pads 24 are formed on the integrated circuit forming surface, and the substrate 22 is A printed circuit board (PCB), such as a motherboard or a memory module board, uses a plurality of conductive bumps 23 to solder the pads 24 of the wafer 21 to the connection pads 25 of the substrate 22. It is known that the connection pads 25 of the substrate 22 have A solder mask is formed on the surface, and the conductive bump 23 is similar to the first embodiment. It is also a gold-tin eutectic alloy with a tin content of 15 /%. 2 ^ /. In the meantime, the wafer 21 is bonded to the substrate μ in a flip-chip form, and the 5 ^ 26 series is an insulating and thermosetting epoxy compound, which is located between the two & I substrates 22 and seals a plurality of conductive bumps. Block 23, as a buffer layer between wafer two = f 2 to absorb the caused by different thermal expansion coefficients

Page 7 V. Description of the invention (5) In the third presentation of the present invention, I # 宭 始 μ + ^ Sincerely, in the example of the body, 图 4 is an application = No .: Specific examples only The two U12 for flip chip bonding are described below: several conductive bumps 33,-sealing rubber; i surfaces 36 m: ϊ 32 has an upper surface 36 and-lower surface 37, on the upper Γ =: a connection pad 35 Preferably, the substrate 32 has vent holes 321 on the penetrating surface 36 and the lower surface 37, and the wafer 3 has a plurality of Tan pads 34 on one surface, and the conductive pads are raised on the pads 34 by flipping the wafer to make conductive protrusions. The block 33 is connected to the substrate 3, the ghost 33, and the conductive bump 33 are made of gold [Au] alloy; 25% of the amount of tin [Sn], the plurality of solder balls have Morble columns, and the lower surface of the W plate 32 37. In this embodiment, the seal matrix array seals a plurality of conductive bumps 33 and a wafer 31. The two have a temperature of about five degrees Celsius, and have a more similar melting point, and can withstand two or three degrees of Baidu. Process: Ensuring the subsequent formation of sealant 39 by automatic compression molding, 2 = Causes the conductive bump 33 to have structural strength due to excessive coarsening [granulation] ^ J this "protection range" The scope of the appended patents shall prevail. Any changes and modifications made by anyone who knows the art well without departing from the scope of the present invention are covered by the invention ^ _ and 486794 Explanation of Formulas Figure 1 • In the first specific embodiment of the present invention 5-cross-sectional view of a combination structure without error; Figure 2 In the first specific embodiment of the present invention,-the wafer is crystallized to one Schematic diagram of the substrate to form an error-free flip-chip bonding structure; Figure 3 • In the second embodiment of the present invention 5-cross-sectional view of the error-free bonding structure; Figure 4 • In the first In the three specific embodiments, J-a cross-sectional view of a non-faulting combined structure; and Fig. 5 is in US Patent No. 5,410, 184 "a microelectronic package with tin-copper soldering and its forming method", Cross-sectional view of the micro-electronic assembly. [Illustration of drawing number] 10 flip-chip bonding structure 11 wafer 12 substrate 13 conductive bump 14 solder pad 15 connection pad 16 metal wiring 17 Bump 18 Plating layer 20 Flip-chip bonding structure 21 Wafer 22 Substrate 23 Conductive bump 24 Solder pad 25 Connection pad 26 Bottom pad 30 Ball grid array package structure 31 Wafer 32 Substrate 321 Exhaust hole 33 Conductive bump 34 Pad 35 Connection Pad one -4 hidden Φ

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Claims (1)

486794 6. Scope of patent application [Scope of patent application 1. An error-free flip-chip bonding structure, which includes: f-board 'with a plurality of connection pads on one surface; two wafers with a plurality of pads on the same surface ; And, each electric bump is located between the connection pad 2 and the welding pad of the substrate, wherein the conductive bump is a gold [Au] alloy, and / or 3 has a mole 15% ~ 2 5% tin [Sn] content. ▲, 铅 The lead-free flip-chip bonding structure 仏 ′ described in item 1 of the 范围 Li scope, and the amount of 3 tin [Sn] in Shangzhong is between 18% and 22%. As described in item 1 of the patent scope, the substrate-less flip-chip bonding structure ^ is a printed circuit board. , Such as: ί !! The lead-free flip-chip bonding structure described in item 3 of Drywall ^ 3 A bottom pad is formed between the substrate and the wafer. : The lead-free fabrication as described in item 丄 of the patent application scope, wherein the substrate is a glass substrate. It is said that ... the structure of an error-free flip-chip bonded structure as described in item 1 is provided ^ with another colloid. A flip-chip bonded array packaging structure, comprising: a substrate having an upper surface and a lower surface, with a plurality of connection pads on the upper surface; a wafer formed on your upper surface and having the same surface A plurality of solder pads are formed with conductive bumps, and the corresponding connection pads of the board are made by flipping the wafer. The conductive bumps are made of gold (AU) and contain a mole percentage of 15% to 25%. Amount of tin [Sn]; and ', Bu; < 1 Page 11 486794 Six 'patent application scope A plurality of solder balls are formed on the lower surface of the substrate. 8. The flip-chip bonded ball grid array package structure described in item 7 of the scope of patent application, wherein the amount of tin [S η] is between 1 $% and 22%. 9. The flip-chip-bonded ball grid array packaging structure described in item 7 of the scope of the patent application, further comprising a substrate, formed between the substrate and the wafer. 10. The flip-chip bonded ball grid array package structure described in item 7 of the scope of the patent application, further comprising a piece of gel for sealing the conductive bumps. 11. The flip-chip bonded ball grid array package structure described in item 10 of the patent application scope, wherein the sealant system seals the wafer. 1 2. A lead-free flip-chip bonding method, comprising the steps of: providing a substrate with a plurality of connection pads on the surface of the substrate, and a tin layer formed on the connection pads; providing at least one wafer having the same surface A plurality of bonding pads, and gold bumps are formed on the bonding pads; and the wafer is pressure-bonded to a temperature of about 400 ° C to 5500 ° C and pressed to the substrate until the wafer The gold bump and the tin layer of the substrate are formed as a conductive bump of a gold-tin eutectic alloy. 1 3. The lead-free flip-chip bonding method according to item 丨 2 of the patent application scope, further comprising: forming a base pad between the wafer and the substrate. 14. The method of bonding without wafers as described in item 12 of the patent scope of Shenyan ', wherein the conductive bumps of the gold-tin eutectic alloy formed after the step of pressure welding have a mole percentage of 15% ~ 25% tin [311] content.