TW200501285A - Flip-chip bonding process - Google Patents

Flip-chip bonding process

Info

Publication number
TW200501285A
TW200501285A TW092116215A TW92116215A TW200501285A TW 200501285 A TW200501285 A TW 200501285A TW 092116215 A TW092116215 A TW 092116215A TW 92116215 A TW92116215 A TW 92116215A TW 200501285 A TW200501285 A TW 200501285A
Authority
TW
Taiwan
Prior art keywords
flip
chip
conductive metal
chip bonding
metal column
Prior art date
Application number
TW092116215A
Other languages
Chinese (zh)
Other versions
TWI224376B (en
Inventor
Kwun-Yao Ho
Moriss Kung
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW092116215A priority Critical patent/TWI224376B/en
Application granted granted Critical
Publication of TWI224376B publication Critical patent/TWI224376B/en
Publication of TW200501285A publication Critical patent/TW200501285A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A flip-chip bonding process is provided. At first, to form a first conductive metal column on a die pad of a first chip, wherein the surface area of the end of the first conductive metal column far from the die pad is bigger than the cross-section area of the first conductive metal column to increase the contact area for flip-chip bonding. Next, to form a first surface preservation layer on the surface of the first copper column, wherein the first surface preservation layer such as a organic preservation layer or a Ni/Au layer for preventing surface oxidation. Then, to bond the first conductive metal column of the first chip to a carrier or a second chip.
TW092116215A 2003-06-16 2003-06-16 Flip-chip bonding process TWI224376B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092116215A TWI224376B (en) 2003-06-16 2003-06-16 Flip-chip bonding process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092116215A TWI224376B (en) 2003-06-16 2003-06-16 Flip-chip bonding process

Publications (2)

Publication Number Publication Date
TWI224376B TWI224376B (en) 2004-11-21
TW200501285A true TW200501285A (en) 2005-01-01

Family

ID=34568389

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092116215A TWI224376B (en) 2003-06-16 2003-06-16 Flip-chip bonding process

Country Status (1)

Country Link
TW (1) TWI224376B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111316432A (en) * 2017-10-05 2020-06-19 德州仪器公司 Enlarged head post for bump bonding
TWI704659B (en) * 2019-10-22 2020-09-11 樂鑫材料科技股份有限公司 Wafer backside thin film structure, power module package including the same, manufacturing method of wafer backside thin film structure, and manufacturing method of power module package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117219526B (en) * 2023-11-09 2024-02-09 日月新半导体(昆山)有限公司 Integrated circuit bonding process and integrated circuit structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111316432A (en) * 2017-10-05 2020-06-19 德州仪器公司 Enlarged head post for bump bonding
CN111316432B (en) * 2017-10-05 2024-06-07 德州仪器公司 Enlarged post for bump bonding
TWI704659B (en) * 2019-10-22 2020-09-11 樂鑫材料科技股份有限公司 Wafer backside thin film structure, power module package including the same, manufacturing method of wafer backside thin film structure, and manufacturing method of power module package

Also Published As

Publication number Publication date
TWI224376B (en) 2004-11-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees