WO2024060058A1

WO2024060058A1 - Integrated circuit device, packaging, and method for forming thereof

Info

Publication number: WO2024060058A1
Application number: PCT/CN2022/120181
Authority: WO
Inventors: Shu Zhang; Xiaojuan WANG; Shifang Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd.
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2024-03-28

Abstract

The present disclosure provides a three-dimensional (3D) integrated circuit (IC) device and fabrication methods. The IC device includes a packaging substrate having a first region, a second region, and a third region; a plurality of connecting structures standing on the first region of the packaging substrate and configured for providing electric power to a plurality of dies; the plurality of dies stacked in a vertical direction on the packaging substrate, a bottom one of the plurality of dies being located within the second region of the packaging substrate; and at least one contact base on the third region of the packaging substrate being electrically connected with at least one contact pad of the bottom one of the plurality of dies by at least one wiring line.

Description

INTEGRATED CIRCUIT DEVICE, PACKAGING, AND METHOD FOR FORMING THEREOF

BACKGROUND

The present disclosure relates to integrated circuit (IC) device and packaging, and fabrication methods thereof.

Planar semiconductor devices are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the semiconductor devices approach a lower limit, planar process and fabrication techniques become challenging and costly. A three-dimensional (3D) device architecture can address the density limitation in some planar semiconductor devices, for example, phase-change memory devices.

3D semiconductor devices including IC devices can be formed by stacking semiconductor wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or copper-to-copper (Cu-Cu) connections, so that the resulting structure acts as a single device to achieve performance improvements at reduced power and smaller footprint than conventional planar processes.

SUMMARY

In one aspect, an IC device includes a packaging substrate having a first region, a second region, and a third region; a plurality of connecting structures standing on the first region of the packaging substrate and configured for providing electric power to a plurality of dies; the plurality of dies stacked in a vertical direction on the packaging substrate, a bottom one of the plurality of dies being located within the second region of the packaging substrate; and at least one contact base on the third region of the packaging substrate being electrically connected with at least one contact pad of the bottom one of the plurality of dies by at least one wiring line. Each connecting structure, extending in the vertical direction under a corresponding one of the plurality of dies, has an upper portion being in contract with a bottom surface of the corresponding one of the plurality of dies and a lower portion being in contact with the packaging substrate.

In some implementations, edges of adjacent two dies of the plurality of dies are misaligned such that an upper one of the adjacent two dies has an extended portion located beyond a lower one of the adjacent two dies, and the extended portion of the upper one of the adjacent two dies includes the bottom surface facing towards the packaging substrate and being in contact with the upper portion of a corresponding one of the plurality of connecting structures.

In some implementations, the plurality of connecting structures are covered by the extended portions of the plurality of dies.

In some implementations, the extended portion of the upper one of the adjacent two dies includes a Through Silicon Via (TSV) that is in contact with the corresponding one of the plurality of connecting structures.

In some implementations, the TSV includes a landing pad in contact with one of the plurality of connecting structures.

In some implementations, the upper portion of each of the plurality of connecting structures includes a solder cap in contact with the landing pad of the TSV in the extended portion of the corresponding one of the plurality of dies, and the lower portion of each of the plurality of connecting structures includes a conductive pillar directly attaching to a corresponding one of a plurality of seed bases in the first region of the packaging substrate.

In some implementations, a material of the conductive pillar includes copper or copper alloys.

In some implementations, the plurality of seed bases includes copper or copper alloys, and each conductive pillar is grown on the corresponding one of the plurality of seed bases.

In some implementations, the extended portion of the upper one of the adjacent two dies includes a first offset in a first lateral direction with respect to the lower one of the adjacent two dies, the first offset is less than one-tenth of a width of the upper one of the adjacent two dies in the first lateral direction.

In some implementations, the plurality of connecting structures includes a first subset of connecting structures arranged along a second lateral direction perpendicular to the first lateral direction and connected with the bottom surface of the corresponding upper one of the adjacent two dies.

In some implementations, the first subset of connecting structures includes at least two rows of connecting structures arranged in straight lines in the second lateral direction, and in a staggered manner in the first lateral direction.

In some implementations, the extended portion of the upper one of the adjacent two dies further includes a second offset in the second lateral direction with respect to the lower one of the adjacent two dies, and the plurality of connecting structures further includes a second subset of connecting structures under the second offset aligned along the first lateral direction and connected with the bottom surface of the corresponding upper one of the adjacent two dies.

In some implementations, the lower one of the adjacent two dies has a staircase portion that is uncovered by the upper one of the adjacent two dies, wherein the staircase portion of the lower one of the adjacent two dies has a top surface facing away from the packaging substrate and including at least one contact pad.

In some implementations, adjacent ones of the plurality of dies are electrically connected with each other by wiring the at least one contact pad of each die together.

In some implementations, the substrate includes an embedded interconnect layer that electrically connects the plurality of seed bases with the at least one contact base.

In some implementations, the plurality of dies includes one or more phase-change memory (PCM) dies.

In some implementations, a material of the one or more PCM dies includes a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .

In some implementations, the plurality of dies includes a Central Processing Unit (CPU) die.

In another aspect, an IC packaging base includes a packaging substrate having a first region, a second region, and a third region ; a plurality of connecting structures standing on the first region of the packaging substrate and configured for providing electric power to a plurality of dies; and at least one contact base on the third region of the packaging substrate configured to electrically connect with at least one contact pad of a bottom one of the plurality of dies by at least one wiring line. Each connecting structure, which extends in a vertical direction, has an upper portion configured to contact with a bottom surface of the corresponding one of the plurality of dies, and a lower portion being in contact with the packaging substrate.

In some implementations, the plurality of connecting structures has different heights in the vertical direction.

In some implementations, the upper portion of each of the plurality of connecting structures includes a solder cap configured to connect with a corresponding one of the plurality of dies, and the lower portion of each of the plurality of connecting structures includes a conductive pillar directly attaching to a corresponding one of a plurality of seed bases in the first region of the packaging substrate.

In some implementations, the plurality of seed bases include copper or copper alloys, and each conductive pillar is grown on the corresponding one of the plurality of seed bases.

In some implementations, the plurality of connecting structures includes a first subset of connecting structures arranged along a second lateral direction perpendicular to a first lateral direction.

In still another aspect, a method for packaging an IC device includes the following operations. A packaging substrate having a first region, a second region, and a third region is provided. A plurality of connecting structures may then be formed and extend in a vertical direction on first region of the packaging substrate. Each of the plurality of connecting structures has a lower portion that is in electric contact with the packaging substrate. A plurality of dies may be stacked in the vertical direction on the packaging substrate in a misaligned manner, such that an upper portion of each connecting structure is in electric contact with a bottom surface of the corresponding one of the plurality of dies. A bottom one of the plurality of dies may be attached within the second region of the packaging substrate. At least one contact base may be formed on the third region of the packaging substrate, and the at least one contact base may be electrically connected with at least one contact pad of the bottom one of the plurality of dies by at least one wiring line. The second region of the packaging substrate is configured to attach the bottom one of the plurality of dies.

In some implementations, stacking the plurality of dies includes misaligning edges of adjacent two dies such that an upper one of the adjacent two dies has an extended portion located beyond a lower one of the adjacent two dies, where the extended portion of the upper one of the adjacent two dies includes the bottom surface facing towards the packaging substrate and being in electric contact with the upper portion of a corresponding one of the plurality of connecting structures, and the extended portions cover the plurality of connecting structures.

In some implementations, the method includes forming a Through Silicon Via (TSV) in the extended portion of the upper one of the adjacent two dies before stacking the plurality of dies. Stacking the plurality of dies includes landing the TSV with the corresponding one of the plurality of connecting structures.

In some implementations, forming the TSV includes forming a landing pad on a lower end of the TSV for landing to the corresponding one of the plurality of connecting structures.

In some implementations, forming one of the plurality of connecting structures includes forming a conductive pillar on one of a plurality of seed bases in the packaging substrate as the lower portion of the one of the plurality of connecting structures, and forming a solder cap on the conductive pillar as the upper portion of the one of the plurality of connecting structures for connecting with the landing pad of the TSV in the extended portion of the corresponding one of the plurality of dies.

In some implementations, forming the conductive pillar includes electroplating copper or copper alloys on the one of the plurality of seed bases.

In some implementations, stacking the plurality of dies includes offsetting a first edge of the extended portion of the upper one of the adjacent two dies at a first distance in a first lateral direction with respect to a first edge of the lower one of the adjacent two dies, wherein the first distance is less than one-tenth of a width of the upper one of the adjacent two dies in the first lateral direction.

In some implementations, forming the plurality of connecting structures includes forming a first subset of connecting structures aligned along a second lateral direction perpendicular to the first lateral direction, and stacking the plurality of dies includes connecting the first subset of connecting structures to the bottom surface of the corresponding upper one of the adjacent two dies.

In some implementations, forming the first subset of connecting structures includes forming at least two rows of connecting structures arranged in straight lines in the second lateral direction, and in a staggered manner in the first lateral direction.

In some implementations, stacking the plurality of dies further includes offsetting the first edge of the extended portion of the upper one of the adjacent two dies to expose a top surface of a staircase portion of the lower one of the adjacent two dies, wherein the top surface of the staircase portion of the lower one of the adjacent two dies faces away from the packaging substrate and including at least one contact pad.

In some implementations, providing the packaging substrate further includes electrically connecting adjacent ones of the plurality of dies with each other by wiring the at least one contact pad of each die together.

In some implementations, providing the packaging substrate further includes forming an embedded interconnect layer that electrically connects the plurality of seed bases with the at least one contact base.

In some implementations, forming a plurality of dies includes stacking one or more phase-change memory (PCM) dies with at least one Central Processing Unit (CPU) die.

In yet another aspect, a method for forming an IC packaging base includes the following operations. A packaging substrate having a first region, a second region, and a third region is provided. A plurality of connecting structures may then be formed and extend in a vertical direction on the first region of the packaging substrate. Each of the plurality of connecting structures has a lower portion that is in electric contact with the packaging substrate, and an upper portion that is configured to contact with a bottom surface of a corresponding one of a plurality of dies. At least one contact base may be formed on the third region of the packaging substrate and be configured to electrically connect with at least one contact pad of a bottom one of the plurality of dies by at least one wiring line. The second region of the packaging substrate is configured to attach the bottom one of the plurality of dies.

In some implementations, forming the plurality of connecting structures includes forming connecting structures having different heights in the vertical direction.

In some implementations, forming one of the plurality of connecting structures includes forming a conductive pillar on one of a plurality of seed bases in the first region of the packaging substrate as the lower portion of the one of the plurality of connecting structures, and forming a solder cap on the conductive pillar as the upper portion of the one of the plurality of connecting structures for connecting with the corresponding one of the plurality of dies.

In some implementations, forming the plurality of connecting structures includes forming a first subset of connecting structures arranged along a second lateral direction perpendicular to a first lateral direction.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1a-1d illustrate schematic views of a 3D IC device according to some aspects of the present disclosure.

FIG. 2 illustrates a schematic view of an IC packaging base according to some aspects of the present disclosure.

FIGs. 3a-3d illustrate an exemplary method for forming a 3D IC device according to some aspects of the present disclosure.

FIGs. 4a-4b illustrate an exemplary method for forming an IC packaging base according to some aspects of the present disclosure.

FIG. 5 illustrates a flowchart of an exemplary method for forming a 3D IC device according to some aspects of the present disclosure.

FIG. 6 illustrates a flowchart of an exemplary method for forming a packaging base according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for the existence of additional factors not necessarily expressly described, again, depending at least in part on the context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, “bond pad” is a term generally referring to electrical bond pads in association with test points or external electrical connections of an integrated electronic device such as an IC or Micro-Electro-Mechanical System device. Related industry terms are “bonding pad” and “bump” . As used herein, “solder bump” or “solder ball” are terms generally referring to a ball of solder bonded to a bond pad for further assembly of the die into packages by the use of surface mount technology or wire bonding.

As used herein, the term “die” generally refers to a small piece of a processed semiconductor wafer that is diced into sections containing integrated circuits or other devices. The term “die stack” generally refers to a vertical assembly of two or more dies containing integrated circuits that are interconnected to function as a unit.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10–30%of the value (e.g., ±10%, ±20%, or ±30%of the value) .

As used herein, the term “3D packaging” or “3D integration” generally refers to the process of encapsulation of a die stack into a complete IC package, where the 3D package has a smaller footprint than that of a single die containing all the circuits in a planar structure. As used herein, the term “3D IC device” refers to a vertically stacked IC device on a laterally oriented substrate so that the stack of dies extends in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

As used herein, the term “connected” refers to a direct connection, such as an electrical or mechanical connection between the things that are connected, without any intermediary devices.

As used herein, the term “circuit” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “IC” is a microelectronic circuit produced monolithically on semiconductor wafer substrates by microfabrication methods.

As used herein, the term “edge offset” generally refers to a stack of dies having one or more edges offset horizontally or laterally from each other.

As used herein, the term “top surface” refers to the surface of a structure that is the farthest away from the substrate the structure is formed on/in, and the term “bottom surface” refers to the surface of a structure that is the closest to the substrate the structure is formed on/in. In the present disclosure, the relative positions of the top surface and the bottom surface do not change as the orientation of the object changes.

In the present disclosure, the elevation of a surface of an object is defined as the distance between the surface and the substrate on/in which the object is formed. In the present disclosure, the relative position of the two surfaces is defined based on the elevations of the two surfaces and does not change as the orientation of the objects change.

As used herein, the terms “stair, ” “step, ” and “level” can be used interchangeably. As used herein, a staircase structure refers to a set of surfaces that include at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A “stair” refers to a vertical shift in the height of a set of adjoined surfaces. A “staircase structure” refers to a structure having a plurality of stairs extending vertically.

In IC packaging, multiple dies may be stacked to allow higher levels of integration, and this technology is known as 3D vertical packaging. In 3D vertical packaging, specifically, dies may be stacked on a substrate in a shingle stack configuration, where the edges of dies are aligned with an offset, such that adjacent two dies may be directed wired together, with short die-to-die interconnects. In this configuration of die packaging, however, all bonding wires are placed on one side of the die stack, which leads to a layout design with pads on one side and the other side has no pad. When the chip area is large, this layout will have challenges in terms of power supply, EM (electro-migration) , IR (voltage drops) , and thermal issues. To solve this problem, a currently used approach is to increase the width of the power metal, hence enhancing the power supply and mitigating EM/IR issues. However, this approach would increase die size, which is an adversary to reducing the cost.

In order to resolve the aforementioned problem, the present disclosure provides an IC device, an IC packaging base, and fabrication methods thereof. An extra power supply is added to the substrate on a side of the die stack opposite to the wiring side. By this approach, power is supplied to the die stack from both sides, which improves the power supply and mitigates EM/IR issues. In addition, supplying power from both sides is beneficial to reducing the width of power metals. Compared to a one-sided power supply for chips, supplying power from both sides can further reduce chip area and size, helping to control the cost of the wafer.

Some implementations in accordance with the present disclosure provide IC devices formed by the joining of different dies with a plurality of connecting and contact structures. One of the IC devices may include a packing substrate having a first region, a second region, and a third region; a plurality of connecting structures standing on the first region of the packaging substrate and configured for providing electric power to a plurality of dies; the plurality of dies stacked in a vertical direction on the packaging substrate and a bottom one of the plurality of dies being located within the second region of the packaging substrate; and at least one contact base on the third region of the packaging substrate being electrically connected with at least one contact pad of the bottom one of the plurality of dies by at least one wiring line. Each connecting structure may extend in the vertical direction under a corresponding one of the plurality of dies, and may include an upper portion being in contact with a bottom surface of the corresponding one of the plurality of dies and a lower portion being in contact with the packaging substrate.

Some implementations in accordance with the present disclosure provide an IC packaging base. One of the IC packaging bases may include a packaging substrate having a first region, a second region, and a third region; a plurality of connecting structures standing on the first region of the packaging substrate and configured for providing electric power to a plurality of dies; and at least one contact base on the third region of the packaging substrate configured to electrically connect with at least one contact pad of a bottom one of the plurality of dies by at least one wiring line. Each of the plurality of connecting structures, which is configured for providing electric power to a plurality of dies, includes an upper portion configured to contact with a bottom surface of a corresponding one of the plurality of dies and a lower portion being in contact with the packaging substrate.

Some implementations in accordance with the present disclosure provide a method for packaging an IC device. A packaging substrate having a first region, a second region, and a third region is provided. A plurality of connecting structures may then be formed and extend in a vertical direction on the first region of the packaging substrate. Each of the plurality of connecting structures has a lower portion that is in electric contact with the packaging substrate. A plurality of dies may be stacked in the vertical direction on the packaging substrate in a misaligned manner, such that an upper portion of each connecting structure is in electric contact with a bottom surface of the corresponding one of the plurality of dies, and a bottom one of the plurality of dies is located within the second region of the packaging substrate; at least one contact base may be formed on the third region of the packaging substrate; and the at least one contact base may be electrically connected with at least one contact pad of the bottom one of the plurality of dies by at least one wiring line.

Some implementations in accordance with the present disclosure provide a method for forming an IC packaging base. A packaging substrate having a first region, a second region, and a third region is provided. A plurality of connecting structures may then be formed and extend in a vertical direction on the first region of the packaging substrate. Each of the plurality of connecting structures has a lower portion that is in electric contact with the packaging substrate, and an upper portion that is configured to contact with a bottom surface of a corresponding one of a plurality of dies. At least one contact base may be formed on the third region of the packaging substrate and configured to electrically connect with at least one contact pad of a bottom one of the plurality of dies by at least one wiring line.

As used herein, the term “cross-section view” and “plan view” correspond to orthogonal planes within a cartesian coordinate system. Profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Generally, profile views in the x-z plane are cross-sectional views.

FIG. 1a illustrates a schematic diagram of IC packaging 100 in a cross-sectional side view, including packaging substrate 102, die stack 104, and connecting structure 112. It is noted that x-, y-, and z-axes are added in FIG. 1, as well as other figures, to illustrate the spatial relationship of the components in the structures/devices. For example, packaging substrate 102 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-and y-axes (the lateral directions) . As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D IC device 100) is determined relative to the substrate of the semiconductor device (e.g., packaging substrate 102) in the z-axis (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-axis. The same notion for describing the spatial relationship is applied throughout the present disclosure.

In some implementations, packaging substrate 102 may be a carrier substrate made from silicon (e.g., single crystalline silicon, c-Si) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials. In some implementations, packaging substrate 102 may be made from ceramic, glass, or an organic material such as epoxy resin or glass-reinforced epoxy resin, phenolic substrate, or the like.

In some implementations, packaging substrate 102 may include three regions: a first region 102-1 for arranging a plurality of connecting structures, a second region 102-2 for attaching dies, and a third region 102-3 having at least one contact base.

In some implementations, die stack 104 includes a plurality of dies with no specific limitation on quantity. Individual dies may be the same or may be different. Dies may be stacked by using an adhesive material. In some implementations, the adhesive material may include thermal/electrical conductive metal to facilitate heat dissipation and reduce resistance. Different dies in the IC device may provide a variety of different functions (e.g., logic, memory, sensors) . In some implementations, the plurality of dies may include at least one memory die, and the at least one memory die may include a phase-change memory (PCM) die, and the PCM die may contain a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) . In some implementations, the plurality of dies may include a central processing unit (CPU) die. The dies may have a same thickness, essentially the same thickness, or different thicknesses. The height of die stack 104 in a vertical direction is controlled by the thickness of individual dies 106 and the number of dies. The thickness of individual dies 106 may be in a range of about 20 to about 200 microns.

In some implementations, edges of adjacent two dies of the plurality of dies are misaligned such that an upper one of the adjacent two dies has an extended portion located beyond a lower one of the adjacent two dies. The extended portion of the upper one of the adjacent two dies includes a first offset 130 in a first lateral direction with respect to the lower one of the adjacent two dies, and the first offset 130 is less than one-tenth of a width of the upper one of the adjacent two dies in the first lateral direction. In some implementations, the extended portion of the upper one of the adjacent two dies includes a second offset (referring to FIG. 1c) in a second lateral direction with respect to the lower one of the adjacent two dies. In some implementations, the extended portion of the upper one of the adjacent two dies includes an offset in both first and second lateral directions (referring to FIG. 1d) . In some implementations, the extended portion of the upper one of the adjacent two dies includes a bottom surface facing toward the packaging substrate. In some implementations, the extended portion of the upper one of the adjacent two dies includes a Through Silicon Via (TSV) 108, and the TSV may include a landing pad 110 exposed on the bottom surface.

Continuing with FIG. 1a, IC packaging 100 may include a plurality of connecting structures 112 standing on the packaging substrate and configured for providing electric power to the plurality of dies. Each connecting structure extends in the vertical direction under a corresponding one of the plurality of dies. In some implementations, each connecting structure may include an upper portion 112-1 being in contact with the bottom surface of the corresponding one of the plurality of dies and a lower portion 112-2 being in contact with the packaging substrate. In some implementations, the upper portion 112-2 of each connecting structure 112 is in contact with the TSV 108 exposed on the bottom surface of the corresponding one of the plurality of dies. In some implementations, the upper portion 112-1 of each connecting structure 112 is in contact with the landing pad 110 of the TSV 108 exposed on the bottom surface of the corresponding one of the plurality of dies. The plurality of connecting structures are covered by the extended portions of the plurality of dies.

In some implementations, each connecting structure 112 may include an upper portion 112-1 and a lower portion 112-2. The upper portion 112-1 may include a solder cap in contact with the landing pad 110 of the TSV 108 in the extended portion of the corresponding one of the plurality of dies. The solder cap increases the reliability and bonding strength between the connecting structure 112 and TSV 108. In some implementations, the solder cap is made from one or more of nickel, tin, gold, silver, palladium, indium, nickel-based alloy, gold-based alloy, palladium-based alloy, or other similar conductive metal/alloy materials. In some implementations, the solder cap is formed by an electroplating process or immersion plating process. The lower portion 112-2 may include a conductive pillar that is directly attached to the packaging substrate. In some implementations, each conductive pillar is attached to a seed base 114 on the packaging substrate. In some implementations, each seed base 114 on the packaging substrate 102 may be connected to the at least one contact base 118 on the packaging substrate 102 through an embedded interconnect layer 116. The seed base 114 may contain copper or copper alloys, and the conductive pillar may be grown using copper or copper alloys through electroplating or other suitable techniques on the seed base. The height of the conductive pillars may be controlled through electroplating time and concentrations of precursor solutions. To better bond the plurality of connecting structures with the die stack, localized laser heating may be used to fuse each of the connecting structures with its respective die, which enhance the contact between connecting structures and dies, hence promoting the power supply for the die stack.

FIGs. 1b-1d illustrate schematic diagrams of IC packaging structures in a perspective top view in accordance with various implementations of the present disclosure. In some implementations as shown in FIG. 1b, the plurality of connecting structures includes a first subset of connecting structures aligned along a second lateral direction (e.g., y-direction) perpendicular to the first lateral direction (e.g., x-direction) and connected with the bottom surface of the corresponding upper one of the adjacent two dies. The first subset of connecting structures includes at least two rows of connecting structures arranged in straight lines in the second lateral direction (e.g., y-direction) , and in a staggered manner in the first lateral direction as shown in FIG. 1b. For better illustration, FIG. 1b only shows one of the first subsets of connecting structures under one die. It shall be understood that each die may have a corresponding first subset of connecting structures under it.

In some implementations as shown in FIG. 1c, the extended portion of the upper one of the adjacent two dies includes a second offset in the second lateral direction (e.g., y-direction) with respect to the lower one of the adjacent two dies. The plurality of connecting structures includes a second subset of connecting structures under the second offset aligned along the first lateral direction (e.g., x-direction) and connected with the bottom surface of the corresponding upper one of the adjacent two dies as shown in FIG. 1c. For better illustration, FIG. 1c only shows one of the second subsets of connecting structures under one die. It shall be understood that each die may have a corresponding second subset of connecting structures under it.

In some implementations as shown in FIG. 1d, the extended portion of the upper one of the adjacent two dies includes an offset in both the first and second lateral directions (e.g., x-and y-directions) with respect to the lower one of the adjacent two dies. The plurality of connecting structures includes a first subset of connecting structures aligned in the second lateral direction (e.g., y-direction) and a second subset of connecting structures aligned in the first lateral direction (e.g., x-direction) as shown in FIG. 1d. For better illustration, FIG. 1d only shows one of the first and second subsets of connecting structures under one die. It shall be understood that each die may have corresponding first and second subsets of connecting structures under it.

Referring back to FIG. 1a, the IC device includes a die stack that is composed of a plurality of same or different dies. The lower one of the adjacent two dies has a staircase portion 132 that is uncovered by the upper one of the adjacent two dies, and the staircase portion of the lower one of the adjacent two dies has a top surface facing away from the packaging substrate 102. In some implementations, each staircase portion 132 has at least one contact pad 120, and the at least one contact pad of the bottom one of the plurality of dies is electrically connected to the at least one contact base 118 on the packaging substrate. In some implementations, the contact pad 120 is made from one of conductive materials, such as metals including copper, silver, gold, or the like. Further, adjacent ones of the plurality of dies are electrically connected with each other by wiring the at least one contact pad of each die using electrical wire 124.

FIG. 2 illustrates a schematic diagram of IC packaging base 200 in a cross-sectional side view, according to some implementations of the present disclosure. IC packaging base 200 can include packaging substrate 202 and a plurality of connecting structures 212. In some implementations, packaging substrate 202 may be a carrier substrate made from silicon (e.g., single crystalline silicon, c-Si) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials. In some implementations, packaging substrate 202 may be made from ceramic, glass, or an organic material such as epoxy resin or glass-reinforced epoxy resin, phenolic substrate, or the like. In some implementations, packaging substrate 202 may include three regions: a first region 202-1 for arranging a plurality of connecting structures, a second region 202-2 for attaching dies, and a third region 202-3 having at least one contact base.

Continuing with FIG. 2, IC packaging base 200 may include a plurality of connecting structures 112 standing on the packaging substrate and configured for providing electric power to the plurality of dies. Each connecting structure extends in the vertical direction for attaching to a corresponding one of the plurality of dies. In some implementations, each connecting structure may include an upper portion 212-1, which may include a solder cap, configured to be in contact with a bottom surface of corresponding one of the plurality of dies. Each connecting structure may also include a lower portion 212-2, which may include a conductive pillar, attached to the packaging substrate 202. In some implementations, each conductive pillar is attached to a seed base 214 on the packaging substrate 202. In some implementations, each seed base 214 on the packaging substrate 202 may be connected to the at least one contact base on the packaging substrate 202 through an embedded interconnect layer 216. The seed base 214 may contain copper or copper alloys, and the conductive pillar may be grown using copper or copper alloys through electroplating or other suitable techniques on the seed base. The height of the conductive pillars may be determined based on the thickness and number of dies, and controlled through electroplating time and concentrations of precursor solutions.

In some implementations, the plurality of connecting structures includes a first subset of connecting structures aligned along a second lateral direction perpendicular to the first lateral direction and connected with the bottom surface of the corresponding upper one of the adjacent two dies. The first subset of connecting structures includes at least two rows of connecting structures arranged in straight lines in the second lateral direction, and in a staggered manner in the first lateral direction.

FIG. 5 illustrates a flowchart of an exemplary method 500 of forming an IC device, according to some implementations. FIGs. 3a-3d illustrate schematic diagrams of an exemplary IC device 300 in a cross-sectional side view at certain fabricating stages of method 500, according to some implementations. It is understood that the operations shown in method 500 are not exhaustive and other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 5.

Referring to FIG. 5, method 500 starts at operation 502, in which a packaging substrate 302 is provided. FIG. 3a illustrates a corresponding structure. As shown in FIG. 3a, the packaging substrate 302 has three regions 302-1, 302-2, and 302-3. Region 302-1 may have a plurality of seed bases 314, and region 302-3 may have at least one contact base 318. In some implementations, packaging substrate 302 may include an embedded interconnect layer 316 for electrically connecting the seed bases 314 and the contact base 318. In some implementations, the seed bases may contain copper or copper alloys. The contact base may include any suitable conductive material, such as copper, copper alloy, silver, and gold.

Referring back to FIG. 5, after providing the packaging substrate 302, method 500 proceeds to operation 504, in which a plurality of connecting structures 312 are formed in the first region of the packaging substrate 302. FIG. 3b illustrates a corresponding structure. As shown in FIG. 3b, a plurality of connecting structures 312 may be formed in the first region 302-1, extending in a vertical direction from the packaging substrate 302. In some implementations, each of the plurality of connecting structures may have an upper portion 312-1 and a lower portion 312-2 in electric contact with the packaging substrate 302. In some implementations, each lower portion 312-2 may include a conductive pillar, and the conductive pillar may be formed by electroplating copper or copper alloy on a corresponding seed base. Heights of conductive pillars may be different, which may be controlled by the time of electroplating and concentration of precursor solutions. In some implementations, forming the plurality of connecting structures also includes forming a solder cap as the upper portion 312-1 of each connecting structure 312.

Referring back to FIG. 5, after forming the plurality of connecting structures 312, method 500 proceeds to operation 506, in which a plurality of dies are stacked in the vertical direction on the packaging substrate in a misaligned manner, such that the upper portion of each connecting structure is in electric contact with a bottom surface of a corresponding one of the plurality of dies. FIG. 3c illustrates a corresponding structure. As shown in FIG. 3c, a plurality of dies 306 are stacked on the packaging substrate 302 to form die stack 304, and the bottom die is attached in the second region 302-2 of the packaging substrate 302. Before stacking the plurality of dies 306, each die 306 may be processed to form one or more TSVs 308, and each TSV 308 may include a landing pad 310, which enhances the contact between each pair of connecting structure 312 and TSV 308. In some implementations, before stacking the plurality of dies 306, each die 306 may also be processed to form one or more contact pads 320 on the opposite side of TSV 308. The plurality of dies 306 are stacked in the vertical direction, and edges of adjacent dies 306 are misaligned, such that each TSV 308 of the upper one of the adjacent two dies 306 contacts a corresponding one of the connecting structures 312 standing on the packaging substrate 302. In some implementations, the plurality of dies 306 may be stacked by using an adhesive material, and the adhesive material may include thermally/electrically conductive metal to facilitate heat dissipation and reduce resistance. Since the dies 306 are misaligned with each other to form an offset 330, the lower one of the adjacent two dies 306 has a staircase portion 332 that is not covered by the upper one of the adjacent two dies 306, and the staircase portion contains the contact pad 320. To better bond the plurality of connecting structures 312 with the die stack 304, localized laser heating may be used to fuse each of the connecting structures with its respective die, which enhance the contact between connecting structures and their respective dies, hence promoting the power supply for the die stack 304.

In some implementations, after stacking the plurality of dies, method 500 may further include operation 508, in which at least one contact base 318 is formed on the third region of the packaging substrate 302-3.

In some implementations, method 500 may further include operation 510, in which the at least one contact base 318 is electrically connected with contact pad 320 of the bottom one of the plurality of dies, and contact pad 320 is wired together with each other such that different dies 306 are electrically connected with each other.

In some implementations, after wiring all the dies with each other and to the packaging substrate, method 500 may further include operation 512, which involves encapsulating the dies, the connecting structures, and wires inside an insulating material 326. In some implementations, method 500 may also include forming a plurality of solder ball 328 on the bottom surface of the packaging substrate 302.

FIG. 6 illustrates a flow chart of an exemplary method 600 of forming an IC device packaging base, according to some implementations. FIGs. 4a-4b illustrate schematic diagrams of an exemplary IC device 400 in a cross-sectional side view at certain fabricating stages of method 600, according to some implementations. It is understood that the operations shown in method 600 are not exhaustive and other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 6.

Referring to FIG. 6, method 600 starts at operation 602, in which a packaging substrate 402 is provided. FIG. 4a illustrates a corresponding structure. As shown in FIG. 4a, the packaging substrate 402 has three regions including first region 402-1, second region 402-2, and third region 402-3. In some implementations, operation 602-1 may be performed to form a plurality of seed bases 414 in first region 402-1, and operation 602-2 may be performed to form at least one contact base 418 in third region 402-3. The second region 402-2 having neither connecting structures nor contact base may be set aside for attaching dies. In some implementations, an embedded interconnect layer 416 may be formed inside packaging substrate 402 for electrically connecting the seed bases 414 and the contact base 418. In some implementations, the seed bases 414 may contain copper or copper alloys. The contact base 418 may include a material selected from copper, copper alloy, and gold.

Referring back to FIG. 6, after providing the packaging substrate, method 600 proceeds to operation 604, in which a plurality of connecting structures is formed. FIG. 4b illustrates a corresponding structure. As shown in FIG. 4b, a plurality of connecting structures 412 may be formed in the first region 402-1, extending in a vertical direction (e.g., z-direction) on the packaging substrate 402. In some implementations, forming each connecting structure may include operation 604-1, which involves forming an upper portion 412-1. In some implementations, forming each connecting structure may include operation 604-2, which involves forming a lower portion 412-2 on the packaging substrate 402. In some implementations, forming the lower portion 412-2 may include growing a conductive pillar by electroplating copper or copper alloy on a corresponding seed base. The heights of conductive pillars may be different, which may be controlled by the time of electroplating and concentration of precursor solutions. In some implementations, forming each connecting structure also includes forming a solder cap on the upper portion of each connecting structure. In some implementations, a plurality of solder balls 428 may be formed on the bottom surface of packaging substrate 402.

Referring back to FIG. 6, method 600 may further proceed to operation 606, in which at least one contact base 418 is formed on the third region of the packaging substrate 402-3. The at least one contact base 418 is configured to electrically connect with a bottom one of a plurality of dies to be attached on the packaging substrate 402.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

An integrated circuit (IC) device, comprising:

a packaging substrate comprising a first region, a second region, and a third region;

a plurality of connecting structures standing on the first region of the packaging substrate and configured for providing electric power to a plurality of dies;

the plurality of dies stacked in a vertical direction on the packaging substrate, wherein a bottom one of the plurality of dies is located within the second region of the packaging substrate; and

at least one contact base on the third region of the packaging substrate being electrically connected with at least one contact pad of the bottom one of the plurality of dies by at least one wiring line,

wherein each connecting structure extends in the vertical direction under a corresponding one of the plurality of dies and comprises:

an upper portion being in contact with a bottom surface of the corresponding one of the plurality of dies; and

a lower portion being in contact with the packaging substrate.
The IC device of claim 1, wherein:

edges of adjacent two dies of the plurality of dies are misaligned such that an upper one of the adjacent two dies has an extended portion located beyond a lower one of the adjacent two dies; and

the extended portion of the upper one of the adjacent two dies includes the bottom surface facing towards the packaging substrate and being in contact with the upper portion of a corresponding one of the plurality of connecting structures.
The IC device of claim 2, wherein:

the plurality of connecting structures are covered by the extended portions of the plurality of dies.
The IC device of claim 3, wherein:

the extended portion of the upper one of the adjacent two dies comprises a Through Silicon Via (TSV) that is in contact with the corresponding one of the plurality of connecting structures.
The IC device of claim 4, wherein the TSV comprises a landing pad in contact with one of the plurality of connecting structures.
The IC device of claim 5, wherein:

the upper portion of each of the plurality of connecting structures comprises a solder cap in contact with the landing pad of the TSV in the extended portion of the corresponding one of the plurality of dies; and

the lower portion of each of the plurality of connecting structures comprises a conductive pillar directly attaching to a corresponding one of a plurality of seed bases in the first region of the packaging substrate.
The IC device of claim 6, wherein a material of the conductive pillar comprises copper or copper alloys.
The IC device of claim 6, wherein the plurality of seed bases comprise copper or copper alloys, and each conductive pillar is grown on the corresponding one of the plurality of seed bases.
The IC device of claim 2, wherein:

the extended portion of the upper one of the adjacent two dies comprises a first offset in a first lateral direction with respect to the lower one of the adjacent two dies, the first offset is less than one-tenth of a width of the upper one of the adjacent two dies in the first lateral direction.
The IC device of claim 9, wherein:

the plurality of connecting structures comprises a first subset of connecting structures arranged along a second lateral direction perpendicular to the first lateral direction and connected with the bottom surface of the corresponding upper one of the adjacent two dies.
The IC device of claim 10, wherein:

the first subset of connecting structures comprises at least two rows of connecting structures arranged in straight lines in the second lateral direction, and in a staggered manner in the first lateral direction.
The IC device of claim 10, wherein:

the extended portion of the upper one of the adjacent two dies further comprises a second offset in the second lateral direction with respect to the lower one of the adjacent two dies; and

the plurality of connecting structures further comprises a second subset of connecting structures under the second offset aligned along the first lateral direction and connected with the bottom surface of the corresponding upper one of the adjacent two dies.
The IC device of claim 6, wherein the lower one of the adjacent two dies has a staircase portion that is uncovered by the upper one of the adjacent two dies, wherein the staircase portion of the lower one of the adjacent two dies has a top surface facing away from the packaging substrate and comprising at least one contact pad.
The IC device of claim 13, wherein adjacent ones of the plurality of dies are electrically connected with each other by wiring the at least one contact pad of each die together.
The IC device of claim 13, wherein the substrate comprises an embedded interconnect layer that electrically connects the plurality of seed bases with the at least one contact base.
The IC device of claim 1, wherein the plurality of dies comprises one or more phase-change memory (PCM) dies.
The IC device of claim 16, wherein a material of the one or more PCM dies comprises a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .
The IC device of claim 17, wherein the plurality of dies comprises a Central Processing Unit (CPU) die.
An integrated circuit (IC) packaging base, comprising:

a packaging substrate comprising a first region, a second region, and a third region; and

a plurality of connecting structures standing on the first region of the packaging substrate and configured for providing electric power to a plurality of dies; and

at least one contact base on the third region of the packaging substrate configured to electrically connect with at least one contact pad of a bottom one of the plurality of dies by at least one wiring line,

wherein each connecting structure extends in a vertical direction and comprises:

an upper portion configured to contact with a bottom surface of the corresponding one of the plurality of dies, and

a lower portion being in contact with the packaging substrate.
The IC packaging base of claim 19, wherein:

the plurality of connecting structures has different heights in the vertical direction.
The IC packaging base of claim 20, wherein:

the upper portion of each of the plurality of connecting structures comprises a solder cap configured to connect with a corresponding one of the plurality of dies; and

the lower portion of each of the plurality of connecting structures comprises a conductive pillar directly attaching to a corresponding one of a plurality of seed bases in the first region of the packaging substrate.
The IC packaging base of claim 21, wherein a material of the conductive pillar comprises copper or copper alloys.
The IC packaging base of claim 22, wherein the plurality of seed bases comprise copper or copper alloys, and each conductive pillar is grown on the corresponding one of the plurality of seed bases.
The IC packaging base of claim 20, wherein the plurality of connecting structures comprises a first subset of connecting structures arranged along a second lateral direction perpendicular to a first lateral direction.
The IC packaging base of claim 24, wherein:

the first subset of connecting structures comprises at least two rows of connecting structures arranged in straight lines in the second lateral direction, and in a staggered manner in the first lateral direction.
The IC packaging base of claim 21, wherein the substrate comprises an embedded interconnect layer that electrically connects the plurality of seed bases with the at least one contact base.
A method for packaging an integrated circuit (IC) device, comprising:

providing a packaging substrate comprising a first region, a second region, and a third region;

forming a plurality of connecting structures extending in a vertical direction on the first region of the packaging substrate, wherein a lower portion of each connecting structure is in electric contact with the packaging substrate;

stacking a plurality of dies in the vertical direction on the packaging substrate in a misaligned manner, such that an upper portion of each connecting structure is in electric contact with a bottom surface of the corresponding one of the plurality of dies, wherein a bottom one of the plurality of dies is located within the second region of the packaging substrate;

forming at least one contact base on the third region of the packaging substrate; and

electrically connecting the at least one contact base with at least one contact pad of the bottom one of the plurality of dies by at least one wiring line.
The method of claim 27, wherein stacking the plurality of dies comprises:

misaligning edges of adjacent two dies such that an upper one of the adjacent two dies has an extended portion located beyond a lower one of the adjacent two dies, wherein:

the extended portion of the upper one of the adjacent two dies comprises the bottom surface facing towards the packaging substrate and being in electric contact with the upper portion of a corresponding one of the plurality of connecting structures; and

the extended portions covers the plurality of connecting structures.
The method of claim 28, further comprising:

forming a Through Silicon Via (TSV) in the extended portion of the upper one of the adjacent two dies before stacking the plurality of dies, wherein stacking the plurality of dies comprises landing the TSV with the corresponding one of the plurality of connecting structures.
The method of claim 29, wherein forming the TSV comprises forming a landing pad on a lower end of the TSV for landing to the corresponding one of the plurality of connecting structures.
The method of claim 30, wherein forming one of the plurality of connecting structures comprises:

forming a conductive pillar on one of a plurality of seed bases in the packaging substrate as the lower portion of the one of the plurality of connecting structures; and

forming a solder cap on the conductive pillar as the upper portion of the one of the plurality of connecting structures for connecting with the landing pad of the TSV in the extended portion of the corresponding one of the plurality of dies.
The method of claim 31, wherein forming the conductive pillar comprises electroplating copper or copper alloys on the one of the plurality of seed bases.
The method of claim 28, wherein stacking the plurality of dies comprises:

offsetting a first edge of the extended portion of the upper one of the adjacent two dies at a first distance in a first lateral direction with respect to a first edge of the lower one of the adjacent two dies, wherein the first distance is less than one-tenth of a width of the upper one of the adjacent two dies in the first lateral direction.
The method of claim 33, wherein:

forming the plurality of connecting structures comprises forming a first subset of connecting structures aligned along a second lateral direction perpendicular to the first lateral direction; and

stacking the plurality of dies comprises connecting the first subset of connecting structures to the bottom surface of the corresponding upper one of the adjacent two dies.
The method of claim 34, wherein:

forming the first subset of connecting structures comprises forming at least two rows of connecting structures arranged in straight lines in the second lateral direction, and in a staggered manner in the first lateral direction.
The method of claim 33, further comprising offsetting the first edge of the extended portion of the upper one of the adjacent two dies to expose a top surface of a staircase portion of the lower one of the adjacent two dies, wherein the top surface of the staircase portion of the lower one of the adjacent two dies faces away from the packaging substrate and comprising at least one contact pad.
The method of claim 36, further comprising electrically connecting adjacent ones of the plurality of dies with each other by wiring the at least one contact pad of each die together.
The method of claim 37, wherein providing the packaging substrate further comprises forming an embedded interconnect layer that electrically connects the plurality of seed bases with the at least one contact base.
The method of claim 27, forming a plurality of dies comprises stacking one or more phase-change memory (PCM) dies with at least one Central Processing Unit (CPU) die.
A method for forming an integrated circuit (IC) packaging base, comprising:

providing a packaging substrate comprising a first region, a second region, and a third region; and

forming a plurality of connecting structures extending in a vertical direction on the first region of the packaging substrate, wherein a lower portion of each connecting structure is in electric contact with the packaging substrate and an upper portion of each connecting structure is configured to contact with a bottom surface of a corresponding one of a plurality of dies; and

forming at least one contact base on the third region of the packaging substrate configured to electrically connect with at least one contact pad of a bottom one of the plurality of dies by at least one wiring line.
The method of claim 40, wherein:

forming the plurality of connecting structures comprises forming connecting structures having different heights in the vertical direction.
The method of claim 41, wherein forming one of the plurality of connecting structures comprises:

forming a conductive pillar on one of a plurality of seed bases in the first region of the packaging substrate as the lower portion of the one of the plurality of connecting structures; and

forming a solder cap on the conductive pillar as the upper portion of the one of the plurality of connecting structures for connecting with the corresponding one of the plurality of dies.
The method of claim 42, wherein forming the conductive pillar comprises electroplating copper or copper alloys on the one of the plurality of seed bases.
The method of claim 40, wherein:

forming the plurality of connecting structures comprises forming a first subset of connecting structures arranged along a second lateral direction perpendicular to a first lateral direction.
The method of claim 44, wherein:

forming the first subset of connecting structures comprises forming at least two rows of connecting structures arranged in straight lines in the second lateral direction, and in a staggered manner in the first lateral direction.
The method of claim 42, providing the packaging substrate further comprises forming an embedded interconnect layer that electrically connects the plurality of seed bases with the at least one contact base.