TWI451505B - 凹入的半導體基底和相關技術 - Google Patents

凹入的半導體基底和相關技術 Download PDF

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Publication number
TWI451505B
TWI451505B TW100103448A TW100103448A TWI451505B TW I451505 B TWI451505 B TW I451505B TW 100103448 A TW100103448 A TW 100103448A TW 100103448 A TW100103448 A TW 100103448A TW I451505 B TWI451505 B TW I451505B
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Taiwan
Prior art keywords
semiconductor substrate
redistribution layer
molding compound
package
dielectric film
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TW100103448A
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English (en)
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TW201140714A (en
Inventor
Albert Wu
Roawen Chen
Chung-Chyung Han
Shiann-Ming Liou
Chien-Chuan Wei
Runzi Chang
Scott Wu
Chuan-Cheng Cheng
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Marvell World Trade Ltd
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Publication of TW201140714A publication Critical patent/TW201140714A/zh
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Publication of TWI451505B publication Critical patent/TWI451505B/zh

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    • H01L2924/19043—Component type being a resistor
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

凹入的半導體基底和相關技術
本公開的實施方式涉及集成電路領域，並且更具體而言，本公開的實施方式涉及用於封裝組件的凹入的半導體基底的技術、結構和配置。
本文所提供的背景技術描述是以對本公開的內容作一般性說明為目的。在背景技術部分描述的範圍內，目前提及姓名的發明人的工作，以及本說明書在提交申請時可能尚未成為現有技術的方面，無論明示地還是暗含地，都不應認為是針對本公開的現有技術。
在裸片或晶片上形成諸如晶體管之類的集成電路器件，該裸片或晶片的尺寸持續等比例縮小至更小尺寸。裸片的縮減尺寸正挑戰傳統基底製造技術和/或封裝組件技術，該傳統基底製造技術和/或封裝組件技術當前用於向半導體裸片路由電信號或從半導體裸片路由出電信號。舉例而言，層壓基底技術可能不能在基底上製作足夠小的特徵以符合更細微的節距的互連或在所述裸片上形成的其他信號路由特徵。
在一個實施方式中，本公開提供了一種方法，包括提供具有(i)第一表面和(ii)與所述第一表面相反佈置的第二表面的半導體基底，在所述半導體基底的第一表面中形成一個或更多個過孔，所述一個或更多個過孔初始僅穿過所述半導體基底的一部分而不到達所述第二表面，在所述半導體基底的第一表面上形成電介質膜，在所述電介質膜上形成再分佈層，所述再分佈層電耦合至所述一個或更多個過孔，將一個或更多個裸片耦合至所述再分佈層，形成模塑膠以封裹所述一個或更多個裸片的至少一部分，並使所述半導體基底的第二表面凹入以暴露所述一個或更多個過孔。
在另一實施方式中，本公開提供一種方法，所述方法包括提供具有(i)第一表面和(ii)與所述第一表面相反佈置的第二表面的半導體基底，在所述半導體基底的第一表面上形成電介質膜，在所述電介質膜上形成再分佈層，將一個或更多個裸片耦合至所述再分佈層，形成模塑膠以封裹所述一個或更多個裸片的至少一部分，使所述半導體基底的第二表面凹入，並在所述半導體基底的第二表面中形成一個或更多個過孔，所述一個或更多個過孔(i)穿過所述半導體基底至所述半導體基底的第一表面並(ii)與所述再分佈層電耦合。
在另一實施方式中，本公開提供了一種設備，所述設備包括：半導體基底，所述半導體基底具有第一表面、與所述第一表面相反佈置的第二表面、形成於所述第一表面上的電介質膜、形成於所述電介質膜上的再分佈層、以及形成於所述半導體基底中以在所述再分佈層和所述半導體基底的第二表面之間提供電通路的一個或更多個過孔；耦合至所述再分佈層的裸片；以及形成於所述半導體基底的第一表面上的模塑膠。
本公開要求2010年2月3日提交的第61/301,125號美國臨時專利申請、2010年3月22日提交的第61/316,282號美國臨時專利申請、2010年4月5日提交的第61/321,068號美國臨時專利申請和2010年4月16日提交的第61/325,189號美國臨時專利申請的優先權，除了與本說明書不一致之處的部分(如果存在這些部分)外，以上專利申請的整個說明書在此通過引用全文併入本文用於所有目的。
本公開的實施方式描述具有凹入區域的半導體基底和相關封裝組件的技術、結構和配置。
本說明書可能使用基於視角的描述，例如上/下、之上/之下和/或頂部/底部。這類描述僅用於方便論述，並非意于將本文所述實施方式應用限制於任何特定的方向。
為了本公開的目的，用語“A/B”意味著A或B。為了本公開的目的，用語“A和/或B”意味著“(A)、(B)或(A和B)”。為了本公開的目的，用語“A、B和C中至少一個”意味著“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)”。為了本公開的目的，用語“(A)B”意味著“(B)或(AB)”，也即，A是可選項。
以最有助於理解請求項主題的方式，描述了作為相繼的多個分立操作的各種操作。然而，描述的順序不應被解釋為暗示這些操作是必須依此順序。具體而言，這些操作可不以所呈現的順序來執行。所描述的操作可以與所描述的實施方式不同的順序來執行。在附加的實施方式中可執行各種附加的操作和/或可省略所描述的操作。
說明書使用用語“在實施方式中”、“在一些實施方式中”或類似語言，所述用語可均指一個或更多個相同的或不同的實施方式。此外，針對本公開的實施方式所使用的術語“包括”、“含有”、“具有”等是同義詞。
圖1至圖6示意性地示出了各種實施例封裝組件的配置，所述封裝組件包括具有凹入表面的半導體基底102。圖1描繪了依照各種實施方式的封裝組件100的配置。封裝組件100包括半導體基底102，半導體基底102是大體上包括諸如矽(Si)之類的半導體材料的基底或內插板(interposer)。也即，半導體基底102的材料的主體是半導體材料。所述半導體材料可包括結晶類材料和/或無定形類材料。舉例而言，在該半導體材料是矽的情形中，該矽材料可包括單晶矽和/或多晶矽的類型。在其他的實施方式中，半導體基底102可包括其他半導體材料，例如鍺、III-V族材料或II-VI族材料，所述鍺、III-V族材料或II-VI族材料也可受益于本文所述的原理。
半導體基底102包括第一表面A1和與第一表面A1相反佈置的第二表面A2。第一表面A1和第二表面A2一般指半導體基底102的相反表面以便於描述本文中所述的各種配置。
依據各種實施方式，所述半導體基底的第二表面A2是凹入的。凹入的第二表面A2一般提供半導體基底102的相對較薄區域以便於穿過基底102的一個或更多個過孔104的形成。在一些實施方式中，半導體基底102是凹入的以具有在約10微米和約500微米之間的厚度T。
一般而言，使用類似於製造裸片上或晶片上的集成電路(IC)結構的那些技術來製造半導體基底102。舉例而言，可使用眾所周知的諸如光刻/刻蝕和/或沉積工藝之類的用於製造裸片上的IC器件的構圖工藝來形成半導體基底102的特徵。通過使用半導體製造技術，半導體基底102可包括比其他類型基底更小的特徵，所述其他類型基底例如層壓(例如有機)基底。對於持續縮減尺寸的裸片而言，半導體基底102便於路由諸如輸入信號/輸出信號(I/O)和/或電源信號/接地信號之類的電信號。舉例而言，在一些實施方式中，半導體基底102允許細微節距的Si對Si互連和在半導體基底102和一個或更多個裸片108之間路由的最終線路。
依據各種實施方式，形成一個或更多個過孔104穿過半導體基底102。所述一個或更多個過孔104提供半導體基底102的第一表面A1和第二表面A2之間的電通路。所述一個或更多個過孔104一般包括導電和/或導熱的材料，例如金屬。電介質材料(例如圖7C的電介質膜105)可佈置於所述一個或更多個過孔104的金屬和半導體基底102的半導體材料之間。在半導體基底102包括矽的實施方式中，所述一個或更多個過孔104是一個或更多個矽貫通孔(TSV)。
在所述半導體基底的第一表面A1和/或第二表面A2上形成電介質膜(例如圖7L的電介質膜105)。類似於連同例如圖7B至圖7M、圖8A至圖8G或圖9A至圖9H所描繪的電介質膜105，所述電介質膜可配置于封裝組件100和圖2至圖6的其他封裝組件中。在圖1至圖6中未描繪所述電介質膜以避免混淆這些圖的各方面。舉例而言，所述電介質膜可包括二氧化矽(SiO2 )、氮化矽(SiN)、氮氧化矽(SiOx Ny )或其他合適的電介質材料。所述電介質膜一般對佈置於半導體基底102之上的導電材料提供電絕緣以防止所述導電材料和半導體基底102的半導體材料(例如矽)之間的電流洩漏。
在半導體基底102上形成一個或更多個再分佈層106以路由耦合至半導體基底102的所述一個或更多個裸片108的電信號。舉例而言，所述一個或更多個再分佈層106在所述一個或更多個裸片108和所述一個或更多個過孔104之間可提供電路由。所述一個或更多個再分佈層106一般包括諸如金屬(例如銅或鋁)之類的導電材料。在其他實施方式中，也可使用其他合適的導電材料以形成所述一個或更多個再分佈層106。
所述一個或更多個再分佈層106可包括多種結構以路由電信號，所述多種結構例如焊盤、焊區或跡線。儘管未描繪出，但在所述一個或更多個再分佈層106上可沉積包括電絕緣材料的鈍化層，並對所述鈍化層進行構圖以提供所述鈍化層中的開口，從而允許所述一個或更多個裸片108與所述一個或更多個再分佈層106電耦合，所述電絕緣材料例如聚醯亞胺。
一個或更多個裸片108耦合至半導體基底102。所述一個或更多個裸片108一般包括半導體材料，例如矽。在一個實施方式中，使用相同的半導體材料製造所述一個或更多個裸片108和半導體基底102，從而降低與材料的加熱/冷卻不匹配有關的應力，例如不匹配的熱膨脹係數(CTE)。
可以使用任何合適的配置將所述一個或更多個裸片108耦合至半導體基底102。所述一個或更多個裸片108一般具有有源側和與所述有源側相反佈置的無源側，所述有源側包括的表面上形成有多個集成電路(IC)器件(圖中未示出)，所述集成電路器件例如用於邏輯和/或存儲器的晶體管。所述一個或更多個裸片108的有源側電耦合至所述一個或更多個再分佈層106。
在一些實施方式中，如所見，在倒裝晶片配置中使用一個或更多個凸點110將所述一個或更多個裸片108的有源側耦合至所述一個或更多個再分佈層106。在其他一些實施方式中，使用其他結構將所述一個或更多個裸片108的有源側電耦合至所述一個或更多個再分佈層106，所述其他結構例如用以提供引線鍵合配置的一個或更多個鍵合引線。
所述一個或更多個凸點110一般包括諸如焊料或其他金屬之類的導電材料以路由所述一個或更多個裸片108的電信號。依據各種實施方式，所述一個或更多個凸點110包括鉛、金、錫、銅、無鉛材料或它們的組合。所述一個或更多個凸點110可具有多種形狀並可通過使用凸點成形工藝形成，所述多種形狀包括球形、圓柱形、矩形或其他形狀，所述凸點成形工藝例如受控坍塌晶片連接(C4)工藝、柱形凸點成形(stud-bumping)工藝或其他的合適工藝。
雖然圖中未示出，但一個或更多個其他的有源組件或者無源組件可安裝在半導體基底102上。所述組件可包括電子元件和集成電路(IC)。舉例而言，所述組件可包括過濾器組件、電阻器、電感器、功率放大器、電容器或經封裝的IC。在其他實施方式中，其他的有源組件或無源組件可耦合至半導體基底102。
模塑膠112佈置於半導體基底102的第一表面A1上。模塑膠112一般包括諸如熱固樹脂之類的電絕緣材料，佈置所述電絕緣材料以保護所述一個或更多個裸片108免於與操縱相關聯的碎裂、氧化或濕氣。在一些實施方式中，如所見，佈置模塑膠112大體上封裹所述一個或更多個裸片108並大體上填充所述一個或更多個裸片108和半導體基底102之間(例如所述一個或更多個凸點110之間)的區域。可選擇模塑膠112以具有與半導體基底102和/或所述一個或更多個裸片108的熱膨脹係數(CTE)相同或相似的熱膨脹係數，從而降低與不匹配的熱膨脹係數材料相關聯的應力。
在所述一個或更多個再分佈層106上形成諸如一個或更多個焊料球或焊料柱之類的一個或更多個封裝互連結構114以進一步路由一個或更多個裸片108的電信號。在所描繪的實施方式中，所述一個或更多個封裝互連結構114耦合至所述半導體基底的第二表面A2上的一個或更多個再分佈層106。所述一個或更多個封裝互連結構114一般包括導電材料。所述一個或更多個封裝互連結構114可形成為多種形狀並可放置成多種定位，所述多種形狀包括球形、平面形狀或多邊形形狀，所述多種定位包括成行或多行的陣列。儘管所述一個或更多個封裝互連結構114描繪在半導體基底102的外圍部分上，但在其他實施方式中，所述一個或更多個封裝互連結構114可佈置在半導體基底102的中心部分上或靠近中心部分。在一些實施方式中，所述一個或更多個封裝互連結構114配置成球柵陣列(BGA)配置。
可以使用所述一個或更多個封裝互連結構114將封裝組件100電耦合至另一電子器件150，以進一步將所述一個或更多個裸片108的電信號路由至其他的電子器件150。舉例而言，所述其他的電子器件150可包括印刷電路板(PCB)(例如主板)、模塊或另一封裝組件。
圖2描繪了依照各種實施方式的封裝組件200的配置。封裝組件200包括與關於圖1的封裝組件100描述的實施方式相一致的半導體基底102、一個或更多個過孔104、一個或更多個再分佈層106、一個或更多個裸片108、一個或更多個凸點110、模塑膠112以及一個或更多個封裝互連結構114。在圖2中，模塑膠112還形成於半導體基底102的第二表面A2上。暴露出所述一個或更多個封裝互連結構114的至少一部分以將所述一個或更多個裸片108的電信號路由至另一電子器件(例如圖1的其他電子器件150)。
圖3描繪了依照各種實施方式的封裝組件300的配置。封裝組件300包括與分別關於圖1和圖2的封裝組件100和封裝組件200描述的實施方式相一致的半導體基底102、一個或更多個過孔104、一個或更多個再分佈層106、一個或更多個裸片108、一個或更多個凸點110、模塑膠112以及一個或更多個封裝互連結構114。在圖3中，所述一個或更多個裸片108中的至少一個耦合至佈置於半導體基底102的第二表面A2上的所述一個或更多個再分佈層106。所述一個或更多個裸片108可佈置在半導體基底102的第一表面A1和第二表面A2二者上。
圖4描繪了依照各種實施方式的封裝組件400的配置。封裝組件400包括與分別關於圖1、圖2和圖3的封裝組件100、封裝組件200和封裝組件300描述的實施方式相一致的半導體基底102、一個或更多個過孔104、一個或更多個再分佈層106、一個或更多個裸片108、一個或更多個凸點110、模塑膠112以及一個或更多個封裝互連結構114。
在圖4中，如所見，底部填充材料116佈置於所述一個或更多個裸片108中的至少一個和半導體基底102之間。舉例而言，底部填充材料116可包括環氧樹脂或其他合適的電絕緣材料。底部填充材料116一般增加所述一個或更多個裸片108與半導體基底102之間的粘附，在所述一個或更多個凸點110之間提供附加的電絕緣，和/或保護一個或更多個凸點110免於濕氣和氧化。
在一些實施方式(未示出)中，底部填充材料116可由模塑膠112封裹。舉例而言，底部填充材料116可佈置於所述一個或更多個裸片108和半導體基底102之間以封裹所述一個或更多個凸點110，並且可佈置模塑膠112以封裹所述一個或更多個裸片108和底部填充材料116。
圖5描繪了依照各種實施方式的封裝組件500的配置。封裝組件500包括與分別關於圖1、圖2、圖3和圖4的封裝組件100、封裝組件200、封裝組件300和封裝組件400描述的實施方式相一致的半導體基底102、一個或更多個過孔104、一個或更多個再分佈層106、一個或更多個裸片108、一個或更多個凸點110、模塑膠112以及一個或更多個封裝互連結構114。
在圖5中，所述一個或更多個封裝互連結構114中的至少一個耦合至佈置在半導體基底102的第一表面A1上的一個或更多個再分佈層106。所述一個或更多個封裝互連結構114可佈置在半導體基底102的第一表面A1和第二表面A2二者上以路由所述一個或更多個裸片108的電信號。
如所見，使用第一表面A1上的一個或更多個封裝互連結構114可將封裝組件500耦合至另一電子器件150，並且使用第二表面A2上的一個或更多個封裝互連結構114可將封裝組件500進一步耦合至另一電子器件150。舉例而言，可使用第二表面A2上的一個或更多個封裝互連結構114將所述一個或更多個裸片108的電信號路由至其上安裝有封裝組件500的印刷電路板(例如主板)。可使用第一表面A1上的一個或更多個封裝互連結構114將所述一個或更多個裸片108的電信號路由至堆疊于封裝組件500上的另一封裝組件，從而提供層疊封裝(PoP)配置。
圖6A描繪了依照各種實施方式的封裝組件600A的配置。封裝組件600A包括與分別關於圖1、圖2、圖3、圖4和圖5的封裝組件100、封裝組件200、封裝組件300、封裝組件400和封裝組件500描述的實施方式相一致的半導體基底102、一個或更多個過孔104、一個或更多個再分佈層106、一個或更多個裸片108、一個或更多個凸點110、模塑膠112以及一個或更多個封裝互連結構114。
在圖6A中，如所見，形成模塑膠112以暴露出所述一個或更多個裸片108中的至少一個的表面。所述一個或更多個裸片108的暴露出的表面便於從所述一個或更多個裸片108散熱。
圖6B描繪了依照各種實施方式的封裝組件600B的配置。封裝組件600B類似於圖6A的封裝組件600A，但是封裝組件600B還包括諸如熱沉之類的散熱結構675。散熱結構675熱耦合至示出的一個或更多個裸片108的背側。在一些實施方式中，在半導體基底102的第一表面A1上形成的一個或更多個封裝互連結構114便於從封裝組件600B處散熱。在其他實施方式中，所述一個或更多個封裝互連結構114根本不形成於半導體基底102的第一表面A1上，並且模塑膠112填充第一表面A1上由圖6B的一個或更多個封裝互連結構114所占的區域。
本文所述的技術和配置可提供如下益處：降低與在半導體基底102中製造一個或更多個過孔104相關聯的工藝複雜度和/或成本，促使利用半導體基底102的兩側，便於實現多堆疊封裝配置，降低封裝組件的尺寸，和/或提高散熱。在一些實施方式中，封裝組件100、200、300、400、500和600是最終的封裝組件，該最終封裝組件安裝於或準備安裝於諸如印刷電路板之類的另一電子器件上。關於圖1至圖6描述的實施方式的合適組合位於本公開的範圍內。
圖7A至圖7M示意性地示出了各種工藝操作之後的封裝組件700。關於圖7A至圖7M描述的操作與製造封裝組件700的方法(例如圖10的方法1000)相對應，其中，在如本文所述的下述步驟中至少之一前大體形成所述一個或更多個過孔104：形成一個或更多個再分佈層106，將所述一個或更多個裸片108耦合至半導體基底102，形成模塑膠112，以及使半導體基底102的表面凹入。
參見圖7A，描繪了在半導體基底102的第一表面A1中形成一個或更多個溝槽103之後的封裝組件700。所述一個或更多個溝槽103是作為在半導體基底102中形成一個或更多個過孔(例如圖7C的一個或更多個過孔104)的一部分從半導體基底102移除半導體材料的區域。舉例而言，使用刻蝕工藝或鐳射鑽孔工藝，通過選擇性地移除半導體材料可形成所述一個或更多個溝槽103。如所見，所述一個或更多個溝槽103僅穿過半導體基底102的一部分。也即，形成於第一表面A1中的一個或更多個溝槽103並未到達半導體基底102的第二表面A2。
參見圖7B，如所見，描繪了在半導體基底102的第一表面A1和第二表面A2上，包括在所述一個或更多個溝槽103中的半導體基底102的表面(例如側壁)上，形成電介質膜105之後的封裝組件700。通過使用沉積技術沉積電介質材料可形成電介質膜105，所述沉積技術例如熱生長、物理氣相沉積(PVD)、化學氣相沉積(CVD)和/或原子層沉積(ALD)，所述電介質材料例如二氧化矽(SiO2 )、氮化矽(SiN)或氮氧化矽(SiOx Ny )，其中x和y代表合適的化學計量值。在其他實施方式中，可使用其他合適的沉積技術和/或電介質材料。
參見圖7C，描繪了在所述一個或更多個溝槽(例如圖7B的一個或更多個溝槽103)中沉積導電材料以大體上形成所述一個或更多個過孔104之後的封裝組件700。舉例而言，所述導電材料可包括銅或其他合適的金屬材料。
在一個實施方式中，沉積所述導電材料以大體上填充所述一個或更多個溝槽。在另一實施方式中，沉積所述導電材料以覆蓋所述一個或更多個溝槽表面上的電介質膜105，並且沉積諸如環氧樹脂、樹脂或氧化物之類的電絕緣材料以填充所述一個或更多個溝槽的剩餘部分。
參見圖7D，描繪了在佈置於半導體基底102的第一表面A1上的所述電介質膜105上形成一個或更多個再分佈層106之後的封裝組件700。所述一個或更多個再分佈層106電耦合至所述一個或更多個過孔104。通過使用任何合適的沉積技術沉積導電材料，可形成所述一個或更多個再分佈層106。沉積的所述導電材料可被構圖和/或刻蝕以提供路由一個或更多個裸片的電信號的路由結構。可堆疊多個再分佈層以提供期望的電信號路由。
參見圖7E，描繪了一個或更多個裸片108耦合至所述一個或更多個再分佈層106之後的封裝組件700。所述一個或更多個裸片108可以以多種配置耦合至半導體基底102，舉例而言，所述多種配置包括倒裝晶片配置或引線鍵合配置或它們的組合。在倒裝晶片配置中，如所見，使用一個或更多個凸點110將所述一個或更多個裸片108的有源表面耦合至所述一個或更多個再分佈層106。所述一個或更多個凸點110可包括微焊料凸點或銅柱形凸點。在其他實施方式中，可使用其他已知的裸片對晶片或裸片對裸片的鍵合技術。在引線鍵合配置(未示出)中，使用粘合劑將所述裸片的無源表面耦合至半導體基底，並且使用一個或更多個鍵合引線將所述裸片的有源表面耦合至所述一個或更多個再分佈層106。所述一個或更多個裸片108電耦合至所述一個或更多個過孔104。
參見圖7F，描繪了形成模塑膠112以封裹所述一個或更多個裸片108的至少一部分之後的封裝組件700。根據各種實施方式，模塑膠112通過沉積電絕緣材料來形成。舉例而言，通過向模具中沉積固體形態(例如粉末)的樹脂(例如熱固樹脂)並施加熱量和/或壓力以熔化所述樹脂，可形成模塑膠112。在其他實施方式中，可使用用於形成模塑膠112的其他已知的技術。
當半導體基底102是在晶片形態中或是在單個化形態中時，在半導體基底102上可形成模塑膠112。在所描繪的實施方式中，形成模塑膠112以封裹所述一個或更多個裸片108。
依據一些實施方式，如所見，可形成模塑膠112以大體上填充所述一個或更多個裸片108和半導體基底102之間(例如所述一個或更多個凸點110之間)的區域。在其他實施方式中，可連同模塑膠112一起使用底部填充材料(例如圖4的底部填充材料116)。也即，所述底部填充材料可佈置於所述一個或更多個裸片108和半導體基底102之間，並且可形成模塑膠112以封裹所述底部填充材料。
參見圖7G，描繪了使半導體基底102的第二表面A2凹入以暴露出所述一個或更多個過孔104之後的封裝組件700。半導體基底102的第二表面A2可通過多種合適的技術凹入，舉例而言，所述合適的技術包括研磨工藝或刻蝕工藝。在一些實施方式中，使半導體基底102凹入以具有約10微米至約500微米之間的厚度。在其他實施方式中，可使用其他的凹入技術和厚度。
依據各種實施方式，在凹入以暴露出一個或更多個過孔104的過程中，使用模塑膠112作為機械載體以支撐半導體基底102。在半導體基底102的凹入的第二表面A2上可執行附加的操作。
參見圖7H，描繪了在半導體基底102的凹入的第二表面A2上形成電介質膜105以及在第二表面A2上的電介質膜105上形成一個或更多個再分佈層106之後的封裝組件700。使用分別關於圖7B和圖7D描述的技術，可形成電介質膜105和所述一個或更多個再分佈層106。
參見圖7I，描繪了將附加的一個或更多個裸片108耦合至半導體基底102的第二表面A2上的一個或更多個再分佈層106之後的封裝組件700。使用關於圖7E描述的技術，可耦合所述附加的一個或更多個裸片108。
參見圖7J，描繪了在半導體基底102的第二表面A2上形成模塑膠112之後的封裝組件700。可以依據關於圖7F描述的實施方式形成模塑膠112。
參見圖7K，描繪了在模塑膠112中形成一個或更多個開口113以暴露出形成於半導體基底102的第一表面A1和/或第二表面A2上的一個或更多個再分佈層106之後的封裝組件700。舉例而言，通過使用鐳射工藝或刻蝕工藝，可形成所述一個或更多個開口113。所述一個或更多個再分佈層106可充當鐳射停止材料或刻蝕停止材料。
參見圖7L，描繪了通過所述一個或更多個開口(例如圖7K的一個或更多個開口113)將一個或更多個封裝互連結構114耦合至所述一個或更多個再分佈層106之後的封裝組件700。通過使用多種合適的工藝將導電材料沉積到所述一個或更多個開口中，可形成所述一個或更多個封裝互連結構114。舉例而言，可使用絲網印刷、電鍍、貼裝或其他眾所周知的工藝沉積所述導電材料。可在半導體基底102的第一表面A1和第二表面A2之一上或兩者上形成所述一個或更多個封裝互連結構114以將去往或來自封裝組件700的一個或更多個裸片108的電信號路由至另一電子器件(例如圖1的另一電子器件150)。
參見圖7M，描繪了封裝組件700以顯示，在一些實施方式中形成模塑膠112以使暴露出所述一個或更多個裸片108的表面，從而利於散熱。也即，舉例而言，可使用模具沉積模塑膠112，這樣所述一個或更多個裸片108具有暴露出的表面。在其他實施方式中，沉積模塑膠112以封裹所述一個或更多個裸片108，並且隨後通過化學機械拋光(CMP)使所述模塑膠112凹入，從而暴露出所述一個或更多個裸片108的表面。
圖8A至圖8G示意性地示出了其他各種工藝操作之後的圖7E的封裝組件700。關於圖8A至圖8G所述的操作與在形成模塑膠112之前將所述一個或更多個封裝互連結構114耦合至所述一個或更多個再分佈層106的技術相對應。
參見圖8A，描繪了將一個或更多個封裝互連結構114耦合至所述一個或更多個再分佈層106之後的圖7E的封裝組件700。通過使用多種合適的工藝沉積導電材料，可形成所述一個或更多個封裝互連結構114。舉例而言，可使用絲網印刷、電鍍、貼裝或其他眾所周知的工藝沉積導電材料。
參見圖8B，描繪了在半導體基底102上形成模塑膠112之後的圖8A的封裝組件700。在一些實施方式中，如所見，形成模塑膠112以大體上封裹所述一個或更多個封裝互連結構114。可以依據關於例如圖7F和圖7M所述的實施方式形成模塑膠112。
參見圖8C，描繪了使半導體基底102的第二表面A2凹入以暴露出所述一個或更多個過孔104之後的圖8B的封裝組件700。可以依據關於圖7G所述的實施方式使半導體基底102凹入。
參見圖8D，描繪了在半導體基底102的凹入的第二表面A2上形成電介質膜105和在第二表面A2上的電介質膜105上形成一個或更多個再分佈層106之後的圖8C的封裝組件700。使用分別關於圖7B和圖7D所述的技術可形成電介質膜105和一個或更多個再分佈層106。
參見圖8E，描繪了將附加的一個或更多個裸片108耦合至半導體基底102的第二表面A2上的一個或更多個再分佈層106之後的圖8D的封裝組件700。可以依據關於圖7E描述的實施方式耦合附加的一個或更多個裸片108。
參見圖8F，描繪了在半導體基底102的第二表面A2上形成附加的一個或更多個封裝互連結構114並形成模塑膠112之後的圖8E的封裝組件700。可以依據關於圖7F所述的實施方式形成模塑膠112。可以依據關於圖8A所述的實施方式形成附加的一個或更多個封裝互連結構114。
參見圖8G，描繪了在所述的模塑膠中形成一個或更多個開口113以暴露出所述一個或更多個封裝互連結構114的圖8F的封裝組件700。通過使用例如鐳射工藝或刻蝕工藝，可形成所述一個或更多個開口113。所述一個或更多個封裝互連結構114可充當鐳射停止材料或刻蝕停止材料。
圖9A至圖9H示意性地示出了各種工藝操作後的另一封裝組件900。關於圖9A至圖9H描述的操作與製造封裝組件900的方法(例如圖11的方法1100)相對應，其中，在如本文所述的下述步驟至少之一後大體形成一個或更多個過孔104：形成一個或更多個再分佈層106，將一個或更多個裸片108耦合至半導體基底102，形成模塑膠112，以及使半導體基底102的表面凹入。
參見圖9A，如所見，描繪了在半導體基底102的第一表面A1和第二表面A2上形成電介質膜105之後的封裝組件900。可以依據關於圖7B所述的實施方式形成電介資膜105。
參見圖9B，描繪了在佈置於半導體基底102的第一表面A1上的電介質膜105上形成一個或更多個再分佈層106之後的封裝組件900。可以依據關於圖7D所述的實施方式形成一個或更多個再分佈層106。
參見圖9C，描繪了將一個和更多個裸片108耦合至所述一個或更多個再分佈層106之後的封裝組件900。可以依據關於圖7E所述的實施方式耦合所述一個或更多個裸片108。
參見圖9D，描繪了形成模塑膠112以封裹所述一個或更多個裸片108的至少一部分之後的封裝組件900。可以依據關於圖7F所述的實施方式形成模塑膠112。
參見圖9E，描繪了使半導體基底102的第二表面A2凹入之後的封裝組件900。通過多種合適的技術可使半導體基底102的第二表面A2凹入，所述多種合適的技術包括研磨工藝或刻蝕工藝。使半導體基底102凹入以便於形成穿過半導體基底102的一個或更多個過孔(例如圖9G的一個或更多個過孔104)。在一些實施方式中，使半導體基底102凹入以具有約10微米至約500微米之間的厚度。在其他實施方式中，可使用其他凹入技術和厚度。依據各種實施方式，在凹入操作期間使用模塑膠112作為機械載體以支撐半導體基底102。
參見圖9F，如所見，描繪了在半導體基底102的第二表面A2中形成一個或更多個溝槽103並在所述半導體基底的第二表面A2上和在所述一個或更多個溝槽103內的表面上形成電介質膜105之後的封裝組件900。作為形成穿過半導體基底102的一個或更多個過孔(例如圖9G的一個或更多個過孔104)的一部分，形成所述一個或更多個溝槽103。所述一個或更多個溝槽103穿過半導體基底102至半導體基底102的第一表面A1。也即，如所見，在半導體基底102的第二表面A2中形成所述一個或更多個溝槽103，或穿過半導體基底102的第二表面A2形成所述一個或更多個溝槽103，從而暴露出一個或更多個再分佈層106。
通過選擇性地去除半導體基底102的半導體材料，可形成一個或更多個溝槽103。舉例而言，所述半導體基底的第二表面A2可借助光致抗蝕劑膜或硬掩模通過濕法或幹法刻蝕工藝被構圖以從所構圖的選定位置去除所述半導體材料。在一些實施方式中，使用選擇性刻蝕工藝，並且第一表面A1上的電介質膜105充當刻蝕停止層。然後，可去除電介質膜105的在所述一個或更多個溝槽103中的部分以暴露出所述一個或更多個再分佈層106。舉例而言，使用濕法或幹法構圖/刻蝕工藝或鐳射鑽孔工藝，可選擇性地去除電介質膜105的電介質材料。所述一個或更多個再分佈層106的導電材料可充當刻蝕/鐳射停止材料。
可在同一沉積操作過程中，在所述半導體基底的第二表面A2上和所述一個或更多個溝槽103內的表面上形成電介質膜105。可以依據關於圖7B所述的實施方式沉積電介質膜105。
參見圖9G，描繪了將導電材料沉積到所述一個或更多個溝槽中以形成所述一個或更多個過孔104之後的封裝組件900。所述一個或更多個過孔104電耦合至所述一個或更多個再分佈層106。可以依據關於圖7C所述的實施方式沉積所述導電材料。
參見圖9H，描繪了在半導體基底102的第二表面A2上的電介質膜105上形成一個或更多個再分佈層106之後的封裝組件900。可以依據關於圖7D所述的實施方式形成一個或更多個再分佈層106。
圖9H的封裝組件900還可進行關於圖7I至圖7M描述的操作和/或關於圖8A至圖8G描述的操作。應清楚的是，在一些實施方式中，可適當地組合關於圖7A至圖7M、圖8A至圖8G和圖9A至圖9H所描述的技術，並且這些技術處於本公開的範圍內。
圖10是用以製造封裝組件(例如圖7A至圖7M的封裝組件700)的方法1000的工藝流程圖。所述工藝流程圖描繪了方法1000，在該方法中，在本文所述的下列步驟至少之一前大體形成一個或更多個過孔(例如圖7C的一個或更多個過孔104)：形成一個或更多個再分佈層(例如圖7D的一個或更多個再分佈層106)，耦合一個或更多個裸片(例如圖7E的一個或更多個裸片108)，形成模塑膠(例如圖7F的模塑膠112)以及使表面(例如圖7G的第二表面A2)凹入。
在1002處，方法1000包括提供半導體基底(例如圖7A的半導體基底102)。所述半導體基底具有第一表面(例如圖7A的第一表面A1)，所述第一表面佈置成與第二表面(例如圖7A的第二表面A2)相反。
在1004處，方法1000還包括在所述半導體基底中形成一個或更多個過孔(例如圖7C的一個或更多個過孔104)。所述一個或更多個過孔形成於所述半導體基底的第一表面中，這樣它們初始僅穿過半導體基底的一部分而不到達所述第二表面。可以依據關於圖7A至圖7C所述的實施方式形成所述一個或更多個過孔。
在1006處，方法1000還包括在所述半導體基底上形成電介質膜(例如圖7B的電介質膜105)。所述電介質膜至少形成於所述半導體基底的第一表面上。依據各種實施方式，如關於圖7B所述地當所述電介質膜形成於一個或更多個溝槽(例如圖7B的一個或更多個溝槽103)的表面上時，所述電介質膜形成於所述半導體基底的第一表面上。可以依據關於圖7C所述的實施方式形成所述電介質膜。
在1008處，方法1000還包括在所述電介質膜上形成再分佈層(例如圖7D的一個或更多個再分佈層106)。可以依據關於圖7D所述的實施方式形成所述再分佈層。
在1010處，方法1000還包括將一個或更多個裸片(例如圖7E的一個或更多個裸片108)耦合至所述再分佈層。可以依據針對圖7E所述的實施方式耦合所述一個或更多個裸片。
在1012處，方法1000還包括在所述半導體基底上形成模塑膠(例如圖7F的模塑膠112)。可以依據關於圖7F的實施方式形成所述模塑膠。
在1014處，方法1000還包括使所述半導體基底的表面凹入以暴露所述一個或更多個過孔。使所述半導體基底的第二表面凹入以暴露形成於所述第一表面中的所述一個或更多個過孔。可以依據關於圖7G所述的實施方式使所述半導體基底凹入。
在1016處，方法1000還包括在凹入表面形成再分佈層。可以依據關於圖7H所述的實施方式凹入表面上可形成所述再分佈層。
在1018處，方法1000還包括將一個或更多個裸片耦合至所述凹入表面。可以依據關於圖7I所述的實施方式，將所述一個或更多個裸片耦合至所述凹入表面。
在1020處，方法1000還包括在所述凹入表面上形成模塑膠。可以依據關於圖7J所述的實施方式，在所述凹入表面上形成所述模塑膠。
在1022處，方法1000還包括將一個或更多個封裝互連結構耦合至所述再分佈層。可以依據關於圖7K至圖7L或關於圖8A至圖8G所述的實施方式，將所述一個或更多個封裝互連結構耦合至所述再分佈層。
圖11是用以製造封裝組件(例如圖9A至圖9H的封裝組件900)的另一方法1100的工藝流程圖。該工藝流程圖描繪了方法1100，其中，在如本文所述地下列步驟中的至少一個之後形成一個或更多個過孔(例如圖9G的一個或更多個過孔104)：形成一個或更多個再分佈層(例如圖9B的一個或更多個再分佈層106)，耦合一個或更多個裸片(例如圖9C的一個或更多個裸片108)，形成模塑膠(例如圖9D的模塑膠112)以及使表面(例如圖9E的第二表面A2)凹入。
在1102處，方法1100包括提供半導體基底(例如圖9A的半導體基底102)。所述半導體基底具有第一表面(例如圖9A的第一表面A1)，該第一表面與第二表面(例如圖9A的第二表面A2)相反佈置。
在1104處，方法1100還包括在所述半導體基底上形成電介質膜(例如圖9A的電介質膜105)。所述電介質膜至少形成於所述半導體基底的第一表面上。可以依據關於圖7C所述的實施方式形成所述電介質膜。
在1106處，方法1100還包括在所述電介質膜上形成再分佈層(例如圖9B的一個或更多個再分佈層)。可以依據關於圖9B所述的實施方式形成所述再分佈層。
在1108處，方法1100還包括將一個或更多個裸片(例如圖9C的一個或更多個裸片108)耦合至所述再分佈層。可以依據關於圖9C所述的實施方式耦合所述一個或更多個裸片。
在1110處，方法1100還包括在所述半導體基底上形成模塑膠(例如圖9D的模塑膠112)。可以依據關於圖9D所述的實施方式形成所述模塑膠。
在1112處，方法1100還包括使所述半導體基底的表面凹入。使所述半導體材料的第二表面凹入以便於在所述第二表面中形成一個或更多個過孔。可以依據關於圖9E所述的實施方式使所述半導體材料凹入。
在1114處，方法1100還包括形成一個或更多個過孔(例如圖9G的一個或更多個過孔104)穿過所述半導體基底。所述一個或更多個過孔形成於所述半導體基底的第二表面中以完全穿過所述半導體基底。也即，所述一個或更多個過孔到達所述半導體基底的第一表面並電耦合至形成於所述第一表面上的再分佈層。可以依據關於圖9F和圖9G所述的實施方式，將所述一個或更多個過孔形成於所述凹入表面中。
在1116處，方法1100還包括在所述凹入表面上形成再分佈層。可以依據關於圖9H所述的實施方式，在所述凹入表面上形成所述再分佈層。
在1118處，方法1100還包括將一個或更多個裸片耦合至所述凹入表面。可以依據關於方法1000的1018處所述的實施方式，將所述一個或更多個裸片耦合至所述凹入表面。
在1120，方法1100還包括在所述凹入表面上形成模塑膠。可以依據關於方法1000的1020處所述的實施方式，在所述凹入表面上形成所述模塑膠。
在1122，方法1100還包括將一個或更多個封裝互連結構耦合至所述再分佈層。可以依據關於圖7K至圖7L或圖8A至圖8G所述的實施方式，將所述一個或更多個封裝互連結構耦合至所述再分佈層。
雖然本文中已示出和描述特定實施方式，但是在不偏離本公開的範圍的情況下，可使用預計能實現相同目的的、多種備選的和/或等同的實施方式或實現方案替代示出的和描述的實施方式。本公開旨在覆蓋本文所論述的實施方式的任意修改或變化。因此，顯然本文所述的實施方式旨在僅由請求項及其等同含義限制。
100．．．封裝元件
102．．．半導體基底
103．．．溝槽
104．．．過孔
105．．．電介質膜
106．．．區域
108．．．裸片
110．．．再分佈層
112．．．模塑膠
113．．．開口
114．．．封裝互連結
116．．．底部填充材料
150．．．電子器件
200．．．封裝組件
300．．．封裝組件
400．．．封裝組件
500．．．封裝組件
600A．．．封裝組件
600B．．．封裝組件
675．．．散熱結構
700．．．封裝組件
900．．．封裝組件
A1．．．第一表面
A2．．．第二表面
T．．．厚度
通過下面的結合附圖的詳細描述，本公開的實施方式將易於理解。為了便於描述，相似的附圖標記表示相似的結構元件。通過實施例而非通過說明書附圖中的圖中的限制來說明本文的實施方式。
圖1至圖6B示意性地示出了各種實施例封裝組件的配置，所述封裝組件包括具有凹入表面的半導體基底。
圖7A至圖7M示意性地示出了各種工藝操作之後的封裝組件。
圖8A至圖8G示意性地示出了其他各種工藝操作之後的圖7E的封裝組件。
圖9A至圖9H示意性地示出了各種工藝操作之後的另一封裝組件。
圖10是用以製造封裝組件的方法的工藝流程圖。
圖11是用以製造封裝組件的另一方法的工藝流程圖。

Claims (47)

  1. 一種製造凹入的半導體封裝之方法，該方法包括：提供具有(i)第一表面和(ii)與所述第一表面相反佈置的第二表面的半導體基底；在所述半導體基底的第一表面中形成一個或更多個過孔，所述一個或更多個過孔初始僅穿過所述半導體基底的一部分而不到達所述第二表面；在所述半導體基底的第一表面上形成電介質膜；在所述電介質膜上形成再分佈層，所述再分佈層電耦合至所述一個或更多個過孔；將一個或更多個裸片耦合至所述再分佈層；形成模塑膠以封裹所述一個或更多個裸片的至少一部分；以及在形成(i)所述再分佈層及(ii)所述模塑膠之後，使所述半導體基底的第二表面凹入以暴露所述一個或更多個過孔。
  2. 如請求項1的方法，其中所述一個或更多個過孔通過以下方式形成：使用刻蝕工藝或鐳射鑽孔工藝去除所述半導體基底的半導體材料以在所述半導體基底中形成一個或更多個溝槽；在所述一個或更多個溝槽的表面上形成電介質膜，其中當在所述半導體基底的第一表面上形成所述電介質膜時，在所述一個或更多個溝槽的表面上形成所述電介質膜；以及將導電材料沉積到所述一個或更多個溝槽中。
  3. 如請求項1的方法，其中所述再分佈層通過以下方式形成：在所述電介質膜上沉積導電材料；對所沉積的導電材料進行構圖；以及刻蝕所構圖的導電材料以形成路由所述裸片的電信號的路由結構。
  4. 如請求項1的方法，其中在倒裝晶片配置中使用一個或更多個凸點將所述一個或更多個裸片耦合至所述再分佈層。
  5. 如請求項1的方法，其中通過沉積電絕緣材料來形成所述模塑膠以大體上封裹所述一個或更多個裸片。
  6. 如請求項1的方法，其中通過研磨工藝或刻蝕工藝使所述半導體基底凹入。
  7. 如請求項1的方法，其中使所述半導體基底凹入以具有在約10微米和約500微米之間的厚度。
  8. 如請求項1的方法，其中所述電介質膜是第一電介質膜，所述方法還包括：在所述半導體基底的凹入的第二表面上形成第二電介質膜。
  9. 如請求項8的方法，其中所述再分佈層是第一再分佈層，所述方法還包括：在所述第二電介質膜上形成第二再分佈層，所述第二再分佈層電耦合至所述一個或更多個過孔。
  10. 如請求項9的方法，其中所述一個或更多個裸片是一個或更多個第一裸片，所述方法還包括：將一個或更多個第二裸片耦合至所述第二再分佈層。
  11. 如請求項10的方法，其中所述模塑膠是第一模塑膠，所述方法還包括：形成第二模塑膠以大體上封裹所述一個或更多個第二裸片。
  12. 如請求項1的方法，還包括：將一個或更多個封裝互連結構耦合至所述再分佈層。
  13. 如請求項12的方法，其中所述一個或更多個封裝互連結構通過以下方式耦合至所述再分佈層：在所述模塑膠中形成一個或更多個開口以暴露所述再分佈層；以及將導電材料沉積到所述一個或更多個開口中以形成所述一個或更多個封裝互連結構。
  14. 如請求項12的方法，其中在形成所述模塑膠之前使所述一個或更多個封裝互連結構耦合至所述再分佈層。
  15. 如請求項1的方法，其中當所述半導體基底為晶片形態時，在所述半導體基底上形成所述模塑膠。
  16. 如請求項1的方法，其中：在形成所述模塑膠之前形成所述一個或更多個過孔；以及在使所述半導體基底的第二表面凹入的過程中，使用所述模塑膠作為機械載體以支撐所述半導體基底。
  17. 一種製造凹入的半導體封裝之方法，該方法包括：提供具有(i)第一表面和(ii)與所述第一表面相反佈置的第二表面的半導體基底；在所述半導體基底的第一表面上形成電介質膜；在所述電介質膜上形成再分佈層；將一個或更多個裸片耦合至所述再分佈層；形成模塑膠以封裹所述一個或更多個裸片的至少一部分；使所述半導體基底的第二表面凹入；以及在形成(i)所述再分佈層及(ii)所述模塑膠之後，在所述半導體基底的第二表面中形成一個或更多個過孔，所述一個或更多個過孔(i)穿過所述半導體基底至所述半導體基底的第一表面並(ii)電耦合至所述再分佈層。
  18. 如請求項17的方法，其中所述再分佈層通過以下方式形成：在所述電介質膜上沉積導電材料。
  19. 如請求項17的方法，其中在倒裝晶片配置中使用一個或更多個凸點將所述一個或更多個裸片耦合至所述再分佈層。
  20. 如請求項17的方法，其中通過沉積電絕緣材料來形成所述模塑膠以大體上封裹所述一個或更多個裸片。
  21. 如請求項17的方法，其中通過研磨工藝或刻蝕工藝使所述半導體基底凹入。
  22. 如請求項17的方法，其中使所述半導體基底凹入以具有在約10微米和約500微米之間的厚度。
  23. 如請求項17的方法，其中所述一個或更多個過孔通過以下方式形成：去除所述半導體基底的半導體材料以在所述半導體基底中形成一個或更多個溝槽；從所述一個或更多個溝槽去除所述電介質膜的電介質材料以暴露所述再分佈層；在所述一個或更多個溝槽的表面上形成電介質膜；以及向所述一個或更多個溝槽中沉積導電材料。
  24. 如請求項17的方法，其中所述電介質膜是第一電介質膜，所述方法還包括：在所述半導體基底的凹入的第二表面上形成第二電介質膜。
  25. 如請求項24的方法，其中所述再分佈層是第一再分佈層，所述方法還包括：通過在所述第二電介質膜上沉積導電材料，在所述第二電介質膜上形成第二再分佈層。
  26. 如請求項25的方法，其中所述一個或更多個裸片是一個或更多個第一裸片，所述方法還包括：將一個或更多個第二裸片耦合至所述第二再分佈層。
  27. 如請求項26的方法，其中所述模塑膠是第一模塑膠，所述方法還包括：形成第二模塑膠以大體上封裹所述一個或更多個第二裸片。
  28. 如請求項17的方法，還包括：將一個或更多個封裝互連結構耦合至所述再分佈層。
  29. 如請求項28的方法，其中所述一個或更多個封裝互連結構通過以下方式耦合至所述再分佈層：在所述模塑膠中形成一個或更多個溝槽以暴露所述再分佈層，以及 向所述一個或更多個溝槽中沉積導電材料以形成所述一個或更多個封裝互連結構。
  30. 如請求項28的方法，其中在形成所述模塑膠之前將所述一個或更多個封裝互連結構耦合至所述再分佈層。
  31. 如請求項17的方法，其中當所述半導體基底為晶片形態時，在所述半導體基底上形成所述模塑膠。
  32. 如請求項17的方法，其中：在形成所述模塑膠之後形成所述一個或更多個過孔；以及在使所述半導體基底的第二表面凹入的過程中，使用所述模塑膠作為機械載體以支撐所述半導體基底。
  33. 一種凹入的半導體封裝，包括：半導體基底，該半導體基底具有第一表面，與所述第一表面相反佈置的第二表面，在所述第一表面上形成的電介質膜，在所述電介質膜上形成的再分佈層，以及在所述半導體基底中形成的一個或更多個過孔以提供所述再分佈層和所述半導體基底的第二表面之間的電通路；耦合至所述再分佈層的裸片；以及形成於所述半導體基底的第一表面上的模塑膠，所述模塑膠封裹所述裸片的至少一部分。
  34. 如請求項33的凹入的半導體封裝，其中：所述半導體基底包括矽；以及所述一個或更多個過孔包括一個或更多個矽貫通孔(TSV)。
  35. 如請求項33的凹入的半導體封裝，其中所述半導體基底的第二表面是凹入的以便於在所述半導體基底中形成所述一個或更多個過孔。
  36. 如請求項33的凹入的半導體封裝，其中所述半導體基底具有在約10微米和約500微米之間的厚度。
  37. 如請求項33的凹入的半導體封裝，其中所述電介質膜是第一電介質膜，所述凹入的半導體封裝還包括：形成於所述半導體基底的第二表面上的第二電介質膜。
  38. 如請求項37的凹入的半導體封裝，其中所述再分佈層是第一再分佈層，所述凹入的半導體封裝還包括第二再分佈層，所述第二再分佈層(i)佈置於所述第二電介質膜上並(ii)與所述一個或更多個過孔電耦合。
  39. 如請求項38的凹入的半導體封裝，還包括：一個或更多個封裝互連結構，所述一個或更多個封裝互連結構耦合至所述第二再分佈層以路由所述裸片的電信號。
  40. 如請求項39的四入的半導體封裝，其中所述裸片是第一裸片，所述凹入的半導體封裝還包括：耦合至所述第二分佈層的第二裸片。
  41. 如請求項40的凹入的半導體封裝，其中所述模塑膠是第一模塑膠，所述凹入的半導體封裝還包括：在所述半導體基底的第二表面上形成的第二模塑膠。
  42. 如請求項41的凹入的半導體封裝，其中(i)所述第一模塑膠和(ii)所述第二模塑膠中的至少一個形成為暴露(i)所述第一裸片或(ii)所述第二裸片的相應表面。
  43. 如請求項40的凹入的半導體封裝，其中：使用一個或更多個第一凸點將所述第一裸片耦合至所述第一再分佈層；使用一個或更多個第二凸點將所述第二裸片耦合至所述第二再分佈層；所述模塑膠佈置於(i)所述第一裸片和所述半導體基底之間，所述凹入的半導體封裝還包括：佈置於(i)所述第二裸片和所述半導體基底之間的底部填充材料。
  44. 如請求項39的凹入的半導體封裝，其中所述一個或更多 個封裝互連結構包括一個或更多個第一封裝互連結構，所述凹入的半導體封裝還包括：耦合至所述第一再分佈層的一個或更多個第二封裝互連結構。
  45. 如請求項44的凹入的半導體封裝，其中：所述半導體基底是第一封裝組件的一部分；所述一個或更多個第一封裝互連結構配置成將所述裸片的電信號路由至印刷電路板；以及所述一個或更多個第二封裝互連結構配置成將所述裸片的電信號路由至第二封裝組件。
  46. 如請求項33的凹入的半導體封裝，其中：所述再分佈層包括金屬；以及所述一個或更多個過孔包括金屬。
  47. 如請求項46的凹入的半導體封裝，還包括：佈置於(i)所述一個或更多個過孔的金屬和(ii)所述半導體基底的半導體材料之間的電介質膜。
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