1345823* 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種打線連接型半導體封裝構造， 特別係有關於一種能低成本達到防止銲線短路與増加 黏晶強度之打線連接型半導體封裝構造。 【先前技術】 半導體封裝構造的演變持續朝向輕薄短小的趨勢， 封裝技術的改善是希望可以沿用既有的封裝設備製作 更微小的半導體封裝構造，但仍有其極限〃一旦既有低 成本的封裝元件，如銲線或液態黏膠，無法適用新一代 的半導體封裝規格，則須採用新的封裝元件至覆晶凸塊 或黏晶膠帶等等，甚至更換半導體封裝設備，將使得封 裝成本大幅的提高。 請參閱第1圖所示，早期一種習知的打線連接型半 導體封裝構造100包含一基板11〇、一液態黏膠12〇、 一0日>! 130、複數個銲線14〇以及一封膠體該基 板110係具有一上表面U1、一下表面以及複數個 設置於該上表面U1之連接指H3。該液態黏膠12〇係 黏接該晶片130之背面132，使其設置於該基板ιι〇之 該上表面1 11。然而在黏晶時，該液態黏膠^ 2 〇會有外 擴而污染該些連接指113之問題。因此，該基板110設 計該晶片130之邊緣至該些連接指113須有5〇〇至 60〇μπι寬度，以防止該液態黏膠12〇外擴至污染該連接 指⑴。藉由該些銲、線14〇係電性連接該晶月】之複 6 1345823* 數個銲墊133與該些連接指113，達到該晶片130與該 基板110之電性互連，其中該些銲墊133係設於該晶片 130之一主動面131。該封膠體150係密封該晶片130 與該些銲線140。然而，選用如環氧液膠之液態黏膠120 進行黏晶，具有低成本之優點，但溢膠問題嚴重，須加 大該些連接指113與該晶片130之間距，故該基板11〇 不符合微小化的要求。再者，習知該些銲線140係為正 打銲線，銲線之最大弧高係鄰近或位於該晶片130之邊 緣，以避免該些銲線140誤觸該晶片130之邊緣，故該 半導體封裝構造 100之整體封裝厚度難以進一步降 低。若嘗試直接將正打銲線改為逆打銲線（reverse bond) «雖可降低該些銲線140之弧高，但在模流壓力 極容易導致該些鲜線140誤觸該晶片130之邊緣，引發 電性短路或漏電流。 請參閱第2圖所示，另一種習知的打線連接型半導 體封裝構造200包含一基板210、一黏晶膠帶220、一 晶片230、複數個銲線240以及一封膠體250 〇該基板 210係具有一上表面211、一下表面212以及複數個連 接指213,其中該些連接指213係設置於該上表面2U。 該晶片230係利用該黏晶膠帶22〇之黏貼，使得該晶片 230之背面232可設置於該基板210之該上表面211。 由於該黏晶膠帶220不會有溢膠之問題，故該基板2 1 0 不需預留寬度進而縮小該基板210之使用面積，該些銲 線240係電性連接該晶片230之複數個銲墊233與該些 7 1345823' 連接指213 ’其中該些銲墊233係設於該晶片23 〇之 主動面231。該封膠體250係密封該晶片23〇與該些 線240。然而’膜片狀的黏晶谬帶220的成本與浪費 遠向於液態黏膠’導致封裝成本增加》上述該打線連 型半導體封裝構造200僅能解決溢膠及縮小基板之 題，無法達到降低整體封裝厚度。 【發明内容】 本發明之主要目的係在於提供一種打線連接型半 趙封裝構造，藉由一線支撐攔壩與液態黏膠運用在打 連接型半導體封裝的組合關係，限制液態黏膠的擴散 染以使基板之連接指可更加靠近於晶片，能低成本微 型設計而不會影響打線品質，另可増加黏晶強度與支 銲線’避免該些銲線因模流壓力或其它外力而碰觸該 片之邊緣導致短路。 本發明之次一目的係在於提供一種打線連接型半 • 體封裝構造，藉由一線支撐攔壩與複數個銲線運用在 線連接型半導趙封裝的組合關係，令該些銲線之最大 咼處係遠離晶片並概略相等於該線支樓攔壞之高度， 低成本薄型設計而不會影響打線品質，更可適用於多 片堆疊。 本發明之另一目的係在於提供—種打線連接型半 體封裝構造，有效減少基板使用面積進而降低成本， 可降低整體封裝構造之厚度，有利於半導體封裝構造 尺寸縮小。 銲 係 接 問 導 線 污 小 撐 晶 導 打 派 以 晶 導 並 之 8 Γ345823* 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種打線連接型半導截封裝 構造主要包含一基板、一液態黏膠、一第一晶片、複數 個銲線以及一線支樓摘塌。該基板係具有一黏晶區以及 複數個在該黏晶區之外的連接指。該液態黏膠係形成於 該黏晶區。該第一晶片係藉由該液態黏膠設置於該基板 之該黏晶區並具有複數個銲塑•。該些銲線係電性連接該 些銲墊與該些速接指。該線支撐攔壩係設置於該基板上 且在該黏晶區與該些連接指之間，並且該液態黏膠係黏 接該第一晶片、該基板與該線支撐棚壞。 本發明的目的及解決其技術問題還可採用以下技術 措施進—步實現。 在前述的打線連接型半導鱧封裝構造中，該線支撐 摘攝係可具有一不低於該第一晶片之高度，以避免該些 緩壓觸該第一晶片之邊緣。 在前述的打線連接型半導體封裝構造中，該些銲線 係可跨過該線支撐攔壩並可壓觸至該線支撐攔壩。 在前述的打線連接型半導趙封裝構造中，該線支撐 摘續係可選自於介電膠材、再塗施防銲層與被覆有電絕 、緣層之金屬物之其中之一。 在前述的打線連接型半導體封裝構造中，該第一晶 片係可具有一主動面、一背面以及複數個在該主動面與 該背面之間之側面。 在前述的打線連接型半導體封裝構造中，該液態黏 9 1345823. 谬係可黏接該第-晶片之背面並沿I該線Λ· # $ 接至該第一晶片之至少一側面。 在則述的打線連接型半導體封裝構造中，該液態黏 膠係可具有—溢出高度（fillet height)，其係高於該第一 :旁面但低於該第一晶片之該主動面。 在前述的打線連接型半導體封裝構造中，該線支撐 攔壞邀 1 # 、"弟一晶片之相鄰側面之間隙係可約相等於該 • 第一晶片之背面與該基板之間隙。 在别述的打線連接型半導體封裝構造中，該些銲墊 係可排列鄰近於該第一晶片之該主動面之邊緣。 I过的打線連接型半導體封裝構造中，該些鲜整 至該主動面之間距係可小於該線支撐攔壩之寬度。 在前述的打線連接型半導體封裝構造中，可另包含 有一封膠體，其係密封該第一晶片該些銲線與該線支 撐攔壩》 鲁 在前述的打線連接型半導體封裝構造中，可另包含 有至少一第二晶片，其係疊設於該第一晶片之上方。 在前述的打線連接型半導體封裝構造中，該第二晶 片係可設置於該線支撐攔壩上。 在前述的打線連接型半導體封裝構造中，該第二晶 片之尺寸係可大於該第一晶片。 在前述的打線連接型半導體封裝構造中，該第一晶 片與該第二晶片之間係可另形成有一液態黏膠。 在前述的打線連接型半導體封裝構造中，該些銲線 1345823 - &線’每一銲線係具有一連接於對應連接指 之結球端與一連接於對應銲墊之尾端。 依據本發明揭示另一種打線連接型半導體封裝構 ^主要包含—基板、一黏膠、一晶片、複數個銲線以 及一線支撐攔壤。該基板係具有一黏晶區以及複數個在 該黏晶區之外的連接指。該黏膠係形成於該黏晶區。該 明片係藉由該黏膠設置於該基板之該黏晶區並具有複 數個銲墊。該些銲線係電性連接該些銲墊與該些連接 指。該線支撐攔壩係設置於該基板上且在該黏晶區與該 些連接指之間。其特徵在於，該些銲線係為逆打銲線且 該線支撐攔壩係具有一不低於該第一晶片之高度，每一 銲線係具有一連接於對應連接指之結球端與一連接於 對應銲墊之尾端，該些銲線係接觸至該線支撐攔壩以修 正其銲線形狀，以致使該些銲線之最大弧高處係遠離該 第一晶片並概略相等於該線支撐攔壩之高度。 【實施方式】 依據本發明之第一具體實施例，揭示一種打線連接 塑半導體封裝構造《第3圖係為該打線連接型半導體封 裝構之截面示意圓。第4圖係為該打線連接型半導體封 裝構造透視封膠體之局部俯視圖。 請參閱第3圖所示，一種打線連接型半導體封裝構 造300主要包含一基板3 1〇、一液態黏膠32〇、一晶片 330、複數個銲線340以及一線支撐攔壩350«該基板 3 1 〇係具有一尺寸對應於該晶片3 3 〇之黏晶區（圖中未 1345823 繪出）以及複數個在該黏晶區之外的連接指313»該基板 係具有一上表面311以及一下表面312。通常該基板係 為具有雙面導通線路之印刷電路板。該液態黏膠320係 形成於該黏晶區。該液態黏膠320係可為一般習知的環 氧樹脂。 通常該晶片330係為一種具有積體電路的半導鱧基 板，該晶片330係可具有一主動面33 1、一背面332以 及複數個在該主動面 3 3 1與該背面 3 3 2之間之側面 334。該晶片330並具有複數個銲墊333，可形成於該 主動面331並作為積體電路之外連接電極《更具體而 言，該些銲墊333係可排列鄰近於該晶片330之該主動 面331之邊緣。例如，該些銲墊333至該主動面331之 間距係可小於該線支撐攔壩350之寬度（如第 4圖所 示）。 能藉由該液態黏膠320黏接該晶片330之背面332, 使該晶片3 3 0設置於該基板3 1 0之該黏晶區。在本實施 例中，該液態黏膠320係除了黏接該晶片330之背面 332並沿著該線支撐攔壩350黏接至該晶片33〇之至少 一側面3 3 4，以增加黏晶強度。 利用打線技術，該些銲線340係電性連接該些銲墊 333與該些連接指313。再參閱第3圖，該些銲線3 40 係可為逆打銲線340’每一銲線340係具有一連接於對 應連接指313之結球端341與一連接於對應薛整333之 尾端342 » 12 1345823 此外，該線支撐攔壩350係設置於該基板310上且 在該黏晶區與該些連接指3 1 3之間，並且該液態黏膠 320係黏接該晶片330、該基板310與該線支撐攔壩 35〇。該線支撐攔壩350係可選自於介電膠材（dielectric resin)、再塗施防銲層（recoated solder mask)與被覆有電 絕緣層之金屬物（metal bar coated with electrically insulating layer)之其中之一，以提供電絕緣性支撐銲線 | 之功效。在具體結構中，該線支撐搁壩3 50係可利用習 知黏晶膠帶的廢料部位多層疊合之後再裁切而成。較佳 地’該線支撐攔壩350係可具有一高度H1，其係不低 於該晶片高度H2，故該些銲線3 40係可跨過該線支撐 攔壩350並可壓觸至該線支撐攔壩350，不會使該些銲 線340壓觸該晶片33〇之邊緣而導致短路或訊號干擾。 因此’在上述之打線連接型半導體封裝構造300 中’利用該線支撐攔壩35〇與該液態黏膠32〇運用在打 ® 線連接型半導體封裝的組合關係，能將低成本的黏晶材 料運用在微型基板尺寸的封裝產品，該基板31〇之連接 指313可更加靠近於該晶片330而不會被該液態黏膠 320擴散污染。此外，可以增加黏晶強度與提供該些銲 線3 40良好支撐性，避免該些銲線mo因模流壓力或其 它外力而碰觸該晶片330之邊緣導致短路。 此外’如第3圖之局部放大圖所示，較佳地，該液 態黏膠320係可具有一溢出高度H3(fillet height)，其 係高於該晶片3 3 0之該背面3 3 2但低於該晶片3 3 0之該 13 1345823 主動面331。即該液態黏膠320之溢出高度H3係不超 過該晶片330之晶片高度H2，不會溢流到該晶片330 之該主動面331，故不會影響該些銲線340之線尾端342 與對應銲墊333之接合強度。在本實施例中，該線支撐 攔壩3 5 0與該晶片3 3 0之相鄰側面3 3 4之間隙係可約相 等於該晶片3 3 0之背面3 3 2與該基板3 1 0之間隙，以利 該液態黏膠320作上升方向之溢膠流動。 該打線連接型半導逋封裝構造300可另包含有一封 膠體360，其係密封該晶片330、該些銲線340與該線 支撐攔壩350，以形成卡片型態或是塊狀。通常，該封 穆體360係為環氧模封化合物（EpOXy Molding Compound, EMC) ’ 以轉移成形（transfer mold)技術製成 於該基板3 10上。 此外’本發明之另一明顯功效係能適用於薄型封裝 產品、堆疊更多晶片或是堆疊更大尺寸的晶片，其特徵 在於該線支撐攔壩350與該些銲線340的組合關係。如 第3圖所示，該些銲線34〇由該線支撐攔壩35〇至對應 連接之銲塾333之間的線段概呈水平，令該些銲線340 之最大狐而處係遠離該晶片330並概略相等於該線支 稽棚壩350之高度，以達到低成本薄型設計而不會影響 打線品質，更可適用於多晶片堆疊。 在本發明之第二具體實施例’揭示另一種打線連接 ^半導體封裝構造。请參閱第5圖所示，該打線連接型 半導體封裝構造400主要包含一基板41〇、液態黏膠421 1345823' 與422、一第一晶片430、複數個第一銲線441以及一 線支撐攔壩450。 該基板410係具有一上表面411與一相對之下表面 412。在該上表面411上，該基板410係具有一對應於 該第一晶片430尺寸之黏晶區（圖未繪出）以及複數個在 該黏晶區之外的連接指4 1 3。該液態黏膠4 2 1則形成於 該黏晶區。 該第一晶片430係可具有一主動面431、一背面432 以及複數個在該主動面43 1與該背面432之間之側面 434。該第一晶片430係藉由該液態黏膠421將其背面 432設置於該基板410之該黏晶區並具有複數個第一銲 墊433。該些第一銲墊433係可排列於該主動面431之 周邊。並利用該些第一銲線441電性連接該些第一銲墊 43 3與該些連接指413。 該線支撐攔壩450係設置於該基板410上且在該黏 晶區與該些連接指4 1 3之間，並且該液態黏膠42 1係黏 接該第一晶片430、該基板410與該線支撐攔壩450。 因此’該些第一銲線441將跨過該線支撐攔壩450，配 合該線支撐攔壩450係具有一不低於該第一晶片430之 主動面43 1之高度，故能使該線支撐攔壩4 50能發揮支 標銲線的功能，以避免該些第一銲線44 1壓觸該第一晶 片4 3 0之邊緣。 該打線連接型半導髋封裝構造4 00可另包含有一封 膠趙460，其係至少密封該第一晶片430、該些第一銲 15 1345823' 線441與該線支撐攔壩450。當該些第一銲線441 該線支撐攔壩450，部份之該些第一銲線441係可 至該線支撑攔塌450，以維持銲線弧高的最小限定 不會受到形成該封膠體460的模流壓力引發該些 銲線441的下沉或左右位移。 較佳地，該液態黏膠42 1係可黏接該第一晶片 之背面432並沿著該線支撐攔壩450黏接至該第— 430之至少一側面434，但較低於該第一晶片43〇 主動面431。藉此，提供一低成本解決方案來增進 強度並符合基板微小化之要求。 此外，在本實施例中，該打線連接型半導體封 造400可另包含至少一第二晶片470，其係疊設於 一晶片430之上方。該第二晶片47〇係具有複數個 銲墊471，可利用複數個打線形成之第二銲線442 連接該些第二銲墊471與該些連接指413。較佳地 第二晶片470係可設置於該線支撐攔壩450上，故 二晶片470之尺寸係可大於該第一晶片430。再者 該第一晶片430與該第二晶片470之間係可另形成 液態黏膠422 ’以低成本黏接該第二晶片470並具 佳的膠填充特性β 以上所述’僅是本發明的較佳實施例而已，並 本發明作任何形式上的限制，雖然本發明已以較佳 例揭露如上，然而並非用以限定本發明，任何熟悉 業的技術人員，在不脫離本發明技術方案範圍内， 跨過 壓觸 值， 第— 430 晶片 之該 黏晶 裝構 該第 第二 電性 ，該 該第 ，在 有一 有較 非對 實施 本專 當可 16 1345823 利用上述揭示的技術内谷作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：一種習知打線連接型半導體封裝構造之截面示 ▲ 意圖。1345823* IX. Description of the Invention: [Technical Field] The present invention relates to a wire bonding type semiconductor package structure, and more particularly to a wire bonding type semiconductor capable of preventing wire bonding short-circuiting and bonding strength at low cost. Package construction. [Prior Art] The evolution of semiconductor package construction continues to be trend toward lightness and thinness. The improvement of packaging technology is expected to make smaller semiconductor package structures using existing packaging equipment, but there are still limits. Once low-cost packages are available. Components such as wire bonds or liquid adhesives cannot be used in the next-generation semiconductor package specifications. New package components must be used to flip-chip bumps or die-bonding tapes, etc., and even replacement of semiconductor packaging equipment will result in significant packaging costs. improve. Referring to FIG. 1 , an early conventional wire bonding type semiconductor package structure 100 includes a substrate 11 , a liquid adhesive 12 , a 0 day > ! 130 , a plurality of bonding wires 14 , and a The substrate 110 has an upper surface U1, a lower surface, and a plurality of connecting fingers H3 disposed on the upper surface U1. The liquid adhesive 12 is adhered to the back surface 132 of the wafer 130 so as to be disposed on the upper surface 11 of the substrate. However, in the case of die bonding, the liquid adhesive 2 2 has a problem of external expansion and contamination of the connecting fingers 113. Therefore, the substrate 110 is designed to have an edge of the wafer 130 to the connecting fingers 113 having a width of 5 〇〇 to 60 〇 μm to prevent the liquid adhesive 12 from expanding to contaminate the connecting finger (1). Electrically interconnecting the wafer 130 and the substrate 110 by electrically connecting the plurality of solder pads 133 and the plurality of solder pads 133 to the substrate 110. The pads 133 are disposed on one of the active faces 131 of the wafer 130. The encapsulant 150 seals the wafer 130 and the bonding wires 140. However, the use of liquid glue 120 such as epoxy liquid glue for die bonding has the advantage of low cost, but the problem of overflowing is serious, and the distance between the connecting fingers 113 and the wafer 130 must be increased, so the substrate 11 does not conform to Miniaturized requirements. Moreover, it is known that the bonding wires 140 are positive bonding wires, and the maximum arc height of the bonding wires is adjacent to or located at the edge of the wafer 130 to prevent the bonding wires 140 from accidentally touching the edge of the wafer 130. The overall package thickness of the semiconductor package construction 100 is difficult to further reduce. If it is attempted to directly change the positive bonding wire to a reverse bond (reverse bond), although the arc height of the bonding wires 140 can be lowered, the molding pressure is extremely likely to cause the fresh wires 140 to accidentally touch the wafer 130. Edge, causing electrical short circuit or leakage current. Referring to FIG. 2 , another conventional wire bonding type semiconductor package structure 200 includes a substrate 210 , a die bonding tape 220 , a wafer 230 , a plurality of bonding wires 240 , and a glue body 250 . There is an upper surface 211, a lower surface 212 and a plurality of connecting fingers 213, wherein the connecting fingers 213 are disposed on the upper surface 2U. The wafer 230 is adhered by the adhesive tape 22 such that the back surface 232 of the wafer 230 can be disposed on the upper surface 211 of the substrate 210. Since the adhesive tape 220 does not have the problem of overflowing the adhesive, the substrate 210 does not need to reserve a width to reduce the use area of the substrate 210. The bonding wires 240 are electrically connected to the plurality of solders of the wafer 230. The pad 233 and the 7 1345823 'connecting fingers 213 ' are disposed on the active surface 231 of the wafer 23 . The encapsulant 250 seals the wafer 23 and the wires 240. However, the cost and waste of the diaphragm-shaped adhesive wafer 220 is far from the liquid adhesive, which leads to an increase in packaging cost. The above-mentioned wire-connected semiconductor package structure 200 can only solve the problem of overflowing and shrinking the substrate, and cannot be reduced. Overall package thickness. SUMMARY OF THE INVENTION The main object of the present invention is to provide a wire-bonding type semi-Zhao package structure, which limits the diffusion and dyeing of liquid glue by using a combination of a line support dam and a liquid glue in a connection type semiconductor package. The connection fingers of the substrate can be closer to the wafer, and the micro-design can be low-cost without affecting the quality of the wire bonding, and the bonding strength and the bonding wire can be added to prevent the bonding wires from being touched by the mold flow pressure or other external force. The edge of the chip causes a short circuit. A second object of the present invention is to provide a wire-bonding type semi-body package structure, which utilizes a combination of a one-line support dam and a plurality of bonding wires using a wire-connected semi-conductive semiconductor package to maximize the thickness of the bonding wires. It is far away from the wafer and is roughly equal to the height of the line branch. It is low-cost and thin design without affecting the quality of the wire, and is suitable for multi-chip stacking. Another object of the present invention is to provide a wire bonding type semiconductor package structure, which can effectively reduce the substrate use area and thereby reduce the cost, can reduce the thickness of the overall package structure, and contribute to the size reduction of the semiconductor package structure. The welding system is connected to the wire and the wire is guided by the crystal. 8 Γ 345823* The object of the present invention and solving the technical problem are achieved by the following technical solutions. According to the present invention, a wire bonding type semi-conductive package structure mainly comprises a substrate, a liquid adhesive, a first wafer, a plurality of bonding wires, and a wire branch. The substrate has a die bonding region and a plurality of connecting fingers outside the die bonding region. The liquid adhesive is formed in the die bond region. The first wafer is disposed on the die bond region of the substrate by the liquid adhesive and has a plurality of solder moldings. The bonding wires are electrically connected to the pads and the quick fingers. The wire support dam is disposed on the substrate and between the die bond region and the connecting fingers, and the liquid adhesive adheres to the first wafer, and the substrate and the wire support shed are broken. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the above-described wire-bonding type semi-conductive package structure, the line support picking system may have a height not lower than the height of the first wafer to prevent the slow pressure from contacting the edge of the first wafer. In the wire bonding type semiconductor package construction described above, the bonding wires may support the dam across the wire and may press the wire to support the dam. In the above-described wire-bonding type semi-conductive package structure, the wire support splicing system may be selected from the group consisting of a dielectric rubber material, a recoating solder resist layer, and a metal material coated with an electric insulating layer and a margin layer. In the above-described wire bonding type semiconductor package structure, the first wafer system may have an active surface, a back surface, and a plurality of sides between the active surface and the back surface. In the above-described wire bonding type semiconductor package structure, the liquid adhesive 9 1345823. can be bonded to the back surface of the first wafer and connected to at least one side of the first wafer along the line I. In the wire bonding type semiconductor package structure described above, the liquid adhesive may have a fillet height which is higher than the first side but lower than the active surface of the first wafer. In the above-described wire bonding type semiconductor package structure, the line support may block the gap between the adjacent sides of the wafer 1 and the wafer to be approximately equal to the gap between the back surface of the first wafer and the substrate. In the wire bonding type semiconductor package structure described above, the pads may be arranged adjacent to the edge of the active surface of the first wafer. In the wire bonding type semiconductor package structure of the I, the freshening to the active surface may be smaller than the width of the wire supporting dam. In the above-mentioned wire-bonding type semiconductor package structure, a gel may be further included, which seals the first wafer and the wire support dams in the wire-bonding type semiconductor package structure. The method includes at least one second wafer stacked on top of the first wafer. In the above-described wire bonding type semiconductor package structure, the second wafer system may be disposed on the wire supporting dam. In the above-described wire bonding type semiconductor package structure, the second wafer may be larger in size than the first wafer. In the above-described wire bonding type semiconductor package structure, a liquid adhesive may be additionally formed between the first wafer and the second wafer. In the above-described wire bonding type semiconductor package structure, each of the bonding wires 1345823 - & wire has a ball end connected to the corresponding connecting finger and a tail end connected to the corresponding pad. According to the present invention, another wire bonding type semiconductor package structure mainly comprises a substrate, a glue, a wafer, a plurality of bonding wires, and a wire supporting barrier. The substrate has a die bonding region and a plurality of connecting fingers outside the die bonding region. The adhesive is formed in the die bond region. The stencil is disposed on the die bond region of the substrate by the adhesive and has a plurality of pads. The bonding wires are electrically connected to the pads and the connecting fingers. The wire support dam is disposed on the substrate and between the die bond region and the connecting fingers. The wire bonding wire is a reverse bonding wire and the wire supporting dam has a height not lower than the height of the first wafer, and each wire has a ball end connected to the corresponding connecting finger and one Connected to the tail end of the corresponding solder pad, the solder wire contacts the wire support dam to correct the shape of the wire, such that the maximum arc height of the wire is away from the first wafer and is substantially equal to The line supports the height of the dam. [Embodiment] According to a first embodiment of the present invention, a wire bonding plastic semiconductor package structure is disclosed. Fig. 3 is a schematic cross-sectional circle of the wire bonding type semiconductor package. Fig. 4 is a partial plan view showing the see-through sealing body of the wire bonding type semiconductor package structure. Referring to FIG. 3 , a wire bonding type semiconductor package structure 300 mainly includes a substrate 3 1 , a liquid adhesive 32 , a wafer 330 , a plurality of bonding wires 340 , and a wire supporting dam 350 « the substrate 3 The lanthanide has a die-bonding region corresponding to the surface of the wafer (not depicted in the figure 1345582) and a plurality of connecting fingers 313 outside the die-bonding region. The substrate has an upper surface 311 and a lower layer. Surface 312. Typically the substrate is a printed circuit board having double-sided conductive lines. The liquid adhesive 320 is formed in the die bond region. The liquid adhesive 320 can be a conventionally known epoxy resin. The wafer 330 is generally a semi-conducting substrate having an integrated circuit. The wafer 330 can have an active surface 33 1 , a back surface 332 , and a plurality of between the active surface 33 1 and the back surface 3 3 2 . Side 334. The wafer 330 has a plurality of pads 333 formed on the active surface 331 and connected as electrodes outside the integrated circuit. More specifically, the pads 333 are arranged adjacent to the active surface of the wafer 330. The edge of 331. For example, the spacing of the pads 333 to the active surface 331 can be less than the width of the wire support dam 350 (as shown in Figure 4). The liquid crystal 320 can be adhered to the back surface 332 of the wafer 330 to place the wafer 3000 in the die bond region of the substrate 310. In this embodiment, the liquid adhesive 320 is adhered to the back surface 332 of the wafer 330 and adhered to the at least one side 3 3 4 of the wafer 33 along the line supporting dam 350 to increase the bonding strength. . The bonding wires 340 are electrically connected to the bonding pads 333 and the connecting fingers 313 by using a wire bonding technique. Referring to FIG. 3 again, the bonding wires 3 40 may be reverse bonding wires 340 ′ each of the bonding wires 340 has a ball end 341 connected to the corresponding connecting finger 313 and a tail end connected to the corresponding Xue 333. 342 » 12 1345823 In addition, the wire support dam 350 is disposed on the substrate 310 between the die bond region and the connecting fingers 3 1 3 , and the liquid adhesive 320 is bonded to the wafer 330 , The substrate 310 and the line support the dam 35 〇. The wire support dam 350 can be selected from the group consisting of a dielectric resin, a recoated solder mask, and a metal bar coated with an electrically insulating layer. One of them to provide electrical insulation to support the wire | In a specific structure, the wire support dam 3 50 series can be formed by laminating the scrap portions of the conventional scotch tape. Preferably, the line support dam 350 can have a height H1 that is not lower than the height H2 of the wafer, so that the wire 340 can support the dam 350 across the line and can be pressed to the The wire supports the dam 350 so that the wire 340 does not press against the edge of the wafer 33, causing a short circuit or signal interference. Therefore, in the above-described wire-bonding type semiconductor package structure 300, the combination of the wire supporting dam 35 〇 and the liquid adhesive 32 〇 in the wire-connected semiconductor package enables a low-cost die-bonding material. With a packaged product of a micro-substrate size, the connection fingers 313 of the substrate 31 can be closer to the wafer 330 without being contaminated by the liquid adhesive 320. In addition, it is possible to increase the bond strength and provide good support for the wires 340 to prevent the wire mo from contacting the edge of the wafer 330 due to the mold flow pressure or other external force to cause a short circuit. In addition, as shown in a partially enlarged view of FIG. 3, preferably, the liquid adhesive 320 may have a fillet height H3 which is higher than the back surface of the wafer 3 3 0 but The 13 1345823 active surface 331 is lower than the wafer 330. That is, the overflow height H3 of the liquid adhesive 320 does not exceed the wafer height H2 of the wafer 330, and does not overflow to the active surface 331 of the wafer 330, so that the wire tail end 342 of the bonding wires 340 is not affected. Corresponding to the bonding strength of the pad 333. In this embodiment, the gap between the line supporting dam 350 and the adjacent side surface 343 of the wafer 303 may be approximately equal to the back surface of the wafer 303 and the substrate 3 1 0 The gap is used to facilitate the flow of the liquid glue 320 in the ascending direction. The wire bonding type semi-conductive package structure 300 may further include a glue 360 that seals the wafer 330, the bonding wires 340 and the wire supporting dam 350 to form a card type or a block shape. Usually, the sealing body 360 is an epoxy molding compound (EpOXy Molding Compound, EMC), which is formed on the substrate 3 10 by a transfer molding technique. Further, another significant effect of the present invention can be applied to thin package products, stacking more wafers, or stacking larger sized wafers, characterized by the combination of the wire support dam 350 and the bond wires 340. As shown in FIG. 3, the wire lines 34 are horizontally supported by the line between the wire dam 35 and the correspondingly connected wire 333, so that the largest fox of the wire 340 is away from the wire. The wafer 330 is roughly equal to the height of the wire dam 350 to achieve a low cost and thin design without affecting the quality of the wire, and is more suitable for multi-wafer stacking. Another second embodiment of the present invention discloses another wire bonding structure. Referring to FIG. 5, the wire bonding type semiconductor package structure 400 mainly includes a substrate 41A, liquid adhesives 421 1345823' and 422, a first wafer 430, a plurality of first bonding wires 441, and a line support dam. 450. The substrate 410 has an upper surface 411 and an opposite lower surface 412. On the upper surface 411, the substrate 410 has a die bond region (not shown) corresponding to the size of the first wafer 430 and a plurality of connection fingers 4 1 3 outside the die bond region. The liquid adhesive 4 2 1 is formed in the die bond region. The first wafer 430 can have an active surface 431, a back surface 432, and a plurality of sides 434 between the active surface 43 1 and the back surface 432. The first wafer 430 is disposed on the back surface 432 of the substrate 410 by the liquid adhesive 421 and has a plurality of first pads 433. The first pads 433 are arranged on the periphery of the active surface 431. The first bonding pads 43 3 and the connecting fingers 413 are electrically connected by using the first bonding wires 441. The wire support dam 450 is disposed on the substrate 410 between the die bond region and the connecting fingers 4 1 3 , and the liquid adhesive 42 1 is bonded to the first wafer 430 and the substrate 410 This line supports the dam 450. Therefore, the first bonding wires 441 will support the dam 450 across the wire, and the wire supporting dam 450 has a height not lower than the active surface 43 1 of the first wafer 430, so that the wire can be The support dam 450 can function as a support wire to prevent the first wire 44 1 from pressing against the edge of the first wafer 430. The wire-bonding type semi-guided hip package structure 400 may further include a glue 460 which seals at least the first wafer 430, the first weld 15 1345823' line 441 and the wire support dam 450. When the first bonding wires 441 support the dam 450, a portion of the first bonding wires 441 can support the collapse 450 to the wire to maintain the minimum definition of the arc height of the bonding wire without being formed. The mold flow pressure of the colloid 460 causes the sinking or left and right displacement of the bonding wires 441. Preferably, the liquid adhesive 42 1 is adhered to the back surface 432 of the first wafer and adhered along the line supporting dam 450 to at least one side 434 of the first 430, but lower than the first The wafer 43 has an active surface 431. In this way, a low-cost solution is provided to increase the strength and meet the requirements for miniaturization of the substrate. In addition, in the embodiment, the wire bonding type semiconductor package 400 may further include at least one second wafer 470 stacked on top of a wafer 430. The second wafer 47 has a plurality of pads 471, and the second pads 442 formed by a plurality of wires are connected to the second pads 471 and the connecting fingers 413. Preferably, the second wafer 470 can be disposed on the wire support dam 450, so the size of the second wafer 470 can be larger than the first wafer 430. Furthermore, a liquid adhesive 422 ′ can be additionally formed between the first wafer 430 and the second wafer 470 to bond the second wafer 470 at a low cost and has a good glue filling property β. The above is only the present invention. The preferred embodiment of the present invention is not limited to the technical solution of the present invention. However, the present invention has been described above by way of a preferred example, and is not intended to limit the present invention. Within the range, across the pressure-contact value, the 430-wafer of the die-bonding device is configured to have the second electrical property, and the first, in the case of a non-practical implementation, may be used. Any equivalent modifications, equivalent changes, and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still present in the present invention without departing from the scope of the present invention. Within the scope of the inventive solution. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional wire-bonding type semiconductor package structure.
W 第2圖：另一種習知打線連接型半導體封裝構造之截面 示意圖。 第3圖：依據本發明之第一具體實施例，一種打線連接 型半導體封裝構造之截面示意圖。 第4圖：依據本發明之第一具體實施例，該打線連接型 半導體封裝構造透視封膠體之局部俯視圖。 第5圖：依據本發明之第二具體實施例，另一種打線連 • 接型半導體封裝構造之截面示意圖。 【主要元件符號說明】 100打線連接型半導體封裝構造 110 基板 111 上表面 112 下表面 113 連接指 120 液態黏膠 130 晶片 131 主動面 132 背面 133 銲墊 140 銲線 150 封膠體 200 打線連接型半導趙封裝構造 210 基板 211 上表面 212 下表面 17 1345823W Fig. 2 is a schematic cross-sectional view showing another conventional wire-bonding type semiconductor package structure. Figure 3 is a cross-sectional view showing a wire bonding type semiconductor package structure in accordance with a first embodiment of the present invention. Figure 4 is a partial plan view of the wire bonding type semiconductor package structure see-through sealant in accordance with a first embodiment of the present invention. Figure 5 is a cross-sectional view showing another wire-bonding type semiconductor package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 100-wire connection type semiconductor package structure 110 substrate 111 upper surface 112 lower surface 113 connection finger 120 liquid adhesive 130 wafer 131 active surface 132 back surface 133 solder pad 140 bonding wire 150 sealing body 200 wire-bonding type semi-conductive Zhao package structure 210 substrate 211 upper surface 212 lower surface 17 1345823
213 連接指 2 2 0點晶膠帶 230 晶片 231主動面 232 背面 233 銲墊 240銲線 250 封膠體 300 打線連接型半導體封裝構造 310 基板 311上表面 312 下表面 313 連接指 320液態黏膠 330 晶片 331主動面 332 背面 333 銲墊 3 3 4側面 340 銲線 341結球端 342 結尾端 350 線支撐攔壩 360封膠體 400 打線連接型 半導體封裝構造 410 基板 411上表面 413 連接指 421 液態黏膠 422液態黏膠 430 第一晶片 431主動面 432 背面 433 第一銲墊 4 3 4側面 441 第一銲線 442第二銲線 450 線支撐攔塌 460封膠體 470 第二晶片 471第二銲墊 HI 線支撐攔壩高度 H2 晶片高 H3 溢出高度 18213 connection finger 2 2 0 crystal bonding tape 230 wafer 231 active surface 232 back 233 solder pad 240 bonding wire 250 sealing body 300 wire bonding type semiconductor package structure 310 substrate 311 upper surface 312 lower surface 313 connection finger 320 liquid adhesive 330 wafer 331 Active surface 332 Back surface 333 Solder pad 3 3 4 Side 340 Bond wire 341 Ball end 342 End end 350 Line support dam 360 Sealing body 400 Wire-bonding type semiconductor package structure 410 Substrate 411 Upper surface 413 Connection finger 421 Liquid adhesive 422 liquid viscosity Glue 430 First wafer 431 active surface 432 Back surface 433 First pad 4 3 4 Side 441 First bonding wire 442 Second bonding wire 450 Wire support collapse 460 Sealant 470 Second wafer 471 Second pad HI wire support bar Dam height H2 wafer height H3 overflow height 18