TWI425581B - 用於凹陷的半導體基底的技術和配置 - Google Patents

用於凹陷的半導體基底的技術和配置 Download PDF

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Publication number
TWI425581B
TWI425581B TW100103443A TW100103443A TWI425581B TW I425581 B TWI425581 B TW I425581B TW 100103443 A TW100103443 A TW 100103443A TW 100103443 A TW100103443 A TW 100103443A TW I425581 B TWI425581 B TW I425581B
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Taiwan
Prior art keywords
semiconductor substrate
dies
channels
recessed
structures
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TW100103443A
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English (en)
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TW201140713A (en
Inventor
Albert Wu
Roawen Chen
Chung-Chyung Han
Shiann-Ming Liou
Chien-Chuan Wei
Runzi Chang
Scott Wu
Chuan-Cheng Cheng
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Marvell World Trade Ltd
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Publication of TW201140713A publication Critical patent/TW201140713A/zh
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    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

用於凹陷的半導體基底的技術和配置
本公開的實施方式涉及積體電路領域，並且更特別地涉及用於封裝元件的凹陷(recessed)半導體基底的技術、結構以及配置。
在此出於一般地呈現本公開的上下文的目的而提供了背景技術描述。在該背景技術部分中所描述的當前署名的發明人的工作以及本說明書中的並未以其他方式被判定為申請日時的現有技術的各方面，均不表示明確地或隱含地被承認為相對於本公開的現有技術。
諸如電晶體的積體電路器件形成在其大小持續縮減為更小尺寸的裸片或晶片上。裸片的緊縮尺寸對當前用於路由去往或來自半導體裸片的電信號的傳統基底製作和/或封裝組件技術提出了挑戰。例如，層壓基底技術不能在基底上產生足夠小的特徵以對應于互連的更細微的節距，或者形成在裸片上的其他路由信號的特徵。
在一個實施方式中，本公開提供了一種方法，包括：提供半導體基底，該半導體基底具有(i)第一表面和(ii)與第一表面相反地佈置的第二表面；在半導體基底的第一表面上形成電介質膜；在電介質膜上形成再分佈層；將一個或多個裸片電耦合到再分佈層；在半導體基底上形成模塑膠(molding compound)；使半導體基底的第二表面凹陷；形成通過半導體基底的凹陷的第二表面的一個或多個溝道以暴露再分佈層；以及在該一個或多個溝道中形成一個或多個封裝互連結構，該一個或多個封裝互連結構電耦合到再分佈層，該一個或多個封裝互連結構用以路由該一個或多個裸片的電信號。
在另一實施方式中，本公開提供了一種裝置，包括：半導體基底，該半導體基底具有(i)第一表面和(ii)與第一表面相反地佈置的第二表面；形成在半導體基底的第一表面上的電介質膜；形成在電介質膜上的再分佈層；電耦合到再分佈層的一個或多個裸片；形成在半導體基底上的模塑膠；形成為通過半導體基底的第二表面的一個或多個溝道；以及佈置在該一個或多個溝道中的一個或多個封裝互連結構，該一個或多個封裝互連結構通過該一個或多個溝道電耦合到再分佈層以路由該一個或多個裸片的電信號。
本公開要求以下專利申請的優先權：2010年2月3日提交的美國臨時專利申請No. 61/301,125、2010年3月22日提交的美國臨時專利申請No. 61/316,282、2010年4月5日提交的美國臨時專利申請No. 61/321,068以及2010年4月16日提交的美國臨時專利申請No. 61/325,189，就各方面而言，在此通過引用的方式引入這些申請整個說明書的全部內容，除了可能存在的與本說明書不一致的那些部分。
本公開的實施方式描述了用於具有凹陷區域和相關聯的封裝元件的半導體基底的技術、結構以及配置。在以下詳細描述中，參考了作為其一部分的附圖，其中貫穿附圖，類似的參考標號表示類似的部分。在不脫離本公開範圍的情況下，可以利用其他實施方式，並且可以在結構上和邏輯上進行改變。因此，以下詳細描述不應理解為限制性的，並且實施方式的範圍由所附請求項書及其等同形式限定。
本說明書可以使用基於透視的描述，諸如上/下、之上/之下，和/或頂部/底部。這種描述僅用於便於討論，而並非旨在將在此描述的實施方式的應用限制為任何特定方向。
出於本公開的目的，短語“A/B”意思是A或B。出於本公開的目的，短語“A和/或B”意思是“(A)、(B)或者(A和B)”。出於本公開的目的，短語“A、B以及C中的至少一個”意思是“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)、或者(A、B以及C)”。出於本公開的目的，短語“(A)B”意思是“(B)或(AB)”，也即，A是可選元素。
各種操作以最有助於理解所要求保護的主題的方式被描述為按次序的多個離散操作。然而，描述的順序不應當理解為暗示這些操作必然是依賴於順序的。特別地，這些操作可以不以所呈現的順序執行。所描述的操作可以以與所描述的實施方式不同的順序來執行。可以執行各種附加的操作和/或所描述的操作在附加實施方式中可以省略。
本說明書使用短語“在一個實施方式中”、“在實施方式中”或者類似的語言，其均可以指代一個或多個相同或不同的實施方式。另外，針對本公開的實施方式而使用的術語“包括”、“包含”、“具有”等是同義的。
圖1示意性地示出包括凹陷的半導體基底的封裝元件100。封裝元件100一般地包括半導體基底102，該半導體基底102是基底或插入物，其實質上包括半導體材料，諸如矽(Si)。也即，半導體基底102的主要材料是半導體材料。半導體材料可以包括晶體和/或非晶類型的材料。在矽的情況下，例如，矽可以包括單晶體和/或多晶矽類型。在其他實施方式中，半導體基底102可以包括其他半導體材料，諸如鍺、III-V族材料或者II-VI族材料，其也可以從在此描述的原理受益。
半導體基底102包括第一表面A1和與第一表面A1相反地佈置的第二表面A2。第一表面A1和第二表面A2通常指代半導體基底102的相反表面，以便於描述在此描述的各種配置。
根據各種實施方式，第二表面A2的一部分是凹陷的，以提供厚度T，該厚度T便於通過半導體基底102而形成一個或者多個溝道104。在某些實施方式中，半導體基底102是凹陷的，以具有在大約10微米與500微米之間的厚度T。該厚度不限於這一範圍，在其他實施方式中可以使用其他更大或者更小的兩種厚度。
半導體基底102是使用與一般已知的用以在裸片或晶片上製作積體電路(IC)結構的那些技術類似的技術來製作的。例如，公知的用於在裸片上製作IC器件的圖案化工藝，諸如光刻/蝕刻和/或沉積工藝，可以用於形成半導體基底102的特徵。通過使用半導體製作技術，半導體基底102可以包括比諸如層壓(例如有機)基底之類的其他類型的基底更小的特徵。半導體基底102實現了對用於大小持續縮減的裸片的電信號，諸如輸入/輸出(I/O)和/或電源/接地信號的路由。例如，在某些實施方式中，半導體基底102允許在半導體基底102與一個或多個裸片108之間進行路由的最終線路和細微節距Si到Si互連。
電介質膜105形成在半導體基底的第一表面A1和/或第二表面A2上。電介質膜105可以包括例如二氧化矽(SiO2 )、氮化矽(SiN)或者氮氧化矽(Si2 N2 O)，或者其他合適的電介質材料。電介質膜105一般地提供針對佈置在半導體基底上的導電材料的電隔離，以防止半導體基底的半導體材料(例如，矽)與導電材料之間的電流洩漏。
一個或多個再分佈層106形成在電介質膜105上，以路由一個或多個裸片108的電信號，該裸片108耦合到半導體基底102。例如一個或多個再分佈層106可以提供一個或多個裸片108與佈置在一個或多個溝道104中的一個或多個封裝互連結構114之間的電路由。
一個或多個再分佈層106一般地包括導電材料，諸如金屬(例如，銅或鋁)。在其他實施方式中，可以使用其他合適的導電材料來形成一個或多個再分佈層106。
一個或多個再分佈層106可以包括用以路由電信號的各種各樣的結構，諸如焊盤、焊區或者跡線。儘管未示出，但可以將包括諸如聚醯亞胺之類的電絕緣材料的鈍化層沉積在一個或多個再分佈層106上，並且圖案化為在鈍化層中提供開口以允許一個或多個裸片108到一個或多個再分佈層106的電耦合。
一個或多個裸片108耦合到半導體基底102。一個或多個裸片108一般地包括半導體材料，諸如矽。在一個實施方式中，一個或多個裸片108和半導體基底102是使用相同的半導體材料來製作的，以減少與材料的加熱/冷卻失配(諸如失配的熱膨脹係數(CTE))相關聯的應力。
一個或多個裸片108可以使用任何合適的配置耦合到半導體基底102。一個或多個裸片108一般地具有活性側和非活性側，活性側包括如下表面，在該表面上形成了用於邏輯和/或記憶體的多個積體電路(IC)器件(未示出)，諸如電晶體，並且非活性側與活性側相反地佈置。一個或多個裸片108的活性側電耦合到一個或多個再分佈層106。
在某些實施方式中，一個或多個裸片108的活性側使用一個或多個凸點110，以倒裝晶片配置耦合到一個或多個再分佈層106，正如可以看到的那樣。在其他實施方式中，一個或多個裸片108的活性側使用其他結構，諸如一個或多個鍵合引線來電耦合到一個或多個再分佈層106以提供引線鍵合配置。
一個或多個凸點110一般地包括導電材料，諸如焊料或其他金屬，以路由一個或多個裸片108的電信號。根據各種實施方式，一個或多個凸點110包括鉛、金、錫、銅或無鉛材料或者其組合。一個或多個凸點110可以具有各種各樣的形狀(包括球形、圓柱形、矩形或其他形狀)，並且能夠使用凸點工藝(諸如可控坍塌晶片連接(C4)工藝、柱形凸點成形(stud-bumping)或者其他合適的工藝)來形成。
儘管未示出，但可以在半導體基底102上安裝一個或多個其他有源或無源部件。這些部件可以包括電子複合體和積體電路(IC)。這些部件可以包括例如濾波器元件、電阻器、電感器、功率放大器、電容器或者已封裝的IC卡。在其他實施方式中，其他有源或無源部件可以耦合到半導體基底102。
模塑膠112佈置在半導體基底102的第一表面A1上。模塑膠112一般地包括電絕緣材料，諸如熱固性樹脂，其佈置以保護一個或多個裸片108不受到潮濕、氧化或者與處理相關聯的破碎。在某些實施方式中，模塑膠112佈置為實質上封住一個或多個裸片108並且實質上充滿一個或多個裸片108與半導體基底102之間(例如，一個或多個凸點110之間)的區域，正如可以看到的那樣。可以將模塑膠112選擇為具有與半導體基底102和/或一個或多個裸片108的熱膨脹係數(CTE)相同或實質上類似的CTE，以減少與失配的CTE材料相關聯的應力。
根據各種實施方式，一個或多個溝道104，又稱為通孔，形成為通過半導體基底102的凹陷表面(例如，第二表面A2)。一個或多個溝道104填充有導電材料和/或導熱材料(諸如金屬)以形成一個或多個封裝互連結構114。一個或多個溝道104一般地提供半導體基底102的第一表面A1與第二表面A2之間的電通路和/或熱通路。在半導體基底102包括矽的實施方式中，一個或多個溝道104是一個或多個矽貫通孔(through-silicon via，簡寫為TSV)。在某些實施方式中，一個或多個溝道104是錐形的。在其他實施方式中，一個或多個溝道104可以是直的或者具有其他形狀。
一個或多個封裝互連結構114，諸如一個或多個焊球或杆，佈置在一個或多個溝道104中，以進一步路由一個或多個裸片108的電信號。一個或多個封裝互連結構114通過一個或多個溝道104電耦合到一個或多個再分佈層106。在圖1所示的實施方式中，一個或多個封裝互連結構114直接耦合到形成在半導體基底102的第一表面A1上的一個或多個再分佈層106。
一個或多個封裝互連結構114一般地包括導電材料，諸如金屬。一個或多個封裝互連結構114可以形成為各種各樣的形狀(包括球面、平面或者多邊形形狀)，並且可以定位在各種各樣的位置(包括在一行中，或者在含多行的陣列中)。儘管在半導體基底102的周邊部分示出了一個或多個封裝互連結構114，但在其他實施方式中，一個或多個封裝互連結構114可以佈置在半導體基底102的中心部分或者靠近該中心部分。
封裝元件100可以使用一個或多個封裝互連結構114來電耦合到另一電子設備150，以進一步向其他電子設備150路由一個或多個裸片108的電信號。該其他電子設備150可以包括例如印刷電路板(PCB)(例如，主板)、模組或者另一封裝組件。
圖2A-圖2I示意性地示出在各種工藝操作之後的封裝元件。參考圖2A，示出了在半導體基底102的至少第一表面A1上形成電介質膜105之後的封裝組件200。在實施方式中，電介質膜105形成在半導體基底102的第一表面A1和第二表面A2上，正如可以看到的那樣。電介質膜105可以通過使用沉積技術(諸如物理氣相沉積(PVD)、化學氣相沉積(CVD)和/或原子層沉積(ALD))來形成，以沉積電介質材料，諸如二氧化矽(SiO2 )、氮化矽(SiN)或者氮氧化矽(Si2 N2 O)。在其他實施方式中，可以使用其他合適的沉積技術和/或電介質材料。
參考圖2B，示出了在佈置於第一表面A1上的電介質膜105上形成一個或多個再分佈層106之後的封裝組件200。一個或多個再分佈層106一般地通過在電介質膜105上沉積導電材料而形成。可以對所沉積的導電材料進行圖案化和/或蝕刻，以提供路由一個或多個裸片(例如，圖2C的一個或多個裸片108)的電信號的路由結構(例如，跡線或焊盤)。可以將多個再分佈層堆疊在半導體基底102上，以提供對電信號的期望路由。
參考圖2C，示出了在將一個或多個裸片108電耦合到一個或多個再分佈層106之後的封裝組件200。一個或多個裸片108可以以各種各樣的配置(例如，倒裝晶片或引線鍵合配置，或者其組合)耦合到半導體基底102。在倒裝晶片配置中，裸片的活性表面使用一個或者多個凸點110耦合到一個或多個再分佈層106。在引線鍵合配置中，裸片的非活性表面使用粘合劑耦合到半導體基底102，裸片的活性表面使用一個或多個鍵合引線電耦合到一個或多個再分佈層106。
在圖2C所示的實施方式中，一個或多個凸點110形成在一個或多個裸片108上，並且以倒裝晶片配置鍵合到一個或多個再分佈層106。一個或多個凸點110可以使用凸點成形工藝(諸如可控坍塌晶片連接(C4)工藝、柱形凸點成形或者其他合適的工藝)來形成。當該一個或多個裸片108是晶片或單切的(singulated)形式時，一個或多個凸點110可以形成在一個或多個裸片108上。當半導體基底102是晶片或單切的形式時，一個或多個裸片108可以附接到半導體基底102。
參考圖2D，示出了在半導體基底102上形成模塑膠112之後的封裝組件200。模塑膠112一般地通過將電絕緣材料沉積為封住一個或多個裸片108而形成。根據各種實施方式，模塑膠112通過將固體形式(例如，粉末)的樹脂(例如，熱固性樹脂)沉積到模具中並施加熱量和/或壓力以熔化該樹脂而形成。在其他實施方式中，可以使用其他公知的用於形成模塑膠112的技術。
在某些實施方式中，模塑膠112可以與底部填充層(例如，圖3的底部填充物118)結合使用。例如，底部填充材料可以佈置在一個或多個裸片108與半導體基底102之間，以封住一個或多個凸點110，並且模塑膠112可以佈置為封住一個或多個裸片108和底部填充物。在某些實施方式中，模塑膠112可以形成為使得一個或多個裸片108的表面暴露，以便於從一個或多個裸片108散熱。
參考圖2E，示出了在使半導體基底102的第二表面A2凹陷之後的封裝元件200。半導體基底102可以通過研磨工藝或蝕刻工藝被凹陷，以提供所具有的厚度在大約10微米與大約500微米之間的半導體基底102。在其他實施方式中，可以使用其他凹陷技術和厚度。半導體基底102是凹陷的以提供更薄的基底，該更薄的基底便於或使得能夠形成完全通過半導體基底102的一個或多個溝道(例如，一個或多個溝道104)。根據各種實施方式，模塑膠112用作機械載體以在半導體基底102的第二表面A2正在被凹陷時、和/或在執行結合圖2H描述的動作時支撐半導體基底102。
參考圖2F，示出了在形成通過半導體基底102的一個或多個溝道104之後的封裝元件200。一個或多個溝道104形成為在半導體基底102的第二表面A2中/通過該半導體基底102的第二表面A2，以暴露電介質膜105，正如可以看到的那樣。一個或多個溝道104可以通過選擇性地移除半導體基底102的半導體材料而形成。例如，可以利用光刻膠膜或硬掩模而將半導體基底的第二表面A2圖案化，並且通過濕法蝕刻工藝或幹法刻蝕工藝進行蝕刻，以從選定位置移除經圖案化的半導體材料。在某些實施方式中，蝕刻工藝是選擇性蝕刻，並且電介質膜105用作蝕刻停止層。根據各種實施方式，在形成模塑膠112之後形成一個或多個溝道104。
參考圖2G，示出了在移除電介質膜105暴露於一個或多個溝道104中的部分，以便暴露一個或多個再分佈層106之後的封裝組件200。可以使用例如濕法或幹法圖案化/蝕刻工藝或者鐳射鑽孔工藝來移除電介質膜105的電介質材料。一個或多個再分佈層106的導電材料可以用作蝕刻/鐳射停止材料。
參考圖2H，示出了在一個或多個溝道104中形成一個或多個球下金屬化(UBM)結構116之後的封裝組件200。一個或多個UBM結構116一般地通過使用任何合適的沉積工藝沉積導電材料而形成。一個或多個UBM結構116可以用作一個或多個封裝互連結構(例如，圖2I的一個或多個封裝互連結構114)與半導體基底102的半導體材料之間的緩衝。在某些實施方式中，一個或多個UBM結構116形成在一個或多個溝道104中的一個或多個再分佈層106的暴露部分上，以及形成在一個或多個溝道104內的半導體基底102上。在其他實施方式中，根本不形成一個或多個UBM結構116(例如，正如在圖1的封裝元件100中可以看到的那樣)。形成UBM結構116可以提供增加的聯結可靠性。不形成UBM結構116可以簡化製作工藝和/或減少與製作工藝相關聯的成本。
參考圖2I，示出了在一個或多個溝道104中形成一個或多個封裝互連結構114之後的封裝組件200。一個或多個封裝互連結構114電耦合到一個或多個再分佈層106以路由一個或多個裸片108的電信號。在某些實施方式中，一個或多個封裝互連結構114形成在一個或多個UBM結構116上。在其他實施方式中，一個或多個封裝互連結構114直接形成在一個或多個再分佈層106上。
一個或多個封裝互連結構114可以通過各種各樣合適的技術(包括例如絲網印刷、電鍍和/或焊球放置)而形成。一個或多個封裝互連結構114可以以各種各樣的方式(包括例如球柵陣列(BGA)配置)來配置。
圖3示意性地示出包括凹陷的半導體基底102的另一封裝元件300。封裝組件300與圖21所示的封裝組件200類似，只不過封裝元件300進一步包括(i)形成在一個或多個裸片108與半導體基底102之間的底部填充物118，以及(ii)一個或多個裸片108的暴露的背側表面。
底部填充物118可以例如在形成模塑膠112之前形成(例如，如圖2C的封裝元件200所示)。根據各種實施方式，底部填充物118通過液體分配或者注射工藝而以液體形式沉積。底部填充物118可以包括例如環氧樹脂或其他合適的電絕緣材料。底部填充物118一般地增加在一個或多個裸片108與半導體基底102之間的粘合，提供一個或多個凸點110之間的電絕緣，和/或保護一個或多個凸點110不受到潮濕和氧化。在某些實施方式中，底部填充物118結合模塑膠112而使用，正如可以看到的那樣。
模塑膠112可以形成為使得一個或多個裸片108的背側表面暴露以便於散熱。在一個實施方式中，可以使用如下模具來沉積模塑膠112，該模具使得模塑膠112被形成為使得一個或多個裸片108的背側表面暴露。在其他實施方式中，模塑膠可以沉積為封住一個或多個裸片，並且隨後可以使模塑膠凹陷以暴露一個或多個裸片108的背側表面。
圖4是用以製作在此描述的封裝元件(例如，圖2I的封裝元件200)的方法400的處理流程圖。在步驟402中，方法400包括提供半導體基底(例如，圖2A的半導體基底102)。該半導體基底一般地包括第一表面(例如，圖2A的第一表面A1)和與第一表面相反地佈置的第二表面(例如，圖2A的第二表面A2)。
在步驟404中，方法400進一步包括在半導體基底上形成電介質膜(例如，圖2A的電介質膜105)。電介質膜可以根據結合圖2A而描述的技術來形成。
在步驟406中，方法400進一步包括在半導體基底上形成再分佈層(例如，圖2B的一個或多個再分佈層106)。再分佈層可以根據結合圖2B而描述的技術來形成。
在步驟408中，方法400進一步包括將一個或多個裸片(例如，圖2C的一個或多個裸片108)電耦合到再分佈層。該一個或多個裸片可以根據結合圖2C而描述的技術來耦合。
在步驟410中，方法400進一步包括在半導體基底上形成模塑膠(例如，圖2D的模塑膠112)。模塑膠可以根據結合圖2D而描述的技術來形成。
在步驟412中，方法400進一步包括使半導體基底的表面(例如，圖2E的第二表面A2)凹陷。該表面可以根據結合圖2E而描述的技術被凹陷。
在步驟414中，方法400進一步包括形成通過半導體基底的一個或多個溝道(例如，圖2F和圖2G的一個或多個溝道104)。該一個或多個溝道可以根據結合圖2F和圖2G而描述的技術來形成。
在步驟416中，方法400進一步包括在一個或多個溝道中形成一個或多個凸點下金屬化(UBM)結構(例如，圖2H的一個或多個UBM結構116)。該一個或多個UBM結構可以根據結合圖2H而描述的技術來形成。
在步驟418中，方法400進一步包括在一個或多個溝道中形成一個或多個封裝互連結構(例如，圖2I的一個或多個封裝互連結構114)。該一個或多個封裝互連結構可以根據結合圖2I而描述的技術來形成。
儘管已經在此示出和描述了特定實施方式，但在不脫離本公開範圍的情況下，用於實現相同目的的廣泛的各種各樣的變更和/或等同的實施方式或實現可以代替所示出和描述的實施方式。本公開旨在覆蓋在此討論的實施方式的任何調整或變化。因此，在此描述的實施方式顯然旨在僅由請求項書及其等同形式限定。
100．．．封裝元件
102．．．半導體基底
104．．．溝道
105．．．電介質膜
106．．．再分佈層
108．．．裸片
110．．．凸點
112．．．模塑膠
114．．．封裝互連結構
116．．．UBM結構
118．．．底部填充物
150．．．電子設備
200．．．封裝組件
300．．．封裝組件
A1．．．第一表面
A2．．．第二表面
T．．．厚度
通過結合附圖的以下詳細描述，將很容易理解本公開的實施方式。為便於進行這一描述，類似的參考標號表示類似的結構性元件。這裏的實施方式在附圖的各圖中以示例的方式而不是限制的方式示出。
圖1示意性地示出包括凹陷的半導體基底的封裝元件。
圖2A-圖2I示意性地示出在各種工藝操作之後的封裝元件。
圖3示意性地示出包括凹陷的半導體基底的另一封裝元件。
圖4是用以製作在此描述的封裝元件的方法的處理流程圖。

Claims (20)

  1. 一種用於凹陷的半導體基底的方法，包括：提供半導體基底，所述半導體基底具有(i)第一表面和(ii)與所述第一表面相反地佈置的第二表面；在所述半導體基底的所述第一表面上形成電介質膜；在所述電介質膜上形成再分佈層；將一個或多個裸片電耦合到所述再分佈層；在所述半導體基底上形成模塑膠；使所述半導體基底的所述第二表面凹陷；形成通過所述半導體基底的凹陷的第二表面的一個或多個溝道以暴露所述再分佈層；以及在所述一個或多個溝道中形成一個或多個封裝互連結構，所述一個或多個封裝互連結構被電耦合到所述再分佈層，所述一個或多個封裝互連結構用以路由所述一個或多個裸片的電信號。
  2. 根據請求項1的方法，其中所述再分佈層通過在所述電介質膜上沉積導電材料而形成。
  3. 根據請求項1的方法，其中所述一個或多個裸片以倒裝晶片配置耦合到所述再分佈層。
  4. 根據請求項1的方法，其中所述模塑膠通過將電絕緣材料沉積為實質上封住所述一個或多個裸片而形成。
  5. 根據請求項1的方法，其中所述半導體基底通過研磨工藝或蝕刻工藝被凹陷。
  6. 根據請求項1的方法，其中所述半導體基底是凹陷的，從而使得所述半導體基底所具有的厚度在大約50微米與大約300微米之間。
  7. 根據請求項1的方法，其中所述一個或多個溝道是通過如下方式形成的：選擇性地移除所述半導體基底的半導體材料；以及選擇性地移除所述電介質膜的電介質材料。
  8. 根據請求項1的方法，進一步包括：在所述一個或多個溝道中形成一個或多個球下金屬化(UBM)結構，所述一個或多個UBM結構被形成在(i)通過形成所述一個或多個溝道而暴露的所述再分佈層和(ii)所述一個或多個溝道內的所述半導體基底上，其中所述一個或多個封裝互連結構耦合到所述一個或多個UBM結構。
  9. 根據請求項1的方法，其中所述一個或多個封裝互連結構包括通過(i)絲網印刷、(ii)電鍍以及(iii)焊球放置中的至少一個而形成的焊球。
  10. 根據請求項1的方法，進一步包括：在(i)所述一個或多個裸片與(ii)所述半導體基底之間形成底部填充層。
  11. 根據請求項1的方法，其中在形成所述模塑膠之後形成 所述一個或多個溝道；以及所述模塑膠用作機械載體以在所述半導體基底的所述第二表面被凹陷時支撐所述半導體基底。
  12. 一種用於凹陷的半導體基底的裝置，包括：半導體基底，所述半導體基底具有(i)第一表面和(ii)與所述第一表面相反地佈置的第二表面；形成在所述半導體基底的所述第一表面上的電介質膜；形成在所述電介質膜上的再分佈層；電耦合到所述再分佈層的一個或多個裸片；形成在所述半導體基底上的模塑膠；形成為通過所述半導體基底的所述第二表面的一個或多個溝道，其中所述一個或多個溝道在所述第二表面具有至少與一封裝互連結構的寬度等寬的寬度；以及沉積在所述一個或多個溝道中的一個或多個所述封裝互連結構，所述一個或多個封裝互連結構通過所述一個或多個溝道電耦合到所述再分佈層，以路由所述一個或多個裸片的電信號。
  13. 根據請求項12的裝置，其中所述一個或多個裸片使用一個或多個凸點以倒裝晶片配置耦合到所述再分佈層。
  14. 根據請求項12的裝置，其中所述模塑膠實質上封住所述一個或多個裸片。
  15. 根據請求項12的裝置，其中所述半導體基底的所述第二表面是凹陷的，從而使得所述半導體基底所具有的厚度在大 約50微米與大約300微米之間。
  16. 根據請求項12的裝置，進一步包括：形成在所述一個或多個溝道中的一個或多個球下金屬化(UBM)結構，所述一個或多個UBM結構形成在(i)所述再分佈層和(ii)所述一個或多個溝道內的所述半導體基底上，其中所述一個或多個封裝互連結構耦合到所述一個或多個UBM結構。
  17. 根據請求項12的裝置，進一步包括：形成在(i)所述一個或多個裸片與(ii)所述半導體基底之間的底部填充層。
  18. 根據請求項12的裝置，其中：所述一個或多個封裝互連結構包括焊球用以路由所述一個或多個裸片的電信號；以及所述再分佈層包括導電材料用以路由所述一個或多個裸片的所述電信號。
  19. 根據請求項12的裝置，其中：所述半導體基底包括矽；所述一個或多個裸片包括矽；以及所述一個或多個溝道包括一個或多個矽貫通孔。
  20. 根據請求項19的裝置，其中：所述模塑膠和所述半導體基底具有相同或實質上類似的熱膨脹係數(CTE)；以及 所述一個或多個矽貫通孔是錐形的。
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