TWI441285B - 用於封裝裝置之凹陷的半導體基底及其方法 - Google Patents

用於封裝裝置之凹陷的半導體基底及其方法 Download PDF

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TWI441285B
TWI441285B TW100103446A TW100103446A TWI441285B TW I441285 B TWI441285 B TW I441285B TW 100103446 A TW100103446 A TW 100103446A TW 100103446 A TW100103446 A TW 100103446A TW I441285 B TWI441285 B TW I441285B
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Taiwan
Prior art keywords
semiconductor substrate
vias
die
package
recessed
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TW100103446A
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English (en)
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TW201140768A (en
Inventor
Albert Wu
Roawen Chen
Chung-Chyung Han
Shiann-Ming Liou
Chien-Chuan Wei
Runzi Chang
Scott Wu
Chuan-Cheng Cheng
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Marvell World Trade Ltd
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Publication of TW201140768A publication Critical patent/TW201140768A/zh
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    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

用於封裝裝置之凹陷的半導體基底及其方法
本公開的實施方式涉及積體電路領域，並且更具體而言，本公開的實施方式涉及用於封裝元件的凹陷的半導體基底的技術、結構和配置。
本文在此所提供的背景技術描述是以對本公開的內容作一般性說明為目的。在背景技術部分描述的範圍內，目前提及姓名的發明人的工作，以及本說明書在提交申請時可能尚未成為現有技術的方面，無論明示地還是暗含地，都不應認為是針對本公開的現有技術。
在裸片或晶片上形成諸如電晶體之類的積體電路器件，該裸片或晶片的尺寸持續在尺寸上縮小至更小維度。裸片的縮減維度正挑戰傳統基底製造技術和/或封裝組件技術，該傳統基底製造技術和/或封裝元件技術當前用於向半導體裸片路由電信號或從半導體裸片路由出電信號。舉例而言，層壓基底技術可能不能在基底上製作足夠小的特徵，以符合更細微的節距的互連或在該裸片上形成的其他信號路由特徵。
在一個實施方式中，本公開提供了一種裝置，該裝置包括半導體基底和耦合到該半導體基底的裸片，該半導體基底具有第一表面、與第一表面相反佈置的第二表面以及一個或更多個過孔，其中第一表面的至少一部分凹陷以形成半導體基底的凹陷區域，該一個或更多個過孔形成在半導體基底的凹陷區域中，以提供在半導體基底的第一表面和第二表面之間的電通路或熱通路，該裸片電耦合到在半導體基底的凹陷區域中形成的一個或更多個過孔。
在另一實施方式中，本公開提供了一種方法，該方法包括：提供具有(i)第一表面和(ii)與第一表面相反佈置的第二表面的半導體基底；使第一表面的至少一部分凹陷以形成半導體基底的凹陷區域；在半導體基底的凹陷區域中形成一個或更多個過孔，以提供在半導體基底的第一表面和第二表面之間的電通路或熱通路；以及將裸片耦合到半導體基底，該裸片電耦合到在半導體基底的凹陷區域中形成的一個或更多個過孔。
本公開要求2010年2月3日提交的第61/301,125號美國臨時專利申請、2010年3月22日提交的第61/316,282號美國臨時專利申請、2010年4月5日提交的第61/321,068號美國臨時專利申請和2010年4月16日提交的第61/325,189號美國臨時專利申請的優先權，除了與本說明書不一致之處的部分(如果存在這些部分)外，在此通過引用將以上專利申請的整個說明書全文併入本文用於所有目的。
本公開的實施方式描述具有凹陷區域的半導體基底和相關封裝元件的技術、結構和配置。
本說明書可以使用基於透視的描述，例如上/下、之上/之下和/或頂部/底部。這類描述僅用於方便論述，並非意于將本文所述實施方式的應用限制於任何特定的方向。
為了本公開的目的，用語“A/B”意味著A或B。為了本公開的目的，用語“A和/或B”意味著“(A)、(B)或(A和B)”。為了本公開的目的，用語“A、B和C中至少一個”意味著“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)”。為了本公開的目的，用語“(A)B”意味著“(B)或(AB)”，也即，A是可選元素。
以最有助於理解請求項主題的方式，描述了作為相繼的多個分立操作的各種操作。然而，描述的順序不應被解釋為暗示這些操作是必須依此順序。具體而言，這些操作可不以所呈現的順序來執行。所描述的操作可以與所描述的實施方式不同的順序來執行。在附加的實施方式中可執行各種附加的操作和/或可省略所描述的操作。
說明書使用用語“在實施方式中”、“在一些實施方式中”或類似語言，所述用語可均指一個或更多個相同的或不同的實施方式。此外，針對本公開的實施方式所使用的術語“包括”、“包含”、“具有”等是同義詞。
圖1至圖19示意性地示出了各種示例封裝元件，該封裝元件包括具有凹陷區域(例如，佈置在區域104內的半導體基底102的部分，以下稱為凹陷區域104)的半導體基底102。圖1描繪了依照各種實施方式的封裝元件100的配置。封裝元件100包括半導體基底102，半導體基底102是實質上包括諸如矽(Si)之類的半導體材料的基底或內插板(interposer)。也即，半導體基底102的材料的主體是半導體材料。該半導體材料可包括結晶類材料和/或無定形類材料。舉例而言，在該半導體材料是矽的情形中，該矽材料可包括單晶矽和/或多晶矽的類型。在其他的實施方式中，半導體基底102可包括其他半導體材料，例如鍺、III-V族材料或II-VI族材料，該鍺、III-V族材料或II-VI族材料也可受益于本文所述的原理。
半導體基底102包括第一表面A1和與第一表面A1相反佈置的第二表面A2。第一表面A1和第二表面A2一般指半導體基底102的相反表面以便於描述本文中所述的各種配置。
根據各種實施方式，使第一表面A1的一部分相對於第一表面A1的其他部分凹陷，以形成半導體基底102的凹陷區域104。凹陷區域104一般提供半導體基底102的相對較薄的區域，從而便於形成穿過半導體基底102的一個或更多個過孔112。在一些實施方式中，將半導體基底102凹陷使得凹陷區域104具有在約10微米和約500微米之間的厚度T1。
圖1的半導體基底102包括半導體基底102的區域106，該區域106在凹陷區域104之外且比凹陷區域104厚，以下將其稱為較厚區域106。在較厚區域106內的半導體基底102的厚度T2大於凹陷區域104的厚度T1。
半導體基底102使用類似於公知用於製造裸片上或晶片上的積體電路(IC)結構的那些技術來製造。舉例而言，可使用眾所周知的諸如光刻/蝕刻和/或沉積工藝之類的用於製造裸片上的IC器件的構圖工藝來形成半導體基底102的特徵。通過使用半導體製造技術，半導體基底102可包括比其他類型基底更小的特徵，該其他類型基底例如層壓(例如有機)基底。對於持續縮減尺寸的當前裸片而言，半導體基底102便於路由諸如輸入/輸出(I/O)信號和/或電源/接地信號之類的電信號。舉例而言，在一些實施方式中，半導體基底102允許細微節距的Si對Si互連和在半導體基底102和一個或更多個裸片112之間路由的最終線路。
根據各種實施方式，在半導體基底102的凹陷區域104中形成一個或更多個過孔112。利用諸如金屬的導電和/或導熱的材料來填充該一個或更多個過孔112。在該一個或更多個過孔的金屬和半導體基底的半導體材料之間可以佈置電介質材料。該一個或更多個過孔112一般提供在半導體基底102的第一表面A1和第二表面A2之間的電通路或熱通路。在半導體基底102包括矽的實施方式中，該一個或更多個過孔112是一個或更多個矽貫通孔(TSV)。
在該半導體基底102的第一表面A1和/或第二表面A2上可以形成一個或更多個再分佈層110，以路由耦合至半導體基底102的一個或更多個裸片112的電信號。舉例而言，一個或更多個再分佈層110可以在一個或更多個裸片112和一個或更多個過孔108之間以及在一個或更多個過孔108和一個或更多個封裝互連結構114之間提供電路由。
一個或更多個再分佈層110例如可以通過以下方式形成：在半導體基底102的表面上形成電介質層，該電介質層例如包括二氧化矽(SiO2 )、氮化矽(SiN)、氮氧化矽(SiOx Ny )或其他適當電介質材料，以及在電介質層上沉積和/或構圖的導電材料，該導電材料諸如金屬(例如銅或鋁)或摻雜半導體材料(例如摻雜多晶矽)。在其他實施方式中，可以使用其他適當導電材料來形成一個或更多個再分佈層110。
一個或更多個再分佈層110可包括各種結構以路由電信號，該多種結構例如焊盤、焊區或跡線。儘管未描繪出，但在一個或更多個再分佈層110上可沉積包括電絕緣材料的鈍化層，並對鈍化層進行構圖以提供鈍化層中的開口，從而允許一個或更多個裸片112電耦合至一個或更多個再分佈層110，該電絕緣材料例如聚醯亞胺。
使用任何適當的配置，例如包括倒裝晶片配置，如所示將一個或更多個裸片112耦合至半導體基底102。在其他實施方式中，可以使用其他適當的裸片附接配置，例如引線鍵合配置。在圖1的所示實施方式中，一個或更多個裸片112耦合到半導體基底102的凹陷區域104的第一表面A1。
一個或更多個裸片112一般包括諸如矽之類的半導體材料。在一個實施方式中，將使用同一半導體材料製造一個或更多個裸片112和半導體基底102，以降低與材料的加熱/冷卻不匹配相關聯的應力，該熱/冷不匹配諸如不匹配的熱膨脹係數(CTE)。
一個或更多個裸片112一般具有有源側和與有源側相反佈置的無源側，該有源側包括的表面上形成有多個積體電路(IC)器件(未示出)，該積體電路器件例如用於邏輯和/或記憶體的電晶體。一個或更多個裸片112的有源側電耦合至一個或更多個再分佈層110。在一些實施方式中，如所見，使用一個或更多個凸點111將一個或更多個裸片112的有源側耦合至一個或更多個再分佈層110。在其他實施方式中，使用諸如一個或更多個鍵合引線之類的其他結構將一個或更多個裸片112的有源側電耦合至一個或更多個再分佈層110。
在圖1的所示實施方式中，一個或更多個凸點111形成在一個或更多個裸片112上，並且鍵合到一個或更多個再分佈層110。一個或更多個凸點111一般包括諸如焊料或其他金屬之類的導電材料，以路由一個或更多個裸片112的電信號。根據各種實施方式，一個或更多個凸點111包括鉛、金、錫、銅、無鉛材料或它們的組合。一個或更多個凸點111可具有多種形狀並可使用凸點成形工藝形成，該多種形狀包括球形、圓柱形、矩形或其他形狀，該凸點成形工藝例如受控坍塌晶片連接(C4)工藝、柱形凸點成形(Stud-bumping)工藝或其他適當工藝。
一個或更多個凸點111可以在一個或更多個裸片112處於晶片形式或單切的(singulated)形式的情況下形成在一個或更多個裸片112上。一個或更多個裸片112可以在處於晶片形式或單切的形式的情況下附接到半導體基底102。
雖然圖中未示出，但一個或更多個其他的有源元件或者無源元件可安裝在半導體基底102上。該組件可包括電子元件和積體電路(IC)。舉例而言，該元件可包括濾波器元件、電阻器、電感器、功率放大器、電容器或經封裝的IC。在其他實施方式中，其他的有源元件或無源元件可耦合至半導體基底102。
在一個或更多個再分佈層110上可以形成諸如一個或更多個焊料球、金屬柱或凸點之類的一個或更多個封裝互連結構114，以進一步路由一個或更多個裸片112的電信號。在圖1的所示實施方式中，一個或更多個封裝互連結構114耦合至半導體基底102的第二表面A2上形成的一個或更多個再分佈層110。一個或更多個封裝互連結構114一般包括導電材料。一個或更多個封裝互連結構114可形成為多種形狀並可放置成多種定位，該多種形狀包括球形、平面形狀或多邊形形狀，該多種定位包括成行或多行的陣列。儘管一個或更多個封裝互連結構114示出在半導體基底102的週邊部分上，但在其他實施方式中，一個或更多個封裝互連結構114可佈置在半導體基底102的中心部分上或靠近中心部分。
圖2描繪了依照各種實施方式的封裝元件200的另一配置。封裝元件200具有耦合到半導體基底102的相反表面的一個或更多個裸片112。一個或更多個裸片112耦合到在半導體基底102的第一表面A1和半導體基底的第二表面A2二者上的一個或更多個再分佈層110。封裝元件200允許一個或更多個裸片112對半導體基底102的兩面進行耦合。在圖2的所示實施方式中，第一表面A1上的一個或更多個裸片112耦合到半導體基底102的同一凹陷區域104。
使用佈置在半導體基底102的第二表面A2上的一個或更多個封裝互連結構114，可以將封裝元件200電耦合到另一電子器件250，以進一步將一個或更多個半導體裸片112的電信號路由到另一電子器件250，該其他電子器件250諸如印刷電路板(PCB)(例如母板)、模組或另一封裝元件。
圖3描繪了依照各種實施方式的封裝元件300的配置。封裝元件300具有形成在半導體基底102的第一表面A1上的一個或更多個封裝互連結構114，以將半導體基底102電耦合到另一電子器件250。也就是，一個或更多個封裝互連結構114可以耦合到被凹陷以形成凹陷區域104的同一表面(例如，圖3中的第一表面A1)。
圖4描繪了依照各種實施方式的封裝元件400的配置。封裝元件400具有佈置在半導體基底102的第一表面A1和第二表面A2二者上的一個或更多個封裝互連結構114。封裝元件400允許另一電子器件250使用佈置在第一表面A1上的一個或更多個封裝互連結構114耦合到第一表面A1，並且允許另一電子器件250使用佈置在第二表面A2上的一個或更多個封裝互連結構114耦合到第二表面A2。舉例而言，在一個實施方式中，耦合到第一表面A1的其他電子器件250是印刷電路板，而耦合到第二表面A2的其他電子器件250是另一封裝元件。封裝元件400可以以各種層疊封裝(POP)或其他三維(3D)封裝配置來進行配置。
圖5描繪了依照各種實施方式的封裝元件500的另一配置。封裝元件500具有形成在半導體基底102的第一表面A1中的作為第一凹陷區域的凹陷區域104和作為第二凹陷區域的至少另一凹陷區域504。凹陷區域104可以通過使第一表面A1的第一部分凹陷來形成，而其他凹陷區域504可以通過使第一表面A1的第二部分凹陷來形成。凹陷區域104和其他凹陷區域504通過半導體基底102的較厚區域106分隔開。較厚區域106為封裝元件500提供較強的機械支撐，包括在製造、封裝和/或組件操作期間。
在所示實施方式中，在凹陷區域104和其他凹陷區域504二者中形成一個或更多個過孔108，並且在凹陷區域104和其他凹陷區域504的每個中佈置一個或更多個裸片112的至少一個裸片。在其他實施方式中，可以使用附加的凹陷區域。
圖6描繪了依照各種實施方式的封裝元件600的另一配置。封裝元件600的半導體基底102具有凹陷的第一表面A1以形成凹陷區域104。在半導體基底102的第二表面A2上佈置一個或更多個裸片112。在所示實施方式中，將一個或更多個裸片112耦合到半導體基底102的凹陷區域104的第二表面A2，該第二表面A2相對於第一表面A1是實質上平坦的。可以以包括球柵陣列(BGA)配置的各種配置來佈置一個或更多個封裝互連結構114。
圖7描繪了依照各種實施方式的封裝元件700的另一配置。封裝元件700具有形成在半導體基底102的第一表面A1中的作為第一凹陷區域的凹陷區域104和作為第二凹陷區域的至少另一凹陷區域504。凹陷區域104和其他凹陷區域504通過半導體基底102的較厚區域106分隔開。
一個或更多個裸片112耦合到凹陷區域104的第一表面A1，並且一個或更多個封裝互連結構114耦合到其他凹陷區域504的第一表面A1。如所見，與一個或更多個封裝互連結構耦合到較厚區域(例如較厚區域106)的封裝元件相比，一個或更多個封裝互連結構114耦合到其他凹陷區域504的封裝元件700提供更薄的封裝元件700。在所示實施方式中，使用形成在半導體基底102的第一表面A1上的一個或更多個再分佈層110，將一個或更多個封裝互連結構114電耦合到一個或更多個裸片112。
圖8描繪了根據各種實施方式的封裝元件800的另一配置。類似于圖7的封裝元件700，封裝元件800包括凹陷區域104、另一凹陷區域504和較厚區域106。封裝元件800還包括形成在其他凹陷區域504中的一個或更多個過孔108，用於將一個或更多個封裝互連結構114電耦合到一個或更多個裸片112。如所見，佈置在其他凹陷區域504中的一個或更多個過孔108至少通過形成在第二表面A2上的一個或更多再分佈層110和佈置在凹陷區域104中的一個或更多過孔108，而電耦合到一個或更多個裸片112。
圖9描繪了根據各種實施方式的封裝元件900的另一配置。類似於結合圖7和圖8所描述的那樣，封裝元件900包括凹陷區域104、另一凹陷區域504和較厚區域106。在圖9中，將半導體基底102的第二表面A2的至少一部分凹陷，以露出佈置在凹陷區域104中的一個或更多個過孔108，使得一個或更多個過孔108延伸到第二表面A2的凹陷部分之外，限定一個或更多個過孔108的延伸部分960。一個或更多個過孔108的延伸部分960可以用作熱沉的一個或者多個散熱片，以便於將熱量從一個或更多個裸片112移走。
圖10描繪了根據各種實施方式的封裝元件1000的另一配置。封裝元件1000包括通過使半導體基底102的第二表面A2的至少一部分凹陷而形成的一個或更多個過孔108的延伸部分960。包括例如氧化物的膜或電介質襯墊120佈置在一個或更多個過孔108的導電和/或導熱材料上。電介質襯墊120例如可以用作保護層來保護一個或更多個過孔108的導電和/或導熱材料免受損於使半導體基底的第二表面A2凹陷以暴露一個或更多個過孔108的工藝(例如蝕刻)。如所見，可以使用一個或更多個凸點111將一個或更多個裸片112電耦合到一個或更多個過孔108的延伸部分960。
圖11描繪了根據各種實施方式的封裝元件1100的另一配置。如所見，封裝元件1100包括凹陷區域104和較厚區域106。在較厚區域106的表面上形成一個或更多個選擇性凹陷的區域113，諸如孔或通道，從而增加半導體基底102的表面面積並因而便於熱量從封裝元件1100的熱源散掉。
圖12描繪了根據各種實施方式的封裝元件1200的另一配置。如所見，封裝元件1200包括凹陷區域104、另一凹陷區域504和佈置在凹陷區域104和其他凹陷區域504之間的較厚區域106。一個或更多個過孔108形成在凹陷區域104和其他凹陷區域504中。一個或更多個封裝互連結構114的至少一個封裝互連結構佈置在凹陷區域104和其他凹陷區域504的第一表面A1上。這種配置可以減小封裝元件1200的總高度或厚度。如所見，一個或更多個裸片112耦合到較厚區域106的第一表面A1和/或第二表面A2。
圖13描繪了根據各種實施方式的封裝元件1300的另一配置。封裝元件1300包括完全穿過半導體基底102的一個或更多個過孔108。也就是，在凹陷區域104和其他凹陷區域504中形成一個或更多個過孔108，以形成在半導體基底102的第一表面A1和第二表面A2之間的持續電連接或熱連接。在半導體基底102的較厚區域106的第二表面A2中形成一個或更多個附加過孔1308。該一個或更多個附加過孔1308不完全穿過半導體基底102。也就是，在所示實施方式中，一個或更多個附加過孔1308僅佈置在半導體基底102的第二表面A2上，並不到達第一表面A1。一個或更多個附加過孔1308通過在封裝元件1300中為熱量提供熱通路，從而提供便於熱移走的指狀物結構。
圖14描繪了根據各種實施方式的用於封裝元件1400的另一配置。封裝元件1400包括形成在半導體基底102的較厚區域106的第一表面A1中的一個或更多個附加過孔1308。一個或更多個附加過孔1308不完全穿過半導體基底102。也就是，在所示實施方式中，一個或更多個附加過孔1308僅佈置在半導體基底102的第一表面A1上，並不到達第二表面A2。一個或更多個附加過孔1308通過在封裝元件1400中為熱量提供熱通路，從而提供便於熱移走的指狀物結構。
圖15描繪了根據各種實施方式的用於封裝元件1500的另一配置。封裝元件1500包括形成在半導體基底102的第二表面A2中的凹陷區域104和另一凹陷區域504，如所見。通過使半導體基底102的第一表面A1的至少一部分凹陷而形成附加凹陷區域1504，如所見。一個或更多個過孔108佈置在凹陷區域104、其他凹陷區域504和附加凹陷區域1504中，如所見。一個或更多個封裝互連結構114佈置在凹陷區域104和其他凹陷區域504的第二表面A2中。一個或更多個裸片112佈置在附加凹陷區域1504的第一表面A1中。這種配置提供具有減小的高度或厚度的封裝元件1500。
圖16描繪了根據各種實施方式的用於封裝元件1600的另一配置。封裝元件1600包括以與圖15的封裝元件1500的半導體基底102類似的方式配置的半導體基底102。封裝元件1600還包括疊置在半導體基底102上的另一半導體基底1602，如所見。其他半導體基底1602包括形成在其他半導體基底1602的第二表面A2中的凹陷區域104和另一凹陷區域504。附加凹陷區域1504形成在其他半導體基底1602的第一表面A1中，如所見。一個或更多個過孔108形成在附加凹陷區域1504中，並且一個或更多個半導體裸片112電耦合到佈置在附加凹陷區域1504中的一個或更多個過孔108。
根據各種實施方式，半導體基底102的第二表面A2耦合到其他半導體基底1602的第二表面A2。半導體基底102和其他半導體基底1602可以使用例如一個或更多個封裝互連結構114來耦合，如所見。在其他實施方式中，可以在半導體基底102與其他半導體基底1602之間製作其他類型的電連接或結構連接。
圖17描繪了根據各種實施方式的用於封裝元件1700的另一配置。封裝元件1700包括以與圖4的封裝元件400的半導體基底102類似的方式配置的半導體基底102。封裝元件1700還包括佈置在半導體基底102的第一表面A1和/或第二表面A2上的模塑膠130。在一些實施方式中，模塑膠130佈置為實質上包封一個或更多個半導體裸片112。模塑膠130一般保護一個或更多個半導體裸片112免受與操縱相關聯的濕氣、氧化或碎裂。
在一些實施方式中，模塑膠130可以結合底部填充材料(未示出)來使用。例如，底部填充材料可以佈置在一個或更多個裸片112和半導體基底102之間，以包封一個或更多個凸點111，並且模塑膠130可以佈置為包封一個或更多個裸片112。在一些實施方式中，模塑膠130可以形成為使得一個或更多個裸片112的表面暴露，以便於熱量從一個或更多個裸片112散去。模塑膠130可以選擇為具有實質上與半導體基底102和/或一個或更多個裸片112的熱膨脹係數相同或類似的熱膨脹係數。
圖18描繪了根據各種實施方式的用於封裝元件1800的另一配置。封裝元件1800包括耦合到半導體基底102的一個或更多個裸片112。一個或更多個裸片112的裸片使用粘合劑142耦合到半導體基底，以將該裸片的非有源表面附接到半導體基底的第二表面A2，如所見。一個或更多個鍵合線140將該裸片的有源表面電耦合到一個或更多個再分佈層110，如所見。
模塑膠130佈置為實質上包封一個或更多個裸片112和一個或更多個鍵合線140，如所見。在各種實施方式中，可以使用倒裝晶片配置和引線鍵合配置的其他組合或者僅引線鍵合配置。
圖19描繪了根據各種實施方式的用於封裝元件1900的另一配置。半導體基底102包括形成在第一表面A1中的凹陷區域104和形成在凹陷區域104中的一個或更多個過孔108。第一表面A1凹陷以暴露一個或更多個過孔108的延伸部分960。電介質襯墊120佈置在一個或更多個過孔108的導電和/或導熱材料上，如所見。一個或更多個裸片112耦合到一個或更多個過孔108的延伸部分960，如所見。模塑膠130佈置為實質上包封一個或更多個裸片112，並且佈置為填充在一個或更多個半導體裸片與半導體基底102之間的區域，如所見。
如這裏所描述的那樣，使用半導體基底的封裝元件的配置可以提供以下益處：降低與在半導體基底中製造一個或更多個過孔相關聯的成本和/或工藝複雜度，能夠實現半導體基底的兩面利用，便於多疊置封裝配置，減小封裝元件的尺寸，和/或增加散熱。本公開在其範圍內包括結合圖1至圖19所描述的實施方式的任意適當組合。
圖20是用於製造包括具有凹陷區域(例如圖1的凹陷區域104)的半導體基底(例如圖1的半導體基底102)的封裝元件(例如圖1的封裝元件100)的方法2000的工藝流程圖。在2002，方法2000包括提供半導體基底。半導體基底具有第一表面(例如圖1的第一表面A1)和與第一表面相反佈置的第二表面(例如圖1的第二表面A2)。半導體基底包括諸如矽之類的半導體材料。半導體基底可以例如從單晶或多晶半導體材料的錠來切割。在結合方法2000描述的處理期間，半導體基底可以處於單切的形式或晶片形式。
在2004，方法2000還包括使半導體基底凹陷以形成一個或更多個凹陷區域(例如圖1的凹陷區域104)。使半導體基底的表面的至少一部分凹陷，以從半導體基底移除半導體材料並提供較薄的凹陷區域，以便於形成通過凹陷區域的一個或更多個過孔。可以使用包括諸如矽濕法蝕刻工藝之類的公知蝕刻工藝的任何適當工藝來使半導體基底的表面凹陷。
在一些實施方式中，僅使第一表面的一部分凹陷。在其他實施方式中，使第一表面和/或第二表面的部分凹陷，以提供如這裏所述的具有多個凹陷區域的封裝元件配置。根據各種實施方式，凹陷區域的厚度比凹陷區域外部的半導體基底的區域(例如，圖1的較厚區域106)的厚度小。
在2006，方法2000還包括在半導體基底中形成一個或更多個過孔(例如圖1的一個或更多個過孔108)。一個或更多個過孔一般形成在凹陷區域中，以提供在半導體基底的第一表面和第二表面之間的電通路和/或熱通路。根據各種實施方式，一個或更多個過孔包括矽貫通孔(TSV)。
一個或更多個過孔一般通過從凹陷區域移除半導體材料，以形成通過半導體基底的一個或更多個通道而形成。可以使用各種適當工藝來形成該一個或更多個通道，該適當工藝包括從凹陷區域移除半導體材料的鐳射鑽孔工藝和/或蝕刻工藝。該凹陷區域通過提供允許鑽孔和/蝕刻一個或更多個過孔完全穿過半導體基底的半導體材料的厚度，可以便於一個或更多個過孔的形成。儘管過孔可以通過從半導體基底的第一面或第二面移除材料而形成，但通過從更平或更平坦的表面(例如圖1的第二表面A2)移除材料可以有利於過孔形成工藝。
在形成一個或更多個通道之後，可以在一個或更多個通道的表面上形成電介質膜。電介質膜可以通過使用諸如物理氣相沉積(PVD)、化學氣相沉積(CVD)和/或原子層沉積(ALD)之類的沉積技術，來沉積諸如二氧化矽(SiO2 )、氮化矽(SiN)或氮氧化矽(SiOx Ny )之類的電介質材料而形成，其中x和y表示適當的化學計量值。在其他實施方式中，可以使用其他適當的沉積技術和/或電介質材料。電介質膜一般為佈置在一個或更多個過孔中的導電材料提供電隔離，以防止在導電材料與半導體基底的半導體材料(例如矽)之間的電流洩漏。
將諸如銅或其他金屬之類的導電和/或導熱材料沉積到一個或更多個通道中。在一個實施方式中，將導電和/或導熱材料沉積為實質上填充一個或更多個通道。在另一實施方式中，將導電和/或導熱材料沉積為塗敷在一個或更多個通道的表面上的電介質膜，並且將諸如環氧樹脂、樹脂或氧化物之類的電絕緣材料沉積為填充一個或更多個通道的其餘部分。
可以使用一個或更多個過孔路由耦合到半導體基底的一個或更多個裸片的電信號。在一些實施方式中，在半導體基底的較厚區域(例如圖13的較厚區域106)中形成一個或更多個過孔(例如圖13的一個或更多個附加過孔1308)以便於散熱。這種過孔一般僅佈置在半導體基底的第一表面和第二表面中的一個表面上。也就是，形成在較厚區域中的一個或更多個過孔不完全穿過半導體基底。
在一些實施方式中，在形成一個或更多個過孔之後使半導體基底的表面凹陷，以提供在半導體基底的凹陷表面之外延伸的一個或更多個過孔的延伸部分(例如圖9的延伸部分960)。佈置在一個或更多個過孔的一個或更多個通道的表面上的電介質膜(例如圖10的電介質襯墊120)可以保護一個或更多個過孔的導電和/或導熱材料免受損於用於暴露延伸部分的蝕刻工藝。可以使用諸如間隔層蝕刻工藝之類的另一蝕刻工藝來去除電介質膜的一部分，以便於一個或更多個裸片耦合到一個或更多過孔的導電和/或導熱材料。
在2008，方法2000還包括在半導體基底上形成再分佈層(例如圖1的一個或更多個再分佈層110)。再分佈層一般通過在半導體基底的表面上沉積電介質膜以及在電介質膜上沉積導電材料來形成。在一些實施方式中，該電介質膜與用於形成一個或更多個過孔的電介質膜的沉積同時地沉積。可以對沉積的導電材料進行構圖和/或蝕刻以提供再分佈層的路由結構，該路由結構路由一個或更多個裸片的電信號。可以在半導體基底的第一表面和/或第二表面上疊置多個再分佈層以提供電信號的期望路由。
在2010，方法2000還包括將一個或更多個裸片耦合到半導體基底。該一個或更多個裸片可以按照各種配置耦合到半導體基底，該各種配置例如包括倒裝晶片配置或引線鍵合配置或者其組合。在倒裝晶片配置中，使用一個或更多個凸點(例如圖1的一個或更多個凸點)將裸片的有源表面耦合到再分佈層。在引線鍵合配置中，使用粘合劑(例如圖18的粘合劑142)將裸片的非有源表面耦合到半導體基底，並且使用一個或更多個鍵合線140將裸片的有源表面耦合到再分佈層。該一個或更多個裸片電耦合到在半導體基底的凹陷區域中形成的一個或更多個過孔。
該一個或更多個裸片可以耦合到半導體基底的第一表面和/或第二表面。此外，根據各種實施方式，該一個或更多個裸片可以耦合到半導體基底的凹陷區域或較厚區域。
在2012，方法2000還包括將一個或更多個封裝互連結構(例如圖1的一個或更多個封裝互連結構114)耦合到半導體基底。該一個或更多個封裝互連結構可以通過各種適當工藝形成，該各種適當工藝包括例如絲網印刷、電鍍、貼裝或其他公知方法。該一個或更多個封裝互連結構電耦合到在半導體基底的第一表面和第二表面中的一個或兩個表面上的再分佈層，以將一個或更多個裸片的電信號路由到封裝組件，或者從封裝元件路由到另一電子器件(例如圖2的另一電子器件250)。
在2014，方法2000還包括在半導體基底上形成模塑膠(例如圖17的模塑膠130)。該模塑膠可以形成在半導體基底的第一表面和第二表面中的一個或兩個表面上。該模塑膠一般佈置為包封一個或更多個裸片。根據各種實施方式，通過以固態形式(例如粉末)將(例如，熱固性)樹脂沉積到模具中並施加熱量和/或壓力來融化樹脂，由此形成該模塑膠。在其他實施方式中可以使用用於形成模塑膠的其他公知技術。
在一些實施方式中，在將一個或更多個封裝互連結構耦合到半導體基底之後形成模塑膠。在這種情況下，可以形成模塑膠以提供對一個或更多個封裝互連結構的電接入。例如，可以沉積模塑膠使得模塑膠不完全包封一個或更多個封裝互連結構。在另一示例中，在一個或更多個封裝互連結構用作蝕刻/鐳射停止材料的情況下，可以通過例如蝕刻或鐳射工藝在模塑膠中形成開口，以暴露用於電接入的一個或更多個封裝互連結構。在另一示例中，可以對模塑膠進行拋光或另外進行凹陷以暴露一個或更多個封裝互連結構。
在其他實施方式中，在將一個或更多個封裝互連結構耦合到半導體基底之前形成模塑膠。在這種情況下，可以選擇性地形成模塑膠使得模塑膠不覆蓋其中將要耦合一個或更多個封裝互連結構的再分佈層的區域。在另一示例中，可以使用例如鐳射或蝕刻工藝在模塑膠中形成一個或更多個開口以暴露再分佈層，並且可以在開口中形成一個或更多個封裝互連結構。
在2016，方法2000還包括將半導體基底耦合到另一電子器件(例如圖2的其他電子器件250)。使用一個或更多個封裝互連結構，將半導體基底電耦合到諸如印刷電路板或另一半導體基底或內插板之類的另一電子器件。可以使用包括例如球柵陣列(BGA)配置的各種配置來將半導體基底耦合到其他電子器件。在一種實施方式中，將半導體基底的一個表面耦合到印刷電路板，而將半導體基底的相反表面耦合到另一半導體基底。
圖21是用於製造包括具有凹陷區域的半導體基底的封裝元件的另一方法2100的工藝流程圖。該方法2100一般性地描述其中在將一個或更多個裸片耦合到半導體基底之前形成一個或更多個過孔的技術。該方法2100可以與結合方法2000描述的相似實施方式相一致。
在2102，方法2100包括提供半導體基底。該基底包括第一表面和與第一表面相反佈置的第二表面。
在2104，方法2100還包括在半導體基底中形成一個或更多個過孔。該一個或更多個過孔可以形成在半導體基底的表面中，使得一個或更多個過孔初始地僅穿過半導體基底的一部分，而不到達半導體基底的相反表面。可以使用如結合方法2000描述的類似技術來形成該一個或更多個過孔。
在2106，方法2100還包括在半導體基底上形成再分佈層。可以使用如結合方法2000描述的類似技術來形成再分佈層。
在2108，方法2100還包括將一個或更多個裸片耦合到半導體基底。該一個或更多個裸片電耦合到再分佈層。可以使用如結合方法2000描述的類似技術來將該一個或更多個裸片耦合到基底。
在2110，方法2100還包括在半導體基底上形成模塑膠。可以使用如結合方法2000描述的類似技術來形成模塑膠。
在2112，方法2100還包括使半導體基底的表面凹陷以暴露一個或更多個過孔。凹陷的表面是與其中形成一個或更多個過孔的表面相反的表面。也就是，如果一個或更多個過孔形成在半導體基底的第一表面中，則使第二表面凹陷，反之亦然。可以通過研磨工藝或蝕刻工藝，來使半導體基底凹陷以提供厚度在約10微米和約500微米之間的凹陷區域。在其他實施方式中可以使用其他凹陷技術和厚度。根據各種實施方式，在用以暴露一個或更多個過孔的凹陷期間將模塑膠用作機械載體以支撐半導體基底。
方法2100還可以包括2114處的在凹陷表面上形成再分佈層、2116處的將一個或更多個裸片耦合到凹陷表面、2118處的在凹陷表面上形成模塑膠、以及2120處的將一個或更多個封裝互連結構耦合到再分佈層。這些動作可以與結合方法2000的已描述相似動作相一致。
圖22是用以製造包括具有凹陷區域的半導體基底的封裝元件的又一方法2200的工藝流程圖。方法2200一般包括其中在將一個或更多個裸片耦合到半導體基底之後形成一個或更多個過孔的技術。該方法可以與結合方法2000描述的相似實施方式相一致。
在2202，方法2200包括提供半導體基底。該基底包括第一表面和與第一表面相反佈置的第二表面。
在2204，方法2200還包括在半導體基底上形成再分佈層。可以使用如結合方法2000描述的類似技術來形成再分佈層。
在2206，方法2200還包括將一個或更多個裸片耦合到半導體基底。可以使用如結合方法2000描述的類似技術將該一個或更多個裸片耦合到基底。
在2208，方法2200還包括在半導體基底上形成模塑膠。可以使用如結合方法2000描述的類似技術來形成模塑膠。
在2210，方法2200還包括使半導體基底的表面凹陷。使與其上耦合一個或更多個裸片的表面相反的表面凹陷。也就是，如果一個或更多個裸片耦合到半導體基底的第一表面，則使第二表面凹陷。可以通過研磨工藝或蝕刻工藝使半導體基底凹陷，以提供厚度在約10微米和約500微米之間的凹陷區域。這種厚度可以有利於完全穿過半導體基底的一個或更多個過孔的形成。在其他實施方式中可以使用其他凹陷技術和厚度。根據各種實施方式，在凹陷期間將模塑膠用作機械載體以支撐半導體基底。
在2212，方法2200還包括形成通過半導體基底的一個或更多個過孔。可以使用如結合方法2000描述的類似技術來形成該一個或更多個過孔。
方法2200還可以包括2214處的在凹陷表面上形成再分佈層、2216處的將一個或更多個裸片耦合到凹陷表面、2218處的在凹陷表面上形成模塑膠、以及2220處的將一個或更多個封裝互連結構耦合到再分佈層。這些動作可以與結合方法2000的已描述相似動作相一致。
儘管本文已經圖示並描述了特定實施方式，但在不脫離本公開的範圍的情況下，為實現相同目的而計算的各種替代和/或等同實施方式或實現方案可以替代這裏所圖示和描述的實施方式。本公開旨在于覆蓋本文所討論的實施方式的任何修改或變化。因此，顯然本文所述的實施方式旨在僅由請求項及其等同含義限制。
100．．．封裝元件
102．．．半導體基底
104．．．區域
106．．．較厚區域
108．．．過孔
110．．．再分佈層
111．．．凸點
112．．．裸片
113．．．凹陷的區域
114．．．封裝互連結構
120．．．電介質襯墊
130．．．模塑膠
140．．．鍵合線
142．．．粘合劑
200．．．電子器件
250．．．電子器件
300．．．封裝元件
400．．．封裝元件
500．．．封裝元件
504．．．凹陷區域
600．．．封裝元件
700．．．封裝元件
800．．．封裝元件
900．．．封裝元件
960．．．延伸部分
1000．．．封裝元件
1100．．．封裝元件
1200．．．封裝元件
1300．．．封裝元件
1308．．．附加過孔
1400．．．封裝元件
1500．．．封裝元件
1504．．．附加凹陷區域
1600．．．封裝元件
1602．．．其他半導體基底
1700．．．封裝元件
1800．．．封裝元件
1900．．．封裝元件
A1．．．第一表面
A2．．．第二表面
T1,T2．．．厚度
通過下面的結合附圖的詳細描述，將易於理解本公開的實施方式。為了便於描述，相似的附圖標記表示相似的結構元件。通過示例而非通過說明書附圖中的圖中的限制來說明本文的實施方式。
圖1至圖19示意性地示出了各種示例封裝元件的配置，該封裝元件包括具有凹陷區域的半導體基底。
圖20是用於製造包括具有凹陷區域的半導體基底的封裝元件的方法的工藝流程圖。
圖21是用於製造包括具有凹陷區域的半導體基底的封裝元件的另一方法的工藝流程圖。
圖22是用於製造包括具有凹陷區域的半導體基底的封裝元件的又一方法的工藝流程圖。

Claims (48)

  1. 一種封裝裝置，包括：半導體基底，所述半導體基底具有第一表面，第二表面，與所述第一表面相反佈置，其中所述第一表面的至少一部分凹陷以形成所述半導體基底的凹陷區域，以及一個或更多個過孔，形成在所述半導體基底的凹陷區域中，以提供在所述半導體基底的第一表面和第二表面之間的電通路或熱通路；以及裸片，耦合到所述半導體基底，所述裸片電耦合到在所述半導體基底的凹陷區域中形成的所述一個或更多個過孔，其中所述第二表面的一部分凹陷以暴露所述一個或更多個過孔；以及其中所述一個或更多個過孔延伸到所述半導體基底的第二表面的凹陷部分之外，從而限定所述一個或更多個過孔的延伸部分。
  2. 如請求項1的封裝裝置，其中所述半導體基底的凹陷區域具有第一厚度，所述第一厚度小於所述凹陷區域外部的所述半導體基底的區域的第二厚度。
  3. 如請求項1的封裝裝置，其中： 所述裸片耦合到所述半導體基底的第一表面；所述裸片耦合到所述凹陷區域；以及所述裸片以倒裝晶片配置耦合到所述半導體基底。
  4. 如請求項3的封裝裝置，還包括：再分佈層，(i)所述再分佈層形成在所述半導體基底的第二表面上，並且(ii)所述再分佈層電耦合到所述一個或更多個過孔以路由所述裸片的電信號。
  5. 如請求項4的封裝裝置，還包括：一個或更多個封裝互連結構，(i)所述一個或更多個封裝互連結構耦合至所述半導體基底的第二表面，並且(ii)所述一個或更多個封裝互連結構電耦合到所述再分佈層以進一步路由所述裸片的電信號。
  6. 如請求項5的封裝裝置，其中所述一個或更多個封裝互連結構包括焊料球或金屬柱中的至少一種。
  7. 如請求項5的封裝裝置，其中：所述再分佈層是第一再分佈層；所述一個或更多個封裝互連結構是第一組封裝互連結構；以及所述封裝裝置還包括：第二再分佈層，(i)所述第二再分佈層形成在所述半導體基底的第一表面上，並且(ii)所述第二再分佈層電耦合到所述一個或更多過孔以進一步路由所述裸片的電信號；以及 第二組封裝互連結構，(i)所述第二組封裝互連結構耦合到所述半導體基底的第一表面，並且(ii)所述第二組封裝互連結構電耦合到所述第二再分佈層以進一步路由所述裸片的電信號。
  8. 如請求項5的封裝裝置，其中所述裸片是第一裸片，所述封裝裝置還包括：第二裸片，所述第二裸片以倒裝晶片配置耦合到(i)所述凹陷區域以及(ii)所述半導體基底的第一表面，所述第二裸片電耦合到所述一個或更多個過孔。
  9. 如請求項5的封裝裝置，其中所述裸片是第一裸片，所述封裝裝置還包括：第二裸片，所述第二裸片以倒裝晶片配置耦合到(i)所述凹陷區域以及(ii)所述半導體基底的第二表面，所述第二裸片電耦合到所述一個或更多個過孔。
  10. 如請求項5的封裝裝置，還包括：印刷電路板，所述印刷電路板使用所述一個或更多個封裝互連結構耦合到所述半導體基底。
  11. 如請求項5的封裝裝置，其中所述半導體基底是第一半導體基底，所述封裝裝置還包括：第二半導體基底，所述第二半導體基底使用所述一個或更多個封裝互連結構耦合到所述第一半導體基底。
  12. 如請求項2的封裝裝置，其中所述凹陷區域是通過使 所述第一表面的第一部分凹陷形成的第一凹陷區域，所述封裝裝置還包括：所述半導體基底的一個或更多個第二凹陷區域，所述半導體基底的所述一個或更多個第二凹陷區域是通過使所述第一表面的一個或更多個第二部分凹陷而形成的，其中所述半導體基底的具有所述第二厚度的區域佈置在所述第一凹陷區域與所述一個或更多個第二凹陷區域之間。
  13. 如請求項12的封裝裝置，其中所述一個或更多個過孔是一個或更多個第一過孔，所述封裝裝置還包括：一個或更多個第二過孔，所述一個或更多個第二過孔形成在所述一個或更多個第二凹陷區域中，以提供在所述半導體基底的第一表面和第二表面之間的電通路。
  14. 如請求項13的封裝裝置，還包括：再分佈層，形成在所述半導體基底的第二表面上，所述再分佈層電耦合到(i)所述一個或更多個第一過孔以及(ii)所述一個或更多個第二過孔，以路由所述裸片的電信號；以及一個或更多個封裝互連結構，(i)耦合到所述一個或更多個第二凹陷區域以及(ii)所述半導體基底的第一表面，所述一個或更多個封裝互連結構使用所述一個或更多個第二過孔而電耦合到所述裸片。
  15. 如請求項1的封裝裝置，其中：所述裸片耦合到所述半導體基底的第二表面； 所述裸片耦合到所述凹陷區域；以及所述裸片以倒裝晶片配置耦合到所述半導體基底。
  16. 如請求項1的封裝裝置，還包括：電介質膜，所述電介質膜佈置在所述一個或更多個過孔的延伸部分的至少一部分上，其中所述裸片電耦合到所述一個或更多個過孔的延伸部分。
  17. 如請求項2的封裝裝置，其中所述裸片耦合到所述半導體基底的具有所述第二厚度的區域。
  18. 如請求項17的封裝裝置，其中所述一個或更多個過孔包括一個或更多個第一過孔，所述封裝裝置還包括：一個或更多個第二過孔，形成在所述半導體基底的具有所述第二厚度的區域中，其中所述一個或更多個第二過孔僅佈置在所述半導體基底的(i)第一表面和(ii)第二表面中的一個表面上。
  19. 如請求項1的封裝裝置，其中所述凹陷區域是第一凹陷區域，所述封裝裝置還包括：第二凹陷區域，所述第二凹陷區域是通過使所述半導體基底的第二表面的至少一部分凹陷而形成的。
  20. 如請求項19的封裝裝置，其中：所述一個或更多個過孔是一個或更多個第一過孔；以及所述第二凹陷區域包括在其中形成的一個或更多個第二過孔，以提供在所述半導體基底的第一表面和第二表面之間的電 通路或熱通路。
  21. 如請求項19的封裝裝置，其中所述半導體基底是第一半導體基底並且所述裸片是第一裸片，所述封裝裝置還包括：第二半導體基底，所述第二半導體基底具有第三表面，其中所述第三表面的至少一部分凹陷以形成第三凹陷區域，第四表面，與所述第三表面相反佈置，其中所述第四表面的至少一部分凹陷以形成第四凹陷區域，和一個或更多個過孔，形成在所述第三凹陷區域中以提供在所述第二半導體基底的第三表面和第四表面之間的電通路或熱通路；以及第二裸片，耦合到所述第二半導體基底，所述第二裸片電耦合到在所述第二半導體基底中形成的所述一個或更多個過孔，其中所述第二半導體基底的第四表面耦合到所述第一半導體基底的第二表面。
  22. 如請求項1的封裝裝置，還包括：模塑膠，佈置在所述半導體基底的(i)第一表面和(ii)第二表面的至少一個表面上，所述模塑膠還佈置為實質上包封所述裸片。
  23. 如請求項1的封裝裝置，其中：所述半導體基底包括矽；所述裸片包括矽；以及 所述一個或更多個過孔包括矽貫通孔(TSV)。
  24. 如請求項1的封裝裝置，其中所述半導體基底凹陷使得所述凹陷區域具有在10微米和500微米之間的厚度。
  25. 一種封裝方法，包括：提供半導體基底，所述半導體基底具有(i)第一表面和(ii)與所述第一表面相反佈置的第二表面；使所述第一表面的至少一部分凹陷，以形成所述半導體基底的凹陷區域；在所述半導體基底的凹陷區域中形成一個或更多個過孔，以提供在所述半導體基底的第一表面和第二表面之間的電通路或熱通路；將裸片耦合到所述半導體基底，所述裸片電耦合到在所述半導體基底的凹陷區域中形成的所述一個或更多個過孔；以及使所述第二表面的一部分凹陷以暴露所述一個或更多個過孔，使得所述一個或更多個過孔延伸到所述半導體基底的第二表面的凹陷部分之外，使所述第二表面的一部分凹陷限定了所述一個或更多個過孔的延伸部分。
  26. 如請求項25的封裝方法，其中：所提供的半導體基底包括矽；耦合到所述半導體基底的所述裸片包括矽；以及在所述凹陷區域中形成的所述一個或更多個過孔包括矽貫通孔(TSV)。
  27. 如請求項25的封裝方法，其中使用蝕刻工藝去除所述半導體基底的半導體材料，由此使所述第一表面的所述部分凹陷。
  28. 如請求項25的封裝方法，其中所述一個或更多個過孔通過以下步驟來形成：使用蝕刻工藝或鐳射鑽孔工藝從所述凹陷區域去除半導體材料，以形成通過所述半導體基底的一個或更多個通道；在所述一個或更多個通道的表面上形成電介質膜；以及將導電材料和/或導熱材料沉積到所述一個或更多個通道中。
  29. 如請求項25的封裝方法，其中所述半導體基底的凹陷區域具有第一厚度，所述第一厚度小於所述凹陷區域外部的所述半導體基底的區域的第二厚度。
  30. 如請求項25的封裝方法，其中：將所述裸片耦合到所述半導體基底的第一表面；將所述裸片耦合到所述凹陷區域；以及將所述裸片以倒裝晶片配置耦合到所述半導體基底。
  31. 如請求項30的封裝方法，還包括：在所述半導體基底的第二表面上形成再分佈層，所述再分佈層電耦合到所述一個或更多個過孔以路由所述裸片的電信號。
  32. 如請求項31的封裝方法，還包括： 將一個或更多個封裝互連結構耦合到所述半導體基底的第二表面，所述一個或更多個封裝互連結構電耦合到所述再分佈層以進一步路由所述裸片的電信號。
  33. 如請求項32的封裝方法，其中通過在所述再分佈層上形成(i)焊料球和(ii)金屬柱中的至少一種，而將所述一個或更多個封裝互連結構耦合到所述第二表面。
  34. 如請求項33的封裝方法，其中所述再分佈層是第一再分佈層，並且所述一個或更多個封裝互連結構是第一組封裝互連結構，所述封裝方法還包括：在所述半導體基底的第一表面上形成第二再分佈層，所述第二再分佈層電耦合到所述一個或更多個過孔以進一步路由所述裸片的電信號；以及將第二組封裝互連結構耦合到所述半導體基底的第一表面，所述第二組封裝互連結構電耦合到所述第二再分佈層以進一步路由所述裸片的電信號。
  35. 如請求項32的封裝方法，其中所述裸片是第一裸片，所述封裝方法還包括：將第二裸片以倒裝晶片配置耦合到(i)所述凹陷區域以及(ii)所述半導體基底的第一表面，所述第二裸片電耦合到所述一個或更多個過孔。
  36. 如請求項32的封裝方法，其中所述裸片是第一裸片，所述封裝方法還包括： 將第二裸片以倒裝晶片配置耦合到所述半導體基底的第二表面，所述第二裸片電耦合到所述一個或更多個過孔。
  37. 如請求項32的封裝方法，還包括：使用所述一個或更多個封裝互連結構將印刷電路板耦合到所述半導體基底。
  38. 如請求項32的封裝方法，其中所述半導體基底是第一半導體基底，所述封裝方法還包括：使用所述一個或更多個封裝互連結構來將第二半導體基底耦合到所述第一半導體基底。
  39. 如請求項29的封裝方法，其中所述凹陷區域是通過使所述第一表面的第一部分凹陷而形成的第一凹陷區域，所述封裝方法還包括：通過使所述第一表面的一個或更多個第二部分凹陷，形成所述半導體基底的一個或更多個第二凹陷區域，其中所述半導體基底的具有所述第二厚度的區域佈置在所述第一凹陷區域和所述一個或更多個第二凹陷區域之間。
  40. 如請求項39的封裝方法，其中所述一個或更多個過孔是一個或更多個第一過孔，所述封裝方法還包括：在所述一個或更多個第二凹陷區域中形成一個或更多個第二過孔，以提供在所述半導體基底的第一表面和第二表面之間的電通路。
  41. 如請求項40的封裝方法，還包括： 在所述半導體基底的第二表面上形成再分佈層，所述再分佈層電耦合到(i)所述一個或更多個第一過孔以及(ii)所述一個或更多個第二過孔以路由所述裸片的電信號；以及將一個或更多個封裝互連結構耦合到(i)所述半導體基底的第一表面以及(ii)所述一個或更多個第二凹陷區域，其中使用一個或更多個第二過孔來將所述一個或更多個封裝互連結構電耦合到所述裸片。
  42. 如請求項25的封裝方法，其中：將所述裸片耦合到所述半導體基底的第二表面；將所述裸片耦合到所述凹陷區域；以及將所述裸片以倒裝晶片配置耦合到所述半導體基底。
  43. 如請求項25的封裝方法，還包括：在使所述第二表面的所述部分凹陷以暴露所述一個或更多個過孔之前，在所述一個或更多個過孔的延伸部分的至少一部分上形成電介質襯墊，並且其中在使所述第二表面的部分凹陷期間所述電介質襯墊保護所述一個或者多個過孔，以及其中所述裸片電耦合到所述一個或更多個過孔的延伸部分。
  44. 如請求項29的封裝方法，其中所述裸片耦合到所述半導體基底的具有所述第二厚度的區域。
  45. 如請求項44的封裝方法，其中所述一個或更多個過孔包括一個或更多個第一過孔，所述封裝方法還包括：在所述半導體裸片的具有所述第二厚度的區域中形成一個 或更多個第二過孔，其中所述一個或更多個第二過孔僅佈置在所述半導體基底的(i)第一表面和(ii)第二表面中的一個表面上。
  46. 如請求項25的封裝方法，其中所述凹陷區域是第一凹陷區域，所述封裝方法還包括：通過使所述半導體基底的第二表面的至少一部分凹陷來形成第二凹陷區域。
  47. 如請求項46的封裝方法，其中所述一個或更多個過孔是一個或更多個第一過孔，所述封裝方法還包括：在所述第二凹陷區域中形成一個或更多個第二過孔，以提供在所述半導體基底的第一表面和第二表面之間的電通路或熱通路。
  48. 如請求項25的封裝方法，還包括：在所述半導體基底的(i)第一表面和(ii)第二表面中的至少一個表面上形成模塑膠，所述模塑膠布置為實質上包封所述裸片。
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