TW201608653A - 製造半導體封裝體的方法 - Google Patents

製造半導體封裝體的方法 Download PDF

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TW201608653A
TW201608653A TW104114915A TW104114915A TW201608653A TW 201608653 A TW201608653 A TW 201608653A TW 104114915 A TW104114915 A TW 104114915A TW 104114915 A TW104114915 A TW 104114915A TW 201608653 A TW201608653 A TW 201608653A
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Taiwan
Prior art keywords
die
substrate
molding compound
thickness
molding material
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TW104114915A
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黃文濬
李建成
劉國洲
薛瑞雲
鄭錫圭
林志賢
林俊成
陸湘台
謝子逸
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台灣積體電路製造股份有限公司
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Publication of TW201608653A publication Critical patent/TW201608653A/zh

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Abstract

本揭露的實施例包含半導體封裝體及其製造方法。一實施例為方法，包含安裝一晶粒至一基板的頂表面，以形成一元件，密封晶粒及基板的頂表面於一模塑化合物內，此模塑化合物於晶粒上具有一第一厚度，以及移除模塑化合物於晶粒上的厚度的一部分，而非全部。此方法更包含對元件進行進一步的處理，以及移除模塑化合物於晶粒上的剩餘厚度。

Description

製造半導體封裝體的方法
本發明係有關於一種半導體封裝體及其製造方法。
半導體元件被廣泛使用在各種電子應用中，例如個人電腦、手機、數位相機和其他電子設備。半導體元件典型地藉由依序沉積絕緣或介電層、導電層和材料的半導體層於半導體基板上，使用微影製程圖案化各種材料層，以形成電路部件和元件於其上方。
半導體元件經歷了快速發展，是因為不斷改進各種電子部件(例如電晶體、二極體、電阻、電容等)的集成密度。在大多數的情況下，集成密度的改善是來自於縮小半導體製程的節點(例如將半導體製程的節點往次20奈米的節點縮小)。近期對於更高速、更寬廣的帶寬及更低的功耗與延遲之微型化的要求成長，使得對於更小及更具創意的半導體晶粒的封裝技術的需求成長。
一實施例為方法，包含安裝晶粒至基板的頂表面，以形成元件，密封晶粒及基板的頂表面於模塑化合物內，此模塑化合物於晶粒上具有第一厚度，以及移除模塑化合物於晶粒上的厚度的一部分，而非全部。此方法更包含對元件進行進一步的處理，以及移除模塑化合物於晶粒上的剩餘厚度。
另一實施例為方法，包含將第一晶粒的活性表面附著至第一基板的第一側，以形成晶粒封裝體，以模塑材料密封第一晶粒及基板的第一側，模塑材料具有第一厚度自模塑材料的第一表面至第一晶粒的背表面，背表面相對活性表面，以及對模塑材料的第一表面進行第一平坦化步驟，以具有第二厚度自模塑材料的第一表面至第一晶粒的背表面，第二厚度小於第一厚度。本方法更包含將模塑材料的第一表面附著至載板，形成電連接器於第一基板的第二側上方，移除載板，以及對模塑材料的第一表面進行第二平坦化步驟，以移除於第一晶粒的背表面上方的剩餘模塑材料。
又一實施例為方法，包含將晶粒附著至第一基板的第一表面，以形成元件封裝體，以模塑化合物密封晶粒及第一基板的第一表面，模塑化合物延伸至晶粒上方，以及移除模塑化合物延伸至晶粒上方的一部分。本方法更包含對元件封裝體進行進一步的處理，以及移除模塑化合物位於晶粒上方的剩餘部分，以暴露晶粒的表面。
102、202、602‧‧‧基板
102A‧‧‧活性表面
106、208‧‧‧互連結構
108、606‧‧‧接合墊、下凸塊金屬化體
110‧‧‧晶粒
110A‧‧‧背表面
202A‧‧‧活性表面、第一表面
202B‧‧‧第二表面
206‧‧‧導通孔
210、408、604‧‧‧電連接器
302、608‧‧‧底部填充膠
304‧‧‧模塑材料
304A‧‧‧表面
402‧‧‧載板
404‧‧‧介電層
406‧‧‧金屬化圖案
420‧‧‧保護膜
502‧‧‧散熱器
702、704、706、708、710、712、714、716、718‧‧‧步驟
T1‧‧‧厚度
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1-10圖繪示根據本發明一些實施例之形成封裝體的中間階段的剖面示意圖。
第11圖繪示根據本發明一些實施例之形成封裝體的流程圖。
以下提供本發明之多種不同的實施例或實例，以實現所提供之標的的不同技術特徵。下述具體實例的元件和設計用以簡化本發明。當然，這些僅為示例，而非用以限定本發明。舉例而言，說明書中揭示形成第一特徵結構於第二特徵結構之上方，其包括第一特徵結構與第二特徵結構形成而直接接觸的實施例，亦包括於第一特徵結構與第二特徵結構之間另有其他特徵結構的實施例，使得第一特徵結構與第二特徵結構並非直接接觸。此外，本發明於各個實例中可能用到重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述結構之間的關係。
另外，空間相對用語，如「下」、「上」等，是用以方便描述一元件或特徵與其他元件或特徵在圖式中的相對關係。這些空間相對用語旨在包含除了圖式中所示之方位以外，裝置在使用或操作時的不同方位。裝置可被另外 定位(例如旋轉90度或其他方位)，而本文所使用的空間相對敘述亦可相對應地進行解釋。
以下將描述特定的上下文的實施例，也就是晶粒插入基板(Die-Interposer-Substrate)堆疊封裝體，使用晶片上晶圓上基板(Chip-on-Wafer-on-Substrate,CoWoS)處理。然而，也可應用其他實施例至其他封裝體，如晶粒-晶粒-基板(Die-Die-Substrate)堆疊封裝體，以及其他處理。
概括地說，本揭露的實施例可提供一種改進的方式，以減少或最小化或完全消除在製造過程中的靜電(electrostatic discharge,ESD)，例如C4(控制塌陷晶片連接)製程。如此一來，能夠擴大製造晶片上晶圓上基板元件的製程窗口，減少製程成本及製程複雜性，同時提昇製程良率。
儘管在製造環境中，不能完全消除靜電，但可以減少其影響。在一方式中，如本文所述，為了在C4凸塊製程時，維持位於晶粒(例如晶粒的背表面)上的隔離層。這可減少或消除靜電能到達及損害敏感元件的路徑。
第1-10圖繪示根據本發明一些實施例之形成封裝體的中間階段的剖面示意圖，而第11圖繪示根據本發明一些實施例之第1至10圖的製程步驟的流程圖。
第1圖繪示形成一或多個晶粒110(步驟702)。在製程中，基板102包含一或多個晶粒110。基板102包含互連結構106位於活性表面102A上，並附有多個接合墊108 形成於互連結構106內和/或於互連結構106上。
基板102可由半導體材料，如矽、鍺、鑽石或其類似物。可替代地，也可以使用化合物材料，如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合及其類似物。此外，基板102可為矽上絕緣體(silicon-on-insulator,SOI)基板。一般而言，矽上絕緣體基板包括一層半導體材料，例如磊晶矽、鍺、矽鍺、矽上絕緣體、矽鍺上絕緣體(silicon germanium on insulator,SGOI)或其組合。
基板102可包含主動和被動元件(第1圖未繪示)。如本技術領域之其中一通常知識者將瞭解的，可使用各式各樣的元件，例如電晶體、電容器、電阻器、其組合與其類似物，產生對於一或多個晶粒110在結構及功能上的設計需求。可使用任何合適的的方法形成元件。
互連結構106包含一或多個介電層與相應的金屬化圖案形成於活性表面202A上。於介電層內的金屬化圖案可在元件之間傳送電子訊號，例如使用通孔和/或走線，且亦可含有各種電子元件，例如電容器、電阻器、電感器或其類似物。各種元件與金屬化圖案可相互連接，以執行一或多個功能。這些功能可包含存儲器結構、處理結構、感測器、放大器、功率分配、輸入/輸出電路或其類似物。
一或多個層間金屬介電(inter-metallization dielectric,IMD)層形成於互連結構208內，舉例而言，低介電常數材料，如磷矽酸鹽玻璃(PSG)、硼磷矽玻璃 (BPSG)、氟矽酸鹽玻璃(FSG)、SiOxCy、旋塗玻璃、旋塗高分子、碳化矽材料、其化合物、其複合物、其組合或其類似物，藉由在本領域中已知的任何合適的方法形成，例如紡絲、化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、高密度電漿化學氣相沉積(HDP-CVD)或其類似物。金屬化圖案可形成在層間金屬介電層內，例如，透過使用微影技術沉積與圖案化在層間金屬介電層上的光阻材料，以暴露出層間金屬介電層的多個部分，這些部分會成為金屬化圖案。蝕刻製程，例如異向性乾蝕刻製程，可用於製造層間金屬介電層內的凹部和/或開口對應層間金屬介電層的露出部分。這些凹部和/或開口可襯有擴散阻障層及以導電材料填充之。擴散阻障層可包括一或多層的氮化鉭、鉭、氮化鈦、鈦、鎢化鈷或其類似物，藉由原子層沉積(ALD)或其類似物進行沉積，導電材料可包括銅、鋁、鎢、銀、其組合或其類似物，藉由化學氣相沉積(CVD)、物理氣相沉積(PVD)或其類似物進行沉積。可以移除在層間金屬介電層上的任何過多的擴散阻障層和/或導電材料，例如透過使用化學機械拋光(CMP)進行移除。
接合墊108形成在互連結構106內和/或互連結構106上。在一些實施例中，藉由形成凹部(未繪示)於互連結構106的一或多個介電層內，形成接合墊108。可形成凹部，以讓接合墊108可以嵌入互連結構106。在其他實施例中，可省略凹部，接合墊108形成在互連結構106的上方。接合墊108電性和/或物理耦接一或多個晶粒110至隨後接 合的基板202(見第4圖)。在一些實施例中，接合墊108包含一薄種晶層(未繪示)，係由銅、鈦、鎳、金、其類似物或其組合所製成。接合墊108的導電材料可沉積在薄種晶層上。導電材料可藉由電化學鍍製程、化學氣相沉積、原子層沉積、物理氣相沉積、其類似物或其組合形成。在一實施例中，接合墊108的導電材料為銅、鎢、鋁、銀、金、其類似物或其組合。
在一實施例中，接合墊108是下凸塊金屬化體(underbump metallizations,UBMs)，其包含三層導電材料，例如一鈦層、一銅層及一鎳層。然而，所屬技術領域之其中一通常知識者將瞭解這些層的材料為多種合適的材料與層的排列，例如鉻/鉻-金合金/銅/金排列、鈦/鈦鎢/銅排列或銅/鎳/金排列，其適合形成下凸塊金屬化體108。可用在下凸塊金屬化體108的任何合適的材料或材料層完全意旨包含於本申請的範圍內。
在第2圖中，單片化包含互連結構106的基板102，而形成單獨的多個晶粒110(步驟704)。通常，多個晶粒110含有相同的電路，例如元件和金屬化圖案，雖然多個晶粒110可具有不同的電路。在一些實施例中，單片化透過鋸切、雷射、劃片、其類似物或其組合進行。
第3圖繪示基板202的第一側的形成(步驟706)。基板202可由半導體材料製成，如矽、鍺、鑽石或其類似物。可替代地，也可以使用化合物材料，如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷 化鎵銦、其組合及其類似物。此外，基板202可為矽上絕緣體基板。一般而言，矽上絕緣體基板包括一層半導體材料，例如磊晶矽、鍺、矽鍺、矽上絕緣體、矽鍺上絕緣體或其組合。在一替代實施例中，基板202是基於一絕緣芯，例如玻璃纖維補強樹脂芯。芯材料的一示例為玻璃纖維樹脂，例如FR4。替代的芯材料包含雙馬來醯亞胺三嗪(bismaleimide-triazine,BT)樹脂，或者替代地，其他PC板材料或薄膜。建構的膜層如味之素建構膜(Akinomoto build-up film,ABF)或其他層壓板，可使用於基板202。
基板202可包含主動和被動元件(未繪示於第3圖)。如本技術領域之其中一通常知識者將瞭解的，可使用各式各樣的元件，例如電晶體、電容器、電阻器、其組合與其類似物，產生對於基板202在結構及功能上的設計需求。可使用任何合適的的方法形成元件。在一些實施例中，基板202是內插件，其通常不包含主動元件於其中，雖然內插件可包含被動元件形成於第一表面202A內和/或第一表面202A上。
導通孔(through-vias,TVs)206形成自基板202的第一表面202A延伸至基板202內。導通孔206亦有時稱為貫基板孔或貫矽孔，當基板202A為矽基板時。導通孔206可藉由形成凹部於基板202內而形成，例如藉由蝕刻、銑削、雷射技術、其類似物或其組合。可共形沉積薄阻障層於基板202的前側上方及開口內，例如藉由化學氣相沉積、 原子層沉積、物理氣相沉積、熱氧化、其類似物或其組合。阻障層可包含氮化物或氮氧化物，例如氮化鈦、氮氧化鈦、氮化鉭、氮化鎢、其類似物或其組合。可沉積導電材料於薄阻障層的上方及開口內。導電材料可藉由電化學鍍製程、化學氣相沉積、原子層沉積、物理氣相沉積、其類似物或其組合形成。導電材料的示例為銅、鎢、鋁、銀、金、其類似物或其組合。過多的導電材料及阻障層可自基板202的前側移除，例如透過化學機械拋光。因此，導通孔206可包含導電材料與薄阻障層位於導電材料與基板202之間。
互連結構208形成於基板202的第一表面202A的上方，其可用以電性連接積體電路元件，如果任何和/或導通孔206一起和/或至外部元件。互連結構208可包含一或多層介電層與位於介電層內的相應的金屬化圖案。金屬化圖案可包含通孔和/或走線，以與任何元件和/或導通孔206一起互連至外部元件。金屬化圖案有時被稱為重佈線(Redistribution Lines,RDLs)。介電層可包含氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數材料，例如磷矽酸鹽玻璃、硼磷矽玻璃、氟矽酸鹽玻璃、SiOxCy、旋塗玻璃、旋塗高分子、碳化矽材料、其化合物、其複合物、其組合或其類似物。藉由在本領域中已知的任何合適的方法沉積介電層，例如紡絲、化學氣相沉積、電漿增強化學氣相沉積、高密度電漿化學氣相沉積或其類似物。可形成金屬化圖案於介電層內，例如，透過使用微影技術沉積與圖案化在介電層上的光阻材料，以暴露出介電層的多個部分，這些部分會成為 金屬化圖案。蝕刻製程，例如異向性乾蝕刻製程，可用於製造介電層內的凹部和/或開口對應介電層的露出部分。這些凹部和/或開口可襯有擴散阻障層及以導電材料填充之。擴散阻障層可包括一或多層的氮化鉭、鉭、氮化鈦、鈦、鎢化鈷或其類似物，藉由原子層沉積或其類似物進行沉積，導電材料可包括銅、鋁、鎢、銀、其組合或其類似物，藉由化學氣相沉積、物理氣相沉積或其類似物進行沉積。在介電層上的任何過多的擴散阻障層和/或導電材料可以被移除，例如透過使用化學機械拋光進行移除。
電連接器210形成於互連結構208的頂表面且電性耦接互連結構208。電連接器210可為焊球、金屬柱、控制塌陷晶片連接(C4)凸塊、微凸塊、化學鍍鎳-化學鍍鈀-浸金(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)技術所形成的凸塊或其類似物。電連接器210可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似物或其組合。在電連接器210為焊球的一實施例中，電連接器210透過一般使用的方法，例如蒸鍍、電鍍、印刷、焊料轉移、焊球置放或其類似物，先形成焊料層。一旦焊料層已形成在結構上，可進行回焊，以塑造材料成為所需的凸塊形狀。在其他實施例中，電連接器210為金屬柱(例如銅柱)，藉由濺鍍、印刷、電鍍、化學鍍、化學氣相沉積或其類似物形成。金屬柱可不含焊料，且具有大致垂直的多個側壁。在一些實施例中，金屬蓋層(未繪示)形成於金屬柱連接器210的頂 端上。金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、其類似物或其組合，且可透過電鍍製程形成。
第4圖繪示將晶粒110附著至第一基板的第一側(步驟708)，例如透過倒裝晶片接合，以形成晶粒封裝體。電連接器210電性耦接在晶粒110內的電路至互連結構208與導通孔206。
晶粒110可包含邏輯晶粒，例如中央處理單元(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、其類似物或其組合。在一些實施例中，晶粒110包含晶粒堆疊(未繪示)，其可包含邏輯晶粒與儲存晶粒。晶粒110可包含輸入/輸出(input/output,I/O)晶粒，例如寬I/O晶粒。
晶粒110與互連結構208之間的接合可為焊料接合或直接金屬對金屬(例如銅對銅或錫對錫)接合。在一實施例中，藉由回焊製程，接合晶粒110至互連結構208。在此回焊製程時，電連接器210接觸接合墊108及互連結構208，以物理及電性耦接晶粒110至互連結構208。
底部填充膠302可被注入或以其他方式形成在晶粒110與互連結構208之間的空間，並圍繞電連接器210。底部填充膠302可例如為液態環氧樹脂、可變形的凝膠、矽橡膠或其類似物，其被分配在結構之間，然後固化變硬。此底部填充膠的材料，除了其他方面以外，用以減少對電連接器210的損害，並保護電連接器210。
在將晶粒110附著至基板202之後，密封晶粒110(步驟710)。在一些實施例中，晶粒110藉由模塑材料304進行密封。模塑材料304可成型於晶粒110上，例如使用壓縮成型。在一些實施例中，模塑材料304由模塑化合物、高分子、環氧樹脂、氧化矽填充材料、其類似物或其組合製成。可對模塑材料304進行固化步驟，其中固化可為熱固化、紫外光固化、其類似物或其組合。
在一些實施例中，晶粒110被埋在模塑材料304中，且在固化模塑材料304之後，對模塑材料304進行第一平坦化製程(步驟712)，如第5圖所示。在一實施例中，第一平坦化製程為磨削製程，雖然也可使用其他技術，包含蝕刻、雷射燒蝕、拋光和其類似物。第一平坦化製程用以平坦化模塑材料304，以提供模塑材料304的大致平坦的頂表面304A。第一平坦化製程移除在晶粒110上方的模塑材料304的一些，而非全部，使得晶粒110的背表面110A仍然被埋在模塑材料304之中。在一實施例中，模塑材料304位於晶粒110的背表面110A上的剩餘量具有一厚度T1大於約30微米，例如為約30微米至約50微米。
厚度T1為模塑材料304足夠阻擋晶粒110與載板402之間的靜電放電路徑的厚度，並允許模塑材料304可進行重工，卻不暴露出晶粒110。舉例而言，在第一平坦化製程之後，可能會發現在模塑材料304上的缺陷，而需要進行重工製程，例如磨削製程，以去除缺陷。透過位於晶粒110的背表面110A上，具有至少30微米的模塑材料304，在重 工時，晶粒110的背表面110A將不會暴露出來，因此，其將持續被模塑材料304保護。
第6圖繪示翻轉晶粒封裝體，且接著模塑材料304的表面304A至載板402上，以允許形成基板202的第二側。載板402可為任何合適的基板，其提供(在製造過程的中間步驟)位於載板402上的部件及結構的機械支撐。此載板402可為一晶圓，包含玻璃、石英、矽(例如矽晶圓)、氧化矽、金屬板、陶瓷材料或其類似物。
在第二側的形成中，對基板202的第二側進行薄化製程，以薄化基板202至第二表面202B，直至導通孔206暴露出。在一實施例中，薄化製程為磨削製程，雖然也可使用其他技術，包含蝕刻、雷射燒蝕、拋光和其類似物。介電層404形成在基板202的第二表面202B上。可形成金屬化圖案406在第二表面202B上及介電層404內，使用上述類似的製程形成。
電連接器408亦形成於基板202的第二側上，並電性耦接導通孔206。在一些實施例中，電連接器408為焊球、金屬柱、C4凸塊、微凸塊、化學鍍鎳-化學鍍鈀-浸金技術所形成的凸塊或其類似物。電連接器408可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似物或其組合。在其他實施例中，電連接器408為金屬柱(例如銅柱)，藉由濺鍍、印刷、電鍍、化學鍍、化學氣相沉積或其類似物形成。金屬柱可不含焊料，且具有大致垂直的多個側壁。在一些實施例中，金屬蓋層(未繪示)形成於金屬柱連 接器408的頂端上。金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、其類似物或其組合，且可透過電鍍製程形成。可使用電連接器408接合至額外的電性部件，其可為半導體基板、封裝基板、印刷電路板(printed circuit board,PCB)或其類似物。
在形成基板202的第二側(例如形成介電層404、金屬化圖案406和/或電連接器408)時，晶粒110、基板202與電連接器408可成為帶正電的，同時載板402可成為帶負電的，反之亦然。因此，晶粒110與載板402之間的界面可以是靜電放電的路徑。靜電能量的放電可損害在晶粒110與基板202內和/或晶粒110與基板202上的元件。透過留下一含量的模塑材料304覆蓋晶粒110的背表面110A，模塑材料304形成隔離層，其可阻擋晶粒110與載板402之間的靜電放電路徑。載板402與晶粒110的背表面110A藉由具有厚度T1的模塑材料304隔離，厚度T1為足夠阻擋晶粒110與載板402之間的靜電放電路徑的厚度。
第7圖繪示施加一保護膜420至基板202的第二側上(步驟714)，及移除載板402。保護膜420可為膠帶，例如背磨削(backgrinding,BG)膠帶(紫外光或非紫外光型)，其可用以保護基板202的第二側不受隨後模塑材料平坦化製程時產生的磨削碎片的損害(見第8圖)。保護膜420可使用例如滾輪(未繪示)，施加在基板202的第二側的上方。保護膜420可具有足夠的厚度，以完全覆蓋電連接器408，如第7圖所示。
第8圖繪示對模塑材料304進行第二平坦化製程(步驟716)。在一實施例中，第二平坦化製程為磨削製程，雖然也可使用其他技術，包含蝕刻、雷射燒蝕、拋光和其類似物。第二平坦化製程可用以移除模塑材料304的多餘部分，此多餘部分位於晶粒110的背表面110A的上方。在一些實施例中，暴露出晶粒110的背表面110A，且與模塑材料304的表面304A齊平。
在一些實施例中，在第二平坦化製程之後，晶粒110可具有一厚度，自活性表面102A至背表面110A，為約2.2微米，相較於未使用上述兩步驟模塑材料平坦化製程的晶粒，其厚度通常為約1.05微米。本揭露的實施例的其他方面是在進行上述製程時，模塑材料304的表面304A的粗糙度差異。舉例而言，在一些實施例中，觀察到的粗糙度為約1微米至約3微米，相對於不使用製程時，粗糙度為約0微米至約1微米。晶粒110的厚度差異與模塑材料304的表面粗糙度的差異至少歸因於進行第二模塑材料平坦化製程(見上述步驟716)，同時，保護膜420位於晶粒封裝體的對側的上方(例如位於基板202的第二側的上方)，因為保護膜420比基板202A軟，其在第一模塑材料平坦化製程時(見上述步驟712)位於晶粒封裝體的對側的上方。因此，較軟的保護膜420可壓縮與吸收在第二模塑材料平坦化製程時被施加的一些壓力，其可能會導致第二模塑材料製程消耗較少的晶粒110的背表面110A，並增加模塑材料304的表面304A的粗糙度。
第9圖繪示移除保護膜420及將選擇性的散熱器502附著至晶粒110的背表面110A與模塑材料304的表面304A。散熱器502可藉由黏合膜(未繪示)接著至晶粒110及模塑材料304。可施加黏合膜至散熱器502或晶粒110的背表面110A與模塑材料304的表面304A，以具有一厚度，使其不那麼厚而抑制散熱。黏合膜可為環氧樹脂、樹脂、其類似物或其混合物。散熱器502可為金屬板。用於金屬板的示例材料為銅、鎳鍍銅、鋁、其類似物或其組合。散熱器502通常可具有良好的導熱性和/或熱膨脹係數(coefficient of thermal expansion,CTE)，相較於晶粒110的熱膨脹係數。散熱器502通常在完成封裝時散出熱能。
第10圖繪示將晶粒封裝體附著至基板602(步驟718)。基板602可由半導體材料製成，如矽、鍺、鑽石或其類似物。可替代地，也可以使用化合物材料，如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合及其類似物。此外，基板602可為矽上絕緣體基板。一般而言，矽上絕緣體基板包括一層半導體材料，例如磊晶矽、鍺、矽鍺、矽上絕緣體、矽鍺上絕緣體或其組合。在一替代實施例中，基板202是基於一絕緣芯，例如玻璃纖維補強樹脂芯。芯材料的一例為玻璃纖維樹脂，例如FR4。替代的芯材料包含雙馬來醯亞胺三嗪樹脂，或替代地，其他PC板材料或薄膜。建構的膜層如味之素建構膜或其他層壓板，可使用於基板602。
基板602可包含主動和被動元件(第10圖未繪示)。如本技術領域之其中一通常知識者將瞭解的，可使用各式各樣的元件，例如電晶體、電容器、電阻器、其組合與其類似物，產生對於基板602在結構及功能上的設計需求。可使用任何合適的的方法形成元件。在一些實施例中，基板602是封裝基板。
基板602包含接合墊606位於基板602的第一側上及電連接器604位於基板的第二側，第二側相對於第一側。接合墊606與電連接器604可分別類似於上述的接合墊108與電連接器408，因而在此不重複敘述，雖然接合墊108,606及電連接器408,604不需為相同的。
晶粒封裝體與基板602之間的接合可為焊料接合或直接金屬對金屬(例如銅對銅或錫對錫)接合。在一實施例中，藉由回焊製程，接合晶粒封裝體至基板602。在此回焊製程時，電連接器408接觸金屬化圖案406及接合墊606，以物理及電性耦接晶粒封裝體至基板602。
底部填充膠608可被注入或以其他方式形成在晶粒封裝體與基板602之間的空間，並圍繞電連接器210。底部填充膠608可例如為液態環氧樹脂、可變形的凝膠、矽橡膠或其類似物，其被分配在結構之間，然後固化變硬。此底部填充膠的材料，除了其他方面以外，用以減少對電連接器408的損害，並保護電連接器408。
在凸塊形成製程中，透過維持位於晶粒上(例如晶粒的背表面)的隔離層，明顯減少或完全消除靜電可到 達及損害敏感部件的路徑。如此一來，能夠擴大製造晶片上晶圓上基板(CoWoS)元件的製程窗口，減少製程成本及製程複雜性，同時提昇製程良率。
舉例而言，在形成基板的第二側(例如形成介電層、金屬化圖案和/或電連接器)時，附著於基板的晶粒、基板本身與電連接器可成為帶正電的，同時載板(附著於晶粒的背表面)可成為帶負電的，反之亦然。因此，晶粒110與載板之間的界面可以是靜電放電的路徑。透過留下一含量的模塑材料覆蓋晶粒的背表面，模塑材料形成隔離層，可阻擋晶粒與載板之間的靜電放電路徑。
一實施例為方法，包含安裝晶粒至基板的頂表面，以形成元件，密封晶粒及基板的頂表面於模塑化合物內，此模塑化合物於晶粒上具有第一厚度，以及移除模塑化合物於晶粒上的厚度的一部分，而非全部。此方法更包含對元件進行進一步的處理，以及移除模塑化合物於晶粒上的剩餘厚度。
另一實施例為方法，包含將第一晶粒的活性表面附著至第一基板的第一側，以形成晶粒封裝體，以模塑材料密封第一晶粒及基板的第一側，模塑材料具有第一厚度自模塑材料的第一表面至第一晶粒的背表面，背表面相對活性表面，以及對模塑材料的第一表面進行第一平坦化步驟，以具有第二厚度自模塑材料的第一表面至第一晶粒的背表面，第二厚度小於第一厚度。本方法更包含將模塑材料的第一表面附著至載板，形成電連接器於第一基板的第二側上 方，移除載板，以及對模塑材料的第一表面進行第二平坦化步驟，以移除於第一晶粒的背表面上方的剩餘模塑材料。
又一實施例為方法，包含將晶粒附著至第一基板的第一表面，以形成元件封裝體，以模塑化合物密封晶粒及第一基板的第一表面，模塑化合物延伸至晶粒上方，以及移除模塑化合物延伸至晶粒上方的一部分。本方法更包含對元件封裝體進行進一步的處理，以及移除模塑化合物位於晶粒上方的剩餘部分，以暴露晶粒的表面。
以上扼要地提及多種實施例的特徵，因此熟悉此技藝之人士可較好了解本發明的各方面。熟悉此技藝之人士應意識到，為了落實相同的目的及/或達到在此提出的實施例的相同優點，其可輕易使用本發明以做為設計或修改其他製程及結構的基礎。熟悉此技藝之人士亦應了解的是，這些均等的構造不背離本發明之精神及範圍，以及其人可在此進行各種改變、取代、及替代而不背離本發明之精神及範圍。
702、704、706、708、710、712、714、716、718‧‧‧步驟

Claims (10)

  1. 一種製造半導體封裝體的方法，包含：安裝一晶粒至一基板的頂表面，以形成一元件；密封該晶粒及該基板的該頂表面於一模塑化合物內，該模塑化合物於該晶粒上方具有一第一厚度；移除該模塑化合物於該晶粒上方的該厚度的一部分，而非全部；對該元件進行進一步的處理；以及移除該模塑化合物於該晶粒上方的該剩餘厚度。
  2. 如請求項第1項所述之方法，其中該進一步的處理包含形成一電連接器於該基板的一底表面，該電連接器為一控制塌陷晶片連接，或該進一步的處理包含背磨削該基板的一底表面及形成一電連接器於該背磨削面。
  3. 如請求項第1項所述之方法，其中在移除該模塑化合物於該晶粒上方的該厚度的該部分，而非全部之後，該模塑化合物的該剩餘厚度大於30微米。
  4. 如請求項第1項所述之方法，更包含：在移除該模塑化合物於該晶粒上方的該剩餘厚度之後，將一散熱器接著至該晶粒及該模塑化合物。
  5. 一種製造半導體封裝體的方法，包含： 將一第一晶粒的一活性表面附著至一第一基板的一第一側，以形成一晶粒封裝體；以一模塑材料密封該第一晶粒及該基板的該第一側，該模塑材料具有一第一厚度自該模塑材料的一第一表面至該第一晶粒的一背表面，該背表面相對該活性表面；對該模塑材料的該第一表面進行一第一平坦化步驟，以具有一第二厚度自該模塑材料的該第一表面至該第一晶粒的該背表面，該第二厚度小於該第一厚度；將該模塑材料的該第一表面附著至一載板；形成一電連接器於該第一基板的一第二側上方；移除該載板；以及對該模塑材料的該第一表面進行一第二平坦化步驟，以移除於該第一晶粒的該背表面上方的該剩餘模塑材料。
  6. 如請求項第5項所述之方法，更包含：形成一第一導通孔自該第一基板的該第一側延伸至該第一基板內，該第一晶粒電性耦接該第一導通孔的一第一端，且該電連接器耦接該導通孔的一第二端。
  7. 如請求項第5項所述之方法，更包含：形成一底部填充膠於該第一晶粒的該活性表面與該第一基板的該第一側之間，該底部填充膠的一側壁直接鄰接該模塑材料。
  8. 如請求項第5項所述之方法，更包含將一第二晶粒的一活性表面附著至該第一基板的該第一側，以形成該晶粒封裝體，該第二晶粒側向鄰接該第一晶粒，其中在對該模塑材料的該第一表面進行該第二平坦化步驟之後，該模塑材料的一部分留在該第一晶粒與該第二晶粒之間。
  9. 一種製造半導體封裝體的方法，包含：將一晶粒附著至一第一基板的一第一表面，以形成一元件封裝體；以一模塑化合物密封該晶粒及該第一基板的該第一表面，該模塑化合物延伸至該晶粒上方；移除該模塑化合物延伸至該晶粒上方的一部分；對該元件封裝體進行進一步的處理；以及移除該模塑化合物位於該晶粒上方的該剩餘部分，以暴露該晶粒的一表面。
  10. 如請求項第9項所述之方法，其中該進一步的處理包含：安裝該元件封裝體至一載板，該模塑化合物自該晶粒與該載板分離；形成一導電凸塊於該第一基板的一第二表面上方，該第二表面相對該第一表面；移除該載板；以及施加一背磨削膠帶至該導電凸塊及該第一基板的該 第二表面上方，在移除該模塑化合物位於該晶粒上方的該剩餘部分，以暴露該晶粒的該表面時，該背磨削膠帶位於該導電凸塊上方，且該方法更包含使用該導電凸塊安裝該元件封裝體至該第二表面。
TW104114915A 2013-12-30 2015-05-11 製造半導體封裝體的方法 TW201608653A (zh)

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US20150187607A1 (en) 2015-07-02
CN104752236A (zh) 2015-07-01
TW201533861A (zh) 2015-09-01

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