CN104752236A - 用于封装应用的两步模塑研磨 - Google Patents

用于封装应用的两步模塑研磨 Download PDF

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Publication number
CN104752236A
CN104752236A CN201410385450.7A CN201410385450A CN104752236A CN 104752236 A CN104752236 A CN 104752236A CN 201410385450 A CN201410385450 A CN 201410385450A CN 104752236 A CN104752236 A CN 104752236A
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tube core
substrate
thickness
moulding
moulding compound
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CN201410385450.7A
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CN104752236B (zh
Inventor
黄文浚
李建成
刘国洲
薛瑞云
郑锡圭
林志贤
林俊成
陆湘台
谢子逸
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开的实施例包括半导体封装件及其形成方法。一个实施例是一种方法，包括：将管芯安装到衬底的顶面以形成器件；将管芯和衬底的顶面封装在模塑料中，模塑料在管芯之上具有第一厚度；以及去除管芯之上的模塑料的部分但非所有厚度。该方法还包括对器件执行进一步处理并且去除管芯之上的模塑料的剩余厚度。

Description

用于封装应用的两步模塑研磨
优先权请求
本申请要求于2013年12月30日提交的标题为“Two Step MoldingGrinding for ESD Protection”的序列号为No.61/922,002的美国临时申请的优先权，该申请结合于此作为参考。
技术领域
本发明总体涉及半导体领域，更具体地，涉及半导体封装技术。
背景技术
半导体器件应用于多种电子应用，诸如应用于个人计算机、手机、数码相机以及其他电子设备。半导体器件通常通过以下方式制造：在半导体衬底上顺序沉积绝缘层或介电层、导电层及半导体材料层；并且使用光刻将多个材料层图案化以在其上形成电路组件和元件。
由于多种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的提高，半导体工业经历了快速发展。在多数情况下，集成度的这种提高源自对半导体工艺节点的缩小(例如，使工艺节点朝向次20nm节点缩小)。随着最近对小型化、更高速度和更大带宽及更低能耗和更小延时的需求的增长，增加了对更小且更具创造性的半导体管芯的封装技术的需求。
发明内容
根据本发明的一个方面，提供了一种方法，包括：将管芯安装到衬底的顶面以形成器件；将管芯和衬底的顶面密封在模塑料中，模塑料具有位于管芯上方的第一厚度；去除模塑料中位于管芯上方的部分厚度但非全部厚度；对器件执行进一步处理；以及去除模塑料中位于管芯上方的剩余厚度。
优选地，进一步处理包括在衬底的底面上形成电连接件。
优选地，电连接件是可控塌陷芯体片连接件。
优选地，该进一步处理包括重新研磨衬底的底面并且在研磨后的表面上形成电连接件。
优选地，该方法还包括：将器件安装到第二衬底上。
优选地，第二衬底是印刷电路板。
优选地，在去除模塑料中位于管芯上方的部分厚度但非全部厚度之后，模塑料的剩余厚度大于30μm。
优选地，该方法还包括：在去除模塑料中位于管芯上方的剩余厚度之后，将散热片粘附至管芯和模塑料。
优选地，在去除模塑料中位于管芯上方的剩余厚度之后，管芯和模塑材料具有基本共面的表面，表面位于衬底的远端。
根据本发明的另一方面，提供了一种方法，包括：将第一管芯的有效表面附接至第一衬底的第一侧以形成管芯封装件；通过模塑材料密封第一管芯和衬底的第一侧，模塑材料具有从模塑材料的第一表面至第一管芯的背面的第一厚度，背面与有效表面相对；对模塑材料的第一表面执行第一平坦化步骤以具有从模塑材料的第一表面至第一管芯的背面的第二厚度，第二厚度小于第一厚度；将模塑材料的第一表面附接至载体衬底；在第一衬底的第二侧上方形成电连接件；去除载体衬底；以及对模塑材料的第一表面执行第二平坦化步骤，以去除位于第一管芯的背面上方的剩余模塑材料。
优选地，该方法还包括：形成从第一衬底的第一侧延伸至第一衬底内的第一通孔，第一管芯电连接至第一通孔的第一端，而电连接件连接至该通孔的第二端。
优选地，该方法还包括：在对模塑材料的第一表面执行第二平坦化步骤之前，在电连接件上方和第一衬底的第二侧上方形成保护膜。
优选地，保护膜是背面研磨胶带。
优选地，该方法还包括：使用电连接件将管芯封装件安装至第二衬底。
优选地，该方法还包括：在第一管芯的有效表面和第一衬底的第一侧之间形成底部填充物，底部填充物的侧壁直接邻接模塑材料。
优选地，在对模塑材料的第一表面执行第二平坦化步骤之后，模塑材料的第一表面和第一管芯的背面基本共面。
优选地，该方法还包括：将第二管芯的有效表面附接至第一衬底的第一侧以形成管芯封装件，第二管芯横向邻近于第一管芯，其中，在对模塑材料的第一表面执行第二平坦化步骤之后，模塑材料的部分保留在第一管芯和第二管芯之间。
根据本发明的又一方面，提供了一种方法，包括：将管芯附接至第一衬底的第一表面以形成器件封装件；通过模塑料密封管芯和第一衬底的第一表面，模塑料在管芯上方延伸；去除模塑料中在管芯上方延伸的部分；对器件封装执行进一步处理；以及去除模塑料中位于管芯上方的剩余部分以暴露管芯的表面。
优选地，该进一步处理包括：将器件封装件安装至载体衬底上，模塑料将载体衬底与管芯分隔开；在第一衬底的第二表面上形成导电凸块，第二表面与第一表面相对；去除载体衬底；以及在导电凸块和第一衬底的第二表面上方施加背面研磨胶带，在去除模塑料中位于管芯上方的剩余部分以暴露管芯的表面期间，背面研磨胶带位于导电凸块上方。
优选地，该方法还包括：使用导电凸块将器件封装件安装至第二衬底。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图10示出了根据一些实施例的形成封装件时的中间步骤的截面图。
图11是根据一些实施例形成封装件的工艺的流程图。
具体实施方式
为了实施本发明的不同部件，以下公开提供了许多不同的实施例或实例。以下描述元件和布置的特定示例以简化本发明。当然这些仅仅是示例且并不打算限定。例如，以下描述中第一部件形成在第二部件上可包括其中第一部件和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成在第一部件和第二部件之间的实施例，使得第一部件和第二部件不直接接触。另外，本发明可能在各个实施例中重复参考数字和/或字母。这种重复只是为了简明的目的且其本身并不指定各个实施例和/或所讨论的结构之间的关系。
而且，为便于说明，诸如“在···之下”、“下面”、“下部的”、“在···之上”、“上部”等空间关系术语可在此用以描述附图中所示的一个元件或特征与另一个元件或特征的关系。除了图中所示的定向之外，空间相对术语旨在包括处于使用或操作状态的器件的不同定向。装置可以另外被定向(旋转90度或者在其他定向)，并且在此使用的空间相对描述符可类似进行相应的解释。
实施例将参考具体环境(即，采用芯体片-晶圆-衬底(CoWoS)工艺的管芯-中介层-衬底堆叠式封装)中的实施例进行描述。然而，其他实施例也可以应用于其他封装，诸如管芯-管芯-衬底堆叠式封装及其他处理。
概括来讲，本公开的实施例可被提供用于改进的方法，以在例如C4(可控塌陷芯体片连接)制造过程的制造过程期间减少或最小化或可能完全消除静电放电(ESD)事件。由此，可扩展用于制造CoWoS器件的工艺窗、降低制造的成本和复杂性，同时增加制程良率。
虽然在制造环境中不能完全消除静电，但可减小其影响。正如本文描述的，一种方法是在C4凸块处理期间在管芯(诸如，管芯的背面)上保持隔离层。这可以减少或消除静电可以到达并且损坏敏感组件的路径。
图1至图10示出了根据一些实施例的形成封装件的中间步骤的截面图，而图11是根据一些实施例的图1至图10中所示的工艺的流程图。
图1示出了一个或多个管芯110的形成(步骤702)。衬底102包括处于处理期间的一个或多个管芯110。衬底102包括有效表面102A之上的互连结构106，接合焊盘108在互连结构106中和/或上形成。
衬底102可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，还可以使用化合物材料，诸如，硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳硅化锗、磷砷化镓、磷化铟镓以及它们的组合等。另外，衬底102可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如，外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。
衬底102可以包括有源和无源器件(图1中未示出)。本领域普通技术人员应当认识到，可以使用多种器件(诸如，晶体管、电容器、电阻器、它们的组合等)来生成用于一个或多个管芯110的结构性和功能性设计需求。
包括一个或多个介电层和各自的金属化图案的互连结构106形成在有效表面202A上。介电层中的金属化图案可诸如通过使用通孔和/或迹线在器件之间引导电信号，并且还可包含诸如电容器、电阻器、电感器等的多种电子器件。多种器件和金属化图案可以被互连以执行一个或多个功能。该功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。
在互连结构208中形成的一个或多个金属间介电(IMD)层可例如通过本领域中已知的任何合适方法由低k介电材料制成，任何合适方法诸如为旋涂、化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体化学汽相沉积(HDP-CVD)等，低k介电材料诸如为磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的的混合物、它们的组合等。例如，通过使用光刻技术在IMD层上沉积并图案化光刻胶材料以暴露IMD层中要变为金属化图案的部分，从而在IMD层中形成金属化图案。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺来在IMD层中形成与IMD层的暴露部分对应的凹槽和/或开口。凹槽和/或开口可内衬有扩散阻挡层并且由导电材料填充。扩散阻挡层可以包括通过原子层沉积(ALD)等沉积的TaN、Ta、TiN、Ti、CoW等中的一层或多层，而导电材料可包括通过化学汽相沉积(CVD)、物理汽相沉积(PVD)等沉积的铜、铝、钨、银以及它们的组合等。IMD层上的任何过多扩散阻挡层和/或导电材料都可以诸如通过使用化学机械抛光(CMP)去除。
接合焊盘108在互连结构106中和/或上形成。在一些实施例中，通过在互连结构106的一个或多个介电层中形成凹槽(未示出)来形成接合焊盘108。凹槽可以成形为允许接合焊盘108被嵌入到互连结构106中。在其他实施例中，由于接合焊盘108形成在互连结构106上，故省略了凹槽。接合焊盘108在电学上和/或物理上将一个或多个管芯110连接至随后接合的衬底202(参见图4)。在一些实施例中，接合焊盘108包括由铜、钛、镍、金等或它们的组合制成的薄种晶层(未示出)。接合焊盘108的导电材料可以沉积在薄种晶层之上。导电材料可以通过电化学镀工艺、CVD、ALD、PVD等或它们的组合形成。在实施例中，接合焊盘108的导电材料是铜、钨、铝、银、金等或者它们的组合。
在实施例中，接合焊盘108是包括三层导电材料(诸如一层钛、一层铜和一层镍)的凸块下金属(UBM)。然而，本领域普通技术人员应当认识到，存在适用于形成UBM 108的材料和层的很多合适的配置，诸如，铬/铬-铜合金/铜/金的配置、钛/钛钨/铜的配置或者铜/镍/金的配置。可用于UBM108的任何合适材料或材料层都旨在包括在当前申请的范围内。
在图2中，包括互连结构106的衬底102被单片化为独立的管芯110(步骤704)。通常，管芯110包含相同电路，诸如包含相同的器件和金属化图案，然而管芯可以具有不同电路。在一些实施例中，该单片化借助锯、激光、切割等或它们的组合。
图3示出了衬底202的第一侧的形成(步骤706)。衬底202可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，还可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳硅化锗、磷砷化镓、磷化铟镓、这些的组合等的化合物材料。另外，衬底202可以是SOI衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合。在一个可选实施例中，衬底202是基于诸如玻璃纤维增强树脂芯体的绝缘芯体。一种示例性芯体材料是诸如FR4的玻璃纤维树脂。用于芯体材料的选择包括双马来酰亚胺三嗪(BT)树脂，或可选地，包括其他PC板材料或膜。诸如干膜式增层膜(ABF)或其他层压材料的增层膜可用于衬底202。
衬底202可以包括在衬底202的第一表面202A中和/或上形成的有源和无源器件(图3中未示出)。本领域普通技术人员应认识到，可以使用诸如晶体管、电容器、电阻器、它们的组合等的多种器件来满足用于衬底202的结构性和功能性设计需求。可以使用任何合适方法来形成这些器件。在一些实施例中，衬底202是内部通常不含有源器件的中介层，然而中介层可以包括在第一表面202A中和/或上形成的无源器件。
通孔(TV)206成形为从衬底202的第一表面202A延伸到衬底202中。TV 206有时还被称为衬底通孔或者当衬底202是硅衬底时被称为硅通孔。TV 206可以通过经过例如蚀刻、粉碎、激光技术等或它们的组合在衬底202中形成凹槽来形成。薄阻挡层可以诸如通过CVD、ALD、PVD、热氧化等或它们的组合被共形地沉积在衬底202的前侧上方和开口中。阻挡层可以包括氮化物或氮氧化物，诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨等或它们的组合。导电材料可以被沉积在薄阻挡层上方和开口中。导电材料可以通过电化学镀工艺、CVD、ALD、PVD等或它们的组合形成。导电材料的实例是铜、钨、铝、银、金等或它们的组合。例如通过CMP从衬底202的前侧去除过多的导电材料和阻挡层。因此，TV 206可以包括导电材料以及位于导电材料和衬底202之间的薄阻挡层。
互连结构208在衬底202的第一表面202A上方形成，并且用于将集成电路器件(如果存在)和/或TV 206连接在一起和/或连接至外部器件。互连结构208可以包括一个或多个介电层以及介电层中相应的金属化图案。金属化图案可以包括通孔和/或迹线，从而将任何器件和/或TV 206互连在一起和/或互连至外部器件。金属化图案有时被称为重分布线(RDL)。介电层可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、低-K介电材料，诸如PSG、BPSG、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的组合物以及它们的组合等。介电层可以通过本领域中已知的任何合适方法沉积，诸如，旋涂、CVD、PECVD、HDP-CVD等。例如通过使用光刻技术在介电层上沉积并且图案化光刻胶材料来暴露介电层中要变为金属化图案的部分，从而在介电层中形成金属化图案。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺在介电层中形成与介电层的暴露部分对应的凹槽和/或开口。凹槽和/或开口可内衬有扩散阻挡层并且由导电材料填充。扩散阻挡层可以包括通过ALD等沉积的TaN、Ta、TiN、Ti、CoW等中的一层或多层，而导电材料可以包括通过CVD、PVD等沉积的铜、铝、钨、银和它们的组合等。介电层上的任何过多的扩散阻挡层和/或导电材料可以诸如通过使用CMP去除。
电连接件210在互连结构208的顶面上形成并且电连接至互连结构208。电连接件210可以是焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、由化学镀镍钯浸金技术(ENEPIG)形成的凸块等。电连接件210可以包括诸如焊料、铜、铝、金、镍、银、钯、锡或它们的组合的导电材料。在电连接件210是焊料凸块的实施例中，通过首先借助通常采用的方法形成焊料层来形成电连接件210，通常采用的方法诸如为蒸发、电镀、印刷、焊料转移、植球等。一旦焊料层在该结构上形成，则可执行回流以将材料成形为期望凸块形状。在另一实施例中，电连接件210是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如，铜柱)。金属柱可以是无焊料并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接器210的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可通过电镀工艺形成。
图4示出例如通过倒装芯片接合将管芯110附接至第一衬底的第一侧(步骤708)以形成管芯封装。电连接件210将管芯110中的电路电连接至互连结构208和TV 206。
管芯110可以包括逻辑管芯，诸如中央处理单元(CPU)、图形处理单元(GPU)等或它们的组合。在一些实施例中，管芯110包括管芯堆叠件(未示出)，管芯堆叠件可以包括逻辑管芯和内存管芯。管芯110可以包括诸如宽I/O管芯的输入/输出(I/O)管芯。
管芯110和互连结构208之间的接合可以是焊料接合或直接金属-金属(诸如，铜-铜或锡-锡)接合。在实施例中，管芯110通过回流工艺接合至互连结构208。在该回流工艺期间，电连接件210与接合焊盘108和互连结构208接触，从而在物理上和电学上将管芯110电连接至互连结构208。
底部填充材料302可以被注入或另外形成在管芯110和互连结构208之间的空间中并且围绕电连接件210。底部填充材料302可例如是配给在该结构之间并且被固化至变硬的液态环氧树脂、可变形凝胶、硅橡胶或类似物。其中，使用该底部填充材料以减少损害并保护电连接件210。
在管芯110附接至衬底202之后，管芯110被密封(步骤710)。在一些实施例中，通过模塑材料304封装管芯110。模塑材料304可例如使用模压成型而模制在管芯110上。在一些实施例中，模塑材料304由模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合制成。可以执行固化步骤来固化模塑材料304，其中，该固化可为热固化、超紫外线固化等或它们的组合。
在一些实施例中，管芯110被埋入模塑材料304中，并且在模塑材料304固化之后，如图5中所示，对模塑材料304执行第一平坦化处理(步骤712)。在一个实施例中，第一平坦化工艺是研磨工艺，然而也可采用包括蚀刻、激光剥蚀、抛光等的其他技术。使用第一平坦化处理来平坦化模塑材料304，以提供模塑材料304的基本平坦顶面304A。第一平坦化处理去除管芯110上方的模塑材料304的一部分而非全部，使得管芯110的背面110A仍然被埋在模塑材料304中。在一个实施例中，管芯110的背面110A之上的模塑材料304的剩余量具有大于约30μm的厚度T1，诸如，约30μm至约50μm之间。
厚度T1是模塑材料304阻断管芯110和载体衬底402之间的静电放电路径的足够厚度，并且还允许在不暴露管芯110的情况下对模塑料304进行可能的再加工。例如，在第一平坦化处理之后，可能在模塑料304上发现缺陷，并且可能需要执行例如研磨工艺的再加工处理以去除该缺陷。通过在管芯110的背面110A上方具有至少30μm模塑料304，不会在再加工处理期间暴露管芯110的背面110A，因此它们仍然由模塑料304保护。
图6示出倒置管芯封装件并且将模塑材料304的表面304A粘合到载体衬底402以允许形成衬底202的第二侧。载体衬底402可以是任何合适衬底，其对载体衬底402上方的组件和结构提供(在制造处理的中间操作期间)机械支撑。载体衬底402可以是晶圆(包括玻璃、石英、硅(例如，硅晶圆)、氧化硅、金属板、陶瓷材料等)。
在形成第二侧时，对衬底202的第二侧执行薄化处理，将衬底202减薄至第二表面202B，直到暴露TV 206为止。在一个实施例中，薄化处理是研磨处理，然而可采用包括蚀刻、激光剥蚀、抛光等的其他技术。介电层404在衬底202的第二表面202B上形成。可使用上述类似技术在第二表面202B上和介电层404中形成金属化图案406。
电连接件408同样在衬底202的第二侧上形成，并且电连接至TV 206。在一些实施例中，电连接件408是焊球、金属柱、C4凸块、微凸块、由ENEPIG形成的凸块等。电连接件408可包括导电材料，诸如，焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在另一实施例中，电连接件408是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如，铜柱)。金属柱可不含焊料并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接器408的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过电镀处理形成。电连接件408可以用于接合至附加电组件，附加电组件可以是半导体衬底、封装衬底、印刷电路板(PCB)等。
在衬底202的第二侧形成(例如，介电层404、金属化图案406和/或电连接件408的形成)期间，管芯110、衬底202以及电连接件408可以变为带正电，而载体衬底402可以变为带负电，反之亦然。因此，管芯110和载体衬底402之间的界面是静电放电路径。该静电能量的放电可能损害管芯110和衬底202中和/或上的器件。通过留下一定量的覆盖管芯110的背面110A的模塑材料304，模塑材料304形成隔离层，其阻断管芯110和载体衬底402之间的静电放电路径。载体衬底402和管芯110的背面110A通过厚度为T1的模塑材料304分离，该厚度T1是阻断管芯110和载体衬底402之间的静电放电路径的模塑材料304的足够厚度。
图7示出将保护膜420施加至衬底202的第二侧(步骤714)并且去除载体衬底402。保护膜420可以是诸如背面研磨(BG)胶带(UV或非UV胶带)的胶带，其可以用于在后续的模塑材料平坦化处理(参见图8)期间保护衬底202的第二侧免于研磨碎片。保护膜420可以例如使用辊子(未示出)而施加在衬底202的第二侧上。保护膜420可以具有足够厚度以如图7所示完全覆盖电连接件408。
图8示出对模塑材料304执行第二平坦化处理(步骤716)。在一个实施例中，第二平坦化处理是研磨处理，然而可以采用包括蚀刻、激光剥蚀、抛光等的其他技术。第二平坦化处理用于去除模塑材料304的过多部分，其过多部分位于管芯110的背面110A之上。在一些实施例中，管芯110的背面110A被暴露，并且与模塑材料304的表面304A平齐。
在一些实施例中，在第二平坦化处理之后，与不使用上述两步模塑材料平坦化处理的管芯(其通常具有约1.05μm的厚度)相比，管芯110可以具有约2.2μm的从有效表面102A到背面110A的厚度。本公开的实施例的另一方面是当采用上述处理时模塑材料304的表面304A的粗糙度不同。例如，在一些实施例中，相对于不采用该处理时的约0至1μm的粗糙度，观测到约1μm至约3μm的粗糙度。管芯110的厚度差异和模塑材料304的表面粗糙度差异至少部分地归结于在保护膜420位于管芯封装的相反侧上(例如，在衬底202的第二侧之上)时执行第二模塑材料平坦化处理(参见以上步骤716)，这是因为保护膜420比在第一模塑材料平坦化处理期间位于管芯封装的相反侧上(参见以上步骤712)的衬底202更软。因此，较软保护膜420可以压缩并且吸收在第二模塑材料平坦化处理期间施加的一些压力，这使得第二模塑材料处理消耗较少的管芯110的背面110A，并且还可以增加模塑材料304的表面304A的粗糙度。
图9示出去除保护膜420并且将可选的散热片502附接至管芯110的背面110A和模塑材料304的表面304A。散热片502通过粘合膜(未示出)而粘合至管芯110和模塑材料304。粘合膜可以被施加至散热片502或管芯110的背面110A和模塑材料304的表面304A，从而使具有的厚度不会厚到抑制热消散。粘合膜可以是环氧树脂、合成树脂等或它们的组合。散热片502可以是金属板。用于金属板的示例性材料是铜、镀镍的铜、铝等或它们的组合。散热片502通常可以具有良好的导热性和/或具有堪比管芯110的热膨胀系数(CTE)的CTE。当处于完整封装件中时，散热片502通常散热。
图10示出将管芯封装附着至衬底602(步骤718)。衬底602可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，还可以使用化合物材料，诸如，硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳硅化锗、磷砷化镓、磷化铟、它们的组合等。另外，衬底602可为SOI衬底。通常，SOI衬底包括半导体材料层，诸如，外延硅、锗、硅锗、SOI、SGOI或它们的组合。在一个可选实施例中，衬底602是基于绝缘芯体的诸如玻璃纤维增强树脂芯体。一种示例性芯体材料是诸如FR4的玻璃纤维树脂。用于芯体材料的选择包括BT树脂，或者可选地，包括其他PC板材料或膜。诸如ABF或其他层压板的增层膜可以用于衬底602。
衬底602可以包括有源和无源器件(未在图10中示出)。本领域普通技术人员应认识到，诸如晶体管、电容器、电阻器、上述组合等的多种器件可以用于满足用于衬底602的结构性和功能性设计要求。可以使用任何合适方法形成器件。在一些实施例中，衬底602是封装衬底。
衬底602包括位于衬底602的第一侧上的接合焊盘606和位于衬底的第二侧上的电连接件604，第二侧与第一侧相对。接合焊盘606和电连接件604可以分别类似于如上的接合焊盘108和电连接件408，因此在此不再重复，然而接合焊盘108和606不一定与电连接件408和604相同。
在管芯封装和衬底602之间的接合可以是焊料接合或直接金属-金属(诸如，铜-铜或锡-锡)接合。在一个实施例中，管芯封装通过回流处理被接合至衬底602。在该回流处理期间，电连接件408与金属化图案406和接合焊盘606接触，从而在物理上和电学上将管芯封装电连接至衬底602。
底部填充材料608可以被注入或以其它方式形成在管芯封装和衬底602之间的空间中并且围绕电连接件408。底部填充材料608可例如是分布在该结构之间并且随后被固化至变硬的液态环氧树脂、可变形凝胶、硅橡胶等。其中，该底部填充材料用来减少对电连接件408的损害并保护电连接件408。
通过在凸块形成处理期间将隔离层保留在管芯(诸如，管芯的背面)上，可明显减小或完全消除静电可以到达并且损害敏感组件的路径。由此，可扩展用于制造CoWoS器件的工艺窗，降低制造的成本和复杂性，同时增加制程良率。
例如，在衬底的第二侧(例如，介电层、金属化图案和/或电连接件的形成)形成期间，附接至衬底的管芯、衬底本身以及电连接件可变为带正电，同时载体衬底(附接至管芯的背面)可变为带负电，反之亦然。因此，管芯110和载体衬底之间的界面可以是静电放电路径。通过留下一定量的覆盖管芯的背面的模塑材料，模塑材料形成隔离层，其阻断管芯和载体衬底之间的静电放电路径。
一个实施例是一种方法，包括：将管芯安装到衬底的顶面以形成器件；将管芯和衬底的顶面封装在模塑料中；模塑料具有在管芯之上的第一厚度；以及去除管芯之上的模塑料的一部分而非所有厚度。该方法还包括：对器件执行进一步处理并且去除管芯之上的模塑料的剩余厚度。
另一个实施例是一种方法，包括：将第一管芯的有效表面附接至第一衬底的第一侧以形成管芯封装；用模塑材料封装第一管芯和衬底的第一侧，模塑材料具有从模塑材料的第一表面到第一管芯的背面的第一厚度，背面与有效表面相对；以及对模塑材料的第一表面执行第一平坦化步骤以具有从模塑材料的第一表面到第一管芯的背面的第二厚度，第二厚度小于第一厚度。该方法还包括：将模塑材料的第一表面附接至载体衬底；在第一衬底的第二侧之上形成电连接件；去除载体衬底；以及对模塑材料的第一表面执行第二平坦化步骤以去除第一管芯的背面之上的剩余模塑材料。
又一个实施例是一种方法，包括：将管芯附接至第一衬底的第一表面以形成器件封装件；通过模塑料封装管芯和第一衬底的第一表面，模塑料在管芯之上延伸；以及去除在管芯之上延伸的模塑料的一部分。该方法还包括：对器件封装执行进一步处理并去除管芯之上的模塑料的剩余部分以暴露管芯的表面。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种方法，包括：
将管芯安装到衬底的顶面以形成器件；
将所述管芯和所述衬底的顶面密封在模塑料中，所述模塑料具有位于所述管芯上方的第一厚度；
去除所述模塑料中位于所述管芯上方的部分厚度但非全部厚度；
对所述器件执行进一步处理；以及
去除所述模塑料中位于所述管芯上方的剩余厚度。
2.根据权利要求1所述的方法，其中，所述进一步处理包括在所述衬底的底面上形成电连接件。
3.根据权利要求2所述的方法，其中，所述电连接件是可控塌陷芯体片连接件。
4.根据权利要求1所述的方法，其中，所述进一步处理包括重新研磨所述衬底的底面并且在研磨后的所述表面上形成电连接件。
5.根据权利要求1所述的方法，还包括：将所述器件安装到第二衬底上。
6.根据权利要求5所述的方法，其中，所述第二衬底是印刷电路板。
7.根据权利要求1所述的方法，其中，在去除所述模塑料中位于所述管芯上方的部分厚度但非全部厚度之后，模塑料的剩余厚度大于30μm。
8.根据权利要求1所述的方法，还包括：
在去除所述模塑料中位于所述管芯上方的所述剩余厚度之后，将散热片粘附至所述管芯和所述模塑料。
9.一种方法，包括：
将第一管芯的有效表面附接至第一衬底的第一侧以形成管芯封装件；
通过模塑材料密封所述第一管芯和所述衬底的第一侧，所述模塑材料具有从所述模塑材料的第一表面至所述第一管芯的背面的第一厚度，所述背面与所述有效表面相对；
对所述模塑材料的第一表面执行第一平坦化步骤以具有从所述模塑材料的第一表面至所述第一管芯的背面的第二厚度，所述第二厚度小于所述第一厚度；
将所述模塑材料的第一表面附接至载体衬底；
在所述第一衬底的第二侧上方形成电连接件；
去除所述载体衬底；以及
对所述模塑材料的第一表面执行第二平坦化步骤，以去除位于所述第一管芯的背面上方的剩余模塑材料。
10.一种方法，包括：
将管芯附接至第一衬底的第一表面以形成器件封装件；
通过模塑料密封所述管芯和所述第一衬底的第一表面，所述模塑料在所述管芯上方延伸；
去除所述模塑料中在所述管芯上方延伸的部分；
对所述器件封装执行进一步处理；以及
去除所述模塑料中位于所述管芯上方的剩余部分以暴露所述管芯的表面。
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