CN106328608B - 用于芯片封装件的结构和形成方法 - Google Patents

用于芯片封装件的结构和形成方法 Download PDF

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CN106328608B
CN106328608B CN201610517172.5A CN201610517172A CN106328608B CN 106328608 B CN106328608 B CN 106328608B CN 201610517172 A CN201610517172 A CN 201610517172A CN 106328608 B CN106328608 B CN 106328608B
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chip
semiconductor chip
substrate
packaging piece
semiconductor
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CN106328608A (zh
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魏文信
吴集锡
余振华
胡宪斌
侯上勇
陈伟铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种芯片封装件的结构和形成方法。该芯片封装件包括具有许多半导体管芯的芯片堆叠件。该芯片封装件还包括半导体芯片，且半导体芯片高于芯片堆叠件。该芯片封装件还包括覆盖芯片堆叠件的顶部和侧壁以及半导体芯片的侧壁的封装层。本发明实施例涉及用于芯片封装件的结构和形成方法。

Description

用于芯片封装件的结构和形成方法
优先权声明和交叉引用
本申请要求于2015年7月2日提交的美国临时申请第62/188,169号的优先权，其全部内容结合于此作为参考。
技术领域
本发明实施例涉及用于芯片封装件的结构和形成方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其他电子设备的各种电子应用中。通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体层以及使用光刻和蚀刻工艺图案化各个材料层以在半导体衬底上形成电路组件和元件来制造这些半导体器件。
半导体工业通过不断减小最小化部件尺寸来继续提高各种电子组件(如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多的组件集成到给定的面积中。在一些应用中，这些更小的电子组件也使用利用更小的面积和更小的高度的更小的封装件。
已经发展了新的封装技术以提高半导体器件的密度和功能。这些用于半导体器件的相对新型的封装技术面临制造的挑战。
发明内容
根据本发明的一个实施例，提供了一种芯片封装件，包括：芯片堆叠件，包括多个半导体管芯；半导体芯片，其中，所述半导体芯片高于所述芯片堆叠件；以及封装层，覆盖所述芯片堆叠件的顶部和侧壁以及所述半导体芯片的侧壁。
根据本发明的另一实施例，还提供了一种芯片封装件，包括：第一半导体芯片；第二半导体芯片；以及模塑料层，围绕所述第一半导体芯片和所述第二半导体芯片，其中，所述模塑料层覆盖所述第一半导体芯片的顶面，以及所述模塑料层的顶面与所述第二半导体芯片的顶面基本上共面。
根据本发明的又一实施例，还提供了一种用于形成芯片封装件的方法，包括：将第一半导体芯片和第二半导体芯片接合在衬底上方；在所述衬底上方形成封装层以包封所述第一半导体芯片和所述第二半导体芯片；以及平坦化所述封装层从而暴露所述第二半导体芯片的顶面，且所述第一半导体芯片的顶面被所述封装层覆盖。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1A至图1F是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。
图2是根据一些实施例的芯片封装件的截面图。
图3A至图3E是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。
图4是根据一些实施例的芯片封装件的截面图。
图5是根据一些实施例的芯片封装件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
描述本发明的一些实施例。图1A至图1F是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。可以在图1A至图1F描述的阶段之前、期间和/或之后提供额外的操作。对于不同的实施例，描述的一些阶段可以被替换或消除。可以将额外的部件添加至半导体器件结构。对于不同的实施例，可以替代或消除以下所描述的一些部件。虽然通过按照特定的顺序实施操作来论述一些实施例，但可以以另一逻辑顺序来实施这些操作。
根据一些实施例，如图1A所示，在衬底180上方接合半导体芯片10以及芯片堆叠件20和30。在一些实施例中，半导体芯片10高于芯片堆叠件20或30。在一些实施例中，半导体芯片10包括半导体衬底100和在半导体衬底100上形成的互连结构(未示出)。例如，在半导体衬底100的底面上形成互连结构。互连结构包括多个层间介电层和在层间介电层中形成的多个导电部件。这些导电部件包括导电线、导电通孔和导电接触件。导电部件的一些部分可以用作导电焊盘。
在一些实施例中，在半导体衬底100中形成各种器件元件。各种器件元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)、二极管和/或其他合适的元件。
器件元件通过互连结构互连以形成集成电路器件。集成电路器件包括逻辑器件、存储器件(例如，静态随机存取存储器，SRAM)、射频(RF)器件、输入/输出(I/O)器件、芯片上系统(SoC)、器件的其他适用的类型或它们的组合。在一些实施例中，半导体芯片10是包括多个功能的芯片上系统(SoC)芯片。
在一些实施例中，芯片堆叠件20和30的每个包括堆叠的多个半导体管芯。如图1A所示，芯片堆叠件20包括半导体管芯200、202A、202B、202C、202D、202E、202F、202G和202H。在一些实施例中，芯片堆叠件20包括包封和保护半导体管芯的模塑料层210。模塑料层210可以包括环氧树脂(具有填料分散在环氧树脂中)。填料可以包括绝缘纤维、绝缘颗粒、其他合适的元素或它们的组合。
在一些实施例中，半导体管芯202A、202B、202C、202D、202E、202F、202G和202H是存储器管芯。存储器管芯可以包括诸如静态随机存取存储器(SRAM)器件、动态随机存取存储器(DRAM)器件、其他合适的器件或它们的组合的存储器器件。在一些实施例中，半导体管芯200是电连接至存储器管芯(堆叠在半导体管芯200上)的控制管芯。芯片堆叠件20可以用作高带宽存储器(HBM)。在一些实施例中，芯片堆叠件30也是包括多个堆叠的存储器管芯的高带宽存储器。
可以对本发明的实施例做出许多改变和/或修改。在一些实施例中，芯片堆叠件20和30的一个仅包括一个芯片。在这些情况下，参考标号20或30可以用于表示半导体芯片。
如图1A所示，在一些实施例中，在这些半导体管芯200、202A、202B、202C、202D、202E、202F、202G和202H之间形成导电接合结构206以将它们接合在一起。在一些实施例中，导电接合结构206的每个包括金属柱和/或焊料凸块。在一些实施例中，底部填充元件208形成在这些半导体管芯之间以围绕和保护导电接合结构206。在一些实施例中，底部填充元件208包括具有环氧树脂(填料分散在环氧树脂中)。填料可以包括绝缘纤维、绝缘颗粒、其他合适的元素或它们的组合。在一些实施例中，分散在底部填充元件208中的填料的尺寸和/或密度小于那些分散在模塑料层210中的填料的尺寸和/或密度。
在一些实施例中，如图1A所示，在芯片堆叠件20中的一些半导体管芯中形成多个导电部件282。导电部件282的每个穿半导体管芯200、202A、202B、202C、202D、202E、202F、202G和202H中的一个并且电连接至导电接合结构206的一个。导电部件282用作衬底穿孔(TSV)。可以通过导电部件282在这些垂直堆叠的半导体管芯之间传输电信号。
根据一些实施例，如图1A所示，半导体芯片10以及芯片堆叠件20和30通过导电接合结构106接合至衬底180上。在一些实施例中，导电接合结构106包括焊料凸块、金属柱凸块、其他合适的结构或它们的组合。在一些实施例中，导电接合结构106中的每个包括金属柱凸块102、焊料元件104和金属柱凸块184。例如，金属柱凸块102和184基本上是由铜制成的。
在一些实施例中，在半导体芯片10以及芯片堆叠件20和30的底面上方形成许多金属柱凸块102。在一些实施例中，在与半导体芯片10以及芯片堆叠件20和30接合之前，在衬底180上方形成许多金属柱凸块184。
在一些实施例中，在接合工艺之前，在金属柱凸块102和184中的一个或两个上施加诸如焊膏的焊料材料。之后，金属柱凸块102和184通过焊料材料接合在一起。焊料材料在金属柱凸块102和184之间形成焊料元件104。结果，如图1A所示，形成导电接合结构106。在一些实施例中，焊料材料是包括锡(Sn)的合金材料。合金材料还包括另一元素。元件可以包括铅、银、铜、镍、铋、另一合适的元素或它们的组合。在一些实施例中，焊料材料不包括铅。
在一些实施例中，衬底180包括半导体材料、陶瓷材料、绝缘材料、聚合物材料、另一合适的材料或它们的组合。在一些实施例中，衬底180是半导体衬底。半导体衬底可以是诸如硅晶圆的半导体晶圆。
如图1A所示，根据一些实施例，在衬底180中形成许多导电部件182。在一些实施例中，在金属柱凸块184的形成之前，形成导电部件182。在一些实施例中，导电部件182的每个电连接至金属柱凸块184的一个。包括例如再分布层的互连结构(未示出)可以用于在导电部件182和金属柱凸块184之间形成电连接件。在一些实施例中，在导电部件182和衬底180之间形成绝缘元件(未示出)以防止不同导电部件182之间的短路。
在一些实施例中，导电材料182由铜、铝、钛、钨、钴、金、铂、另一合适的材料或它们的组合制成。在一些实施例中，绝缘元件是由氧化硅、氮化硅、氮氧化硅、碳化硅、另一合适的材料或它们的组合制成的。在一些实施例中，一种或多种光刻和蚀刻工艺用于形成限定导电部件182的位置的许多开口。之后，在衬底180上方依次沉积绝缘层和导电层以填充开口。然后，实施平坦化工艺以去除绝缘层和导电层的在开口的外部的部分。结果，绝缘层和导电层的在开口中的剩余部分分别形成绝缘元件和导电部件182。
如图1B所示，根据一些实施例，形成底部填充层108以围绕和保护导电接合结构106。在一些实施例中，底部填充层108与导电接合结构106直接接触。在一些实施例中，通过毛细管作用分散液态底部填充材料并且固化液态底部填充材料以形成底部填充层108。在一些实施例中，底部填充层108包括环氧树脂(填料分散在环氧树脂中)。填料可以包括纤维、颗粒、其他合适的元素或它们的组合。
根据一些实施例，如图1C所示，在衬底180上方形成封装层110以包封半导体芯片10以及芯片堆叠件20和30。在一些实施例中，封装层110填充半导体芯片10以及芯片堆叠件20或30之间的间隙。在一些实施例中，封装层110与底部填充层108直接接触。在一些实施例中，封装层110不与导电接合结构106直接接触。在一些实施例中，封装层110与芯片堆叠件20和30的模塑料层210直接接触。
在一些实施例中，封装层110包括聚合物材料。在一些实施例中，封装层110是模塑料层。模塑料层可以包括环氧树脂(填料分散在环氧树脂中)。填料可以包括绝缘纤维、绝缘颗粒、其他合适的元素或它们的组合。在一些实施例中，分散在封装层110中的填料的尺寸和/或密度大于分散在底部填充层108中的那些填料的尺寸和/或密度。
在一些实施例中，施加液态模塑料材料，并且然后应用热操作以固化液态模塑料材料。结果，液态模塑料材料被硬化且被转变为封装层110。在一些实施例中，在从约200摄氏度至约230摄氏度的范围内的温度下实施热操作。热操作的操作时间可以在从约1小时至约3小时的范围内。
如图1D所示，根据一些实施例，平坦化封装层110从而暴露半导体芯片10的顶面。在一些实施例中，半导体芯片10和封装层110的顶面基本上彼此共面。在一些实施例中，使用研磨工艺、化学机械抛光(CMP)工艺、另一适用的工艺或它们的组合平坦化封装层110。在一些实施例中，芯片堆叠件20或30的顶面仍然由封装层110覆盖。在一些实施例中，在平坦化工艺期间，芯片堆叠件20和30由封装层110保护。在平坦化工艺期间，芯片堆叠件20和30不接地。因此，在平坦化工艺期间，防止芯片堆叠件20和30受到损坏，显著地改善了芯片堆叠件20和30的质量和可靠性。
如图1D所示，在一些实施例中，封装层110覆盖芯片堆叠件20和30的顶面和侧壁。在一些实施例中，半导体芯片10的顶面不由封装层110覆盖。在一些实施例中，封装层110的顶面与半导体芯片10的顶面基本上共面，这可以有助于后续的工艺。
如图1E所示，根据一些实施例，减薄衬底180以暴露导电部件182。在一些实施例中，导电部件182的每个都穿透衬底180。在一些实施例中，导电部件182的每个都电连接至导电接合结构106的一个。在一些实施例中，颠倒图1D所示的结构。之后，使用平坦化工艺减薄衬底180以暴露导电部件182。平坦化工艺可以包括CMP工艺、研磨工艺、蚀刻工艺、另一适用的工艺或它们的组合。
之后，根据一些实施例，如图1E所示，在衬底180上方形成导电元件。如图1E所示，在一些实施例中，导电元件包括金属柱114和焊料元件116。然而，可以对本发明的实施例做出许多改变和/或修改。在一些其他实施例中，导电元件具有不同的结构。例如，导电元件不包括金属柱。导电元件仅可以包括焊料凸块。在一些实施例中，形成缓冲层112以保护导电元件。在一些实施例中，金属柱114的每个电连接至导电部件182的一个。如图1E所示，在一些实施例中，缓冲层112沿着金属柱114的侧壁的部分延伸。在一些实施例中，缓冲层112由氮化硅、氮氧化硅、氧化硅、聚酰亚胺、环氧树脂、聚苯并恶唑(PBO)、另一合适的材料或它们的组合制成。
如图1F所示，根据一些实施例，图1E中所示的结构接合至衬底118上。在一些实施例中，衬底118是诸如印刷电路板的电路板。在一些其他实施例中，衬底118是陶瓷衬底。如图1F所示，在一些实施例中，在衬底118的相对两表面上形成导电元件120和124。在一些实施例中，导电元件120和124是诸如可控塌陷芯片连接(C4)凸块和/或球栅阵列(BGA)凸块的焊料凸块。如图1F所示，在一些实施例中，导电元件120和焊料元件116被回流且接合在一起。
在一些实施例中，导电部件120的每个通过在衬底118中形成的导电部件(未示出)电连接至导电元件124的一个。导电部件可以包括导线和导电通孔。然后，在一些实施例中，在衬底118和衬底180之间形成底部填充层122以保护其间的导电接合结构。
可以对本发明的实施例作出许多改变和/或修改。图2是根据一些实施例的芯片封装件的截面图。在一些实施例中，不形成底部填充层108。在一些实施例中，封装层110填充衬底180和包括半导体芯片10以及芯片堆叠件20和30的半导体芯片之间的间隙。封装层110围绕导电接合结构106。在一些实施例中，由于不形成底部填充层108，所以封装层110与导电接合结构106直接接触。
在一些实施例中，衬底180用作插入件。在一些实施例中，插入件不包括其中的有源器件。在一些其他实施例中，插入件包括在其中形成的一个或多个有源器件。在一些实施例中，衬底180是硅插入件。可以使用衬底180以改善结构强度和芯片封装件的可靠性。然而，本发明的实施例不限制于此。可以对本发明的实施例作出许多改变和/或修改。在一些实施例中，不形成衬底180。
图3A至图3E是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。根据一些实施例，如图3A所示，半导体芯片10以及芯片堆叠件20和30附接在载体衬底300上。粘合层(未示出)可以用于将半导体芯片10以及芯片堆叠件20和30附接至载体衬底300上。在一些实施例中，载体衬底300包括玻璃衬底、陶瓷衬底、半导体衬底、聚合物衬底、另一合适的衬底或它们的组合。在一些实施例中，载体衬底300是临时衬底以在随后的工艺期间支撑半导体芯片10以及芯片堆叠件20和30。之后，可以去除载体衬底300。
根据一些实施例，如图3B所示，在载体衬底300上方形成封装层310以包封半导体芯片10以及芯片堆叠件20和30。在一些实施例中，封装层310填充半导体芯片10以及芯片堆叠件20或30之间的间隙。在一些实施例中，封装层310与芯片堆叠件20和30的模塑料层210直接接触。
在一些实施例中，封装层310包括聚合物材料。在一些实施例中，封装层310是模塑料层。模塑料层可以包括环氧树脂(填料分散在环氧树脂中)。填料可以包括绝缘纤维、绝缘颗粒、其他合适的元素或它们的组合。
在一些实施例中，施加液态模塑料材料，并且然后应用热操作以固化液态模塑料材料。结果，液态模塑料材料被硬化且被转变为封装层310。在一些实施例中，在从约200摄氏度至约230摄氏度的范围内的温度下实施热操作。热操作的操作时间可以在从约1小时至约3小时的范围内。
如图3C所示，根据一些实施例，平坦化封装层310从而暴露半导体芯片10的顶面。在一些实施例中，使用研磨工艺、化学机械抛光(CMP)工艺、另一适用的工艺或它们的组合平坦化封装层310。在一些实施例中，芯片堆叠件20或30的顶面仍然由封装层310覆盖。在一些实施例中，在平坦化工艺期间，芯片堆叠件20和30由封装层310保护。在平坦化工艺期间，芯片堆叠件20和30不接地。因此，在平坦化工艺期间，防止芯片堆叠件20和30受到损坏，显著地改善了芯片堆叠件20和30的质量和可靠性。
如图3C所示，在一些实施例中，封装层310覆盖芯片堆叠件20和30的顶面和侧壁。在一些实施例中，半导体芯片10的顶面不由封装层310覆盖。在一些实施例中，封装层310的顶面与半导体芯片10的顶面基本上共面，这可以有助于后续的工艺。
如图3D所示，根据一些实施例，去除载体衬底300从而暴露半导体芯片10、芯片堆叠件20和30以及封装层310的底面。在一些实施例中，半导体芯片10、芯片堆叠件20和30以及封装层310的底面基本上彼此共面。
之后，如图3D所示，根据一些实施例，在半导体芯片10以及芯片堆叠件20和30的底面上方形成导电元件。如图3D所示，在一些实施例中，导电元件包括金属柱314和焊料元件316。在一些其他实施例中，导电元件包括其他配置。在一些实施例中，形成缓冲层(未示出)以保护导电元件。
如图3E所示，根据一些实施例，图3D中所示的结构接合至衬底318上。在一些实施例中，衬底318是诸如印刷电路板的电路板。在一些其他实施例中，衬底318是陶瓷衬底。如图3E所示，在一些实施例中，在衬底318的相对两表面上形成导电元件320和324。在一些实施例中，导电元件320和324是诸如可控塌陷芯片连接(C4)凸块和/或球栅阵列(BGA)凸块的焊料凸块。如图3E所示，在一些实施例中，导电元件320和焊料元件316被回流且接合在一起。
在一些实施例中，导电部件320的每个通过在衬底318中形成的导电部件(未示出)电连接至导电元件324的一个。导电部件可以包括导线和导电通孔。然后，在一些实施例中，在衬底318和包括半导体芯片10以及芯片堆叠件20和30的芯片之间形成底部填充层322以保护其间的导电接合结构。在一些实施例中，封装层310不与其间的导电接合结构直接接触。
在一些实施例中，由于封装层310的保护，在制造工艺期间防止芯片堆叠件20和30受到损坏。例如，缓冲了从封装层310的平坦化和至衬底318的接合工艺生成的应力。改善了芯片封装件的质量。
可以对本发明的实施例作出许多改变和/或修改。图4是根据一些实施例的芯片封装件的截面图。在一些实施例中，底部填充层108不仅围绕导电接合结构106并且还在半导体芯片10的侧壁上延伸。半导体芯片10的侧壁的部分由底部填充层108覆盖。在一些实施例中，底部填充层108在芯片堆叠件20和30上延伸。芯片堆叠件20和30的侧壁的部分由底部填充层108覆盖。
可以对本发明的实施例作出许多改变和/或修改。图5是根据一些实施例的芯片封装件的截面图。图5中示出的结构类似与图1F中示出的结构。在一些实施例中，在芯片堆叠件20和半导体芯片40之间定位半导体芯片10。在一些实施例中，半导体芯片10高于芯片堆叠件20或半导体芯片40。在一些实施例中，半导体芯片40和芯片堆叠件20的高度彼此不同。在一些实施例中，半导体芯片40高于芯片堆叠件20。
在一些实施例中，半导体芯片40包括半导体衬底400和在半导体衬底400上形成的互连结构(未示出)。例如，在半导体衬底400的底面上形成互连结构。互连结构包括多个层间介电层和在层间介电层中形成的多个导电部件。这些导电部件包括导线、导电通孔和导电接触件。导电部件的一些部分可以用作导电焊盘。
在一些实施例中，类似于半导体衬底100，在半导体衬底400中形成各种器件元件。各种器件元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)、二极管和/或其他合适的元件。
器件元件通过互连结构互连以形成集成电路器件。集成电路器件包括逻辑器件、存储器器件(例如，静态随机存取存储器，SRAM)、射频(RF)器件、输入/输出(I/O)器件、芯片上系统(SoC)、器件的其他适用的类型或它们的组合。在一些实施例中，半导体芯片40是包括多个功能的芯片上系统(SoC)芯片。在一些实施例中，半导体管芯10和40的一个或多个功能彼此不同。
本发明的实施例形成包括可以是芯片堆叠件的第一半导体芯片和第二半导体芯片的芯片堆叠件。第一半导体芯片和第二半导体芯片的高度不同。形成诸如模塑料层的封装层以包封第一半导体芯片和第二半导体芯片。减薄封装层以暴露第一半导体芯片。在减薄工艺期间，第二半导体芯片由封装层保护而不直接地接地。由于在减薄工艺期间封装层的保护，防止第二半导体芯片(或芯片堆叠件)受到负面影响。显著地改善了芯片封装件的性能和可靠性。
根据一些实施例，提供一种芯片封装件。该芯片封装件包括具有许多半导体管芯的芯片堆叠件。该芯片封装件还包括半导体芯片，且半导体芯片高于芯片堆叠件。该芯片封装件还包括覆盖芯片堆叠件的顶部和侧壁以及半导体芯片的侧壁的封装层。
根据一些实施例，提供一种芯片封装件。该芯片封装件包括第一半导体芯片和第二半导体芯片。该芯片封装件还包括围绕第一半导体芯片和第二半导体芯片的模塑料层。该模塑料层覆盖第一半导体芯片的顶面，且模塑料层的顶面与第二半导体芯片的顶面基本上共面。
根据一些实施例，提供了一种用于形成芯片封装件的方法。该方法包括在衬底上方接合第一半导体芯片和第二半导体芯片。该方法还包括在衬底上方形成封装层以包封第一半导体芯片和第二半导体芯片。该方法还包括平坦化封装层从而暴露第二半导体芯片的顶面，且第一半导体芯片的顶面由封装层覆盖。
根据本发明的一个实施例，提供了一种芯片封装件，包括：芯片堆叠件，包括多个半导体管芯；半导体芯片，其中，所述半导体芯片高于所述芯片堆叠件；以及封装层，覆盖所述芯片堆叠件的顶部和侧壁以及所述半导体芯片的侧壁。
在上述芯片封装件中，所述半导体芯片的顶面未被所述封装层覆盖。
在上述芯片封装件中，还包括衬底，其中，所述芯片堆叠件和所述半导体芯片通过导电接合结构接合在所述衬底上。
在上述芯片封装件中，所述衬底是半导体衬底。
在上述芯片封装件中，还包括穿透所述衬底且电连接至所述导电接合结构的一个导电接合结构的导电部件。
在上述芯片封装件中，所述封装层围绕所述导电接合结构且与所述导电接合结构直接接触。
在上述芯片封装件中，还包括围绕所述导电接合结构且与所述导电接合结构直接接触的底部填充层，其中，所述底部填充层位于所述衬底和所述封装层之间。
在上述芯片封装件中，所述底部填充层与所述封装层直接接触。
在上述芯片封装件中，所述芯片堆叠件包括多个存储器管芯。
在上述芯片封装件中，所述封装层的顶面与所述半导体芯片的顶面基本共面。
在上述芯片封装件中，所述芯片堆叠件包括围绕所述半导体管芯的模塑料层。
根据本发明的另一实施例，还提供了一种芯片封装件，包括：第一半导体芯片；第二半导体芯片；以及模塑料层，围绕所述第一半导体芯片和所述第二半导体芯片，其中，所述模塑料层覆盖所述第一半导体芯片的顶面，以及所述模塑料层的顶面与所述第二半导体芯片的顶面基本上共面。
在上述芯片封装件中，所述第二半导体芯片高于所述第一半导体芯片。
在上述芯片封装件中，还包括衬底，其中，所述第一半导体芯片和所述第二半导体芯片通过导电接合结构接合在所述衬底上。
在上述芯片封装件中，还包括穿透所述衬底且电连接至所述导电接合结构的一个导电接合结构的导电部件。
在上述芯片封装件中，所述模塑料层围绕所述导电接合结构且与所述导电接合结构直接接触。
根据本发明的又一实施例，还提供了一种用于形成芯片封装件的方法，包括：将第一半导体芯片和第二半导体芯片接合在衬底上方；在所述衬底上方形成封装层以包封所述第一半导体芯片和所述第二半导体芯片；以及平坦化所述封装层从而暴露所述第二半导体芯片的顶面，且所述第一半导体芯片的顶面被所述封装层覆盖。
在上述用于形成芯片封装件的方法中，在所述平坦化工艺期间，所述第一半导体芯片不接地。
在上述用于形成芯片封装件的方法中，所述第一半导体芯片和所述第二半导体芯片通过多个导电接合结构接合在所述衬底上。
在上述用于形成芯片封装件的方法中，还包括在形成所述封装层之前形成底部填充层以围绕所述导电接合结构。
上面概述了若干实施例的特征、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (18)

1.一种芯片封装件，包括：
芯片堆叠件，包括多个半导体管芯；
半导体芯片，其中，所述半导体芯片高于所述芯片堆叠件，所述半导体芯片与所述芯片堆叠件横向偏移，并且在垂直方向上不存在重叠部分；
封装层，覆盖所述芯片堆叠件的顶部和侧壁以及所述半导体芯片的侧壁；以及
衬底，其中，所述芯片堆叠件和所述半导体芯片通过导电接合结构接合在所述衬底上。
2.根据权利要求1所述的芯片封装件，其中，所述半导体芯片的顶面未被所述封装层覆盖。
3.根据权利要求1所述的芯片封装件，其中，所述衬底是半导体衬底。
4.根据权利要求3所述的芯片封装件，还包括穿透所述衬底且电连接至所述导电接合结构的一个导电接合结构的导电部件。
5.根据权利要求1所述的芯片封装件，其中，所述封装层围绕所述导电接合结构且与所述导电接合结构直接接触。
6.根据权利要求1所述的芯片封装件，还包括围绕所述导电接合结构且与所述导电接合结构直接接触的底部填充层，其中，所述底部填充层位于所述衬底和所述封装层之间。
7.根据权利要求6所述的芯片封装件，其中，所述底部填充层与所述封装层直接接触。
8.根据权利要求1所述的芯片封装件，其中，所述芯片堆叠件包括多个存储器管芯。
9.根据权利要求1所述的芯片封装件，其中，所述封装层的顶面与所述半导体芯片的顶面共面。
10.根据权利要求1所述的芯片封装件，其中，所述芯片堆叠件包括围绕所述半导体管芯的模塑料层。
11.一种芯片封装件，包括：
第一半导体芯片；
第二半导体芯片，其中，所述第一半导体芯片与所述第二半导体芯片横向偏移，并且在垂直方向上不存在重叠部分；
模塑料层，围绕所述第一半导体芯片和所述第二半导体芯片，其中，所述模塑料层覆盖所述第一半导体芯片的顶面，以及所述模塑料层的顶面与所述第二半导体芯片的顶面共面；以及
衬底，其中，所述第一半导体芯片和所述第二半导体芯片通过导电接合结构接合在所述衬底上。
12.根据权利要求11所述的芯片封装件，其中，所述第二半导体芯片高于所述第一半导体芯片。
13.根据权利要求11所述的芯片封装件，还包括穿透所述衬底且电连接至所述导电接合结构的一个导电接合结构的导电部件。
14.根据权利要求11所述的芯片封装件，其中，所述模塑料层围绕所述导电接合结构且与所述导电接合结构直接接触。
15.一种用于形成芯片封装件的方法，包括：
将第一半导体芯片和第二半导体芯片接合在衬底上方，其中，所述第一半导体芯片与所述第二半导体芯片横向偏移，并且在垂直方向上不存在重叠部分；
在所述衬底上方形成封装层以包封所述第一半导体芯片和所述第二半导体芯片；以及
平坦化所述封装层从而暴露所述第二半导体芯片的顶面，且所述第一半导体芯片的顶面被所述封装层覆盖。
16.根据权利要求15所述的用于形成芯片封装件的方法，其中，在所述平坦化工艺期间，所述第一半导体芯片不接地。
17.根据权利要求15所述的用于形成芯片封装件的方法，其中，所述第一半导体芯片和所述第二半导体芯片通过多个导电接合结构接合在所述衬底上。
18.根据权利要求17所述的用于形成芯片封装件的方法，还包括在形成所述封装层之前形成底部填充层以围绕所述导电接合结构。
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