CN103137596A - 用于多芯片封装的凸块结构 - Google Patents

用于多芯片封装的凸块结构 Download PDF

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CN103137596A
CN103137596A CN2012103016093A CN201210301609A CN103137596A CN 103137596 A CN103137596 A CN 103137596A CN 2012103016093 A CN2012103016093 A CN 2012103016093A CN 201210301609 A CN201210301609 A CN 201210301609A CN 103137596 A CN103137596 A CN 103137596A
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projection
chip
substrate
cube structure
layer
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CN103137596B (zh
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余振华
林俊成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

所述的形成多芯片封装件的机制使具有不同凸块尺寸的芯片能够封装到公共基板。可以将具有较大凸块的芯片和基板上的两个或者两个以上的较小凸块接合起来。相反，可以将芯片上的两个或者两个以上的小凸块和基板上的大凸块接合起来。通过允许将具有不同尺寸的凸块接合在一起，可以将具有不同凸块尺寸的芯片封装在一起，从而形成多芯片封装件。本发明提供了用于多芯片封装的凸块结构。

Description

用于多芯片封装的凸块结构
相关申请的交叉参考
本申请要求于2011年11月29日提交的美国临时专利申请第61/564,594号的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及芯片封装件，具体而言，涉及凸块结构。
背景技术
现代电路的制造包括若干步骤。首先在半导体晶圆上制造集成电路，该半导体晶圆包含多个重复的半导体芯片，每个都包括集成电路。然后从晶圆切割半导体芯片并且对其进行封装。封装工艺具有两个主要目的：保护精细的半导体芯片，以及将内部集成电路连接到外部连接件。
在封装集成电路(IC)芯片中，焊料连接是将IC芯片接合到封装基板的常用方法之一，封装基板可以包括或者可以不包括集成电路和/或其他无源元件。在封装工艺中，可以采用倒装芯片接合在封装基板上安装半导体管芯(或者芯片)。封装基板可以是包括用于在相对侧之间布线发送电信号的金属连接件的中介层。也可以使用其他类型的基板。可以通过直接金属接合、焊料接合等将管芯接合到基板。在芯片封装方面具有许多挑战。
发明内容
为了解决上述技术问题，一方面，本发明提供了一种芯片封装件，包括：第一凸块结构，位于所述芯片封装件的第一芯片和基板之间，其中，所述第一凸块结构的第一焊料层覆盖所述基板上的多于一个凸块。
在所述的芯片封装件中，所述第一凸块结构包括所述第一芯片的一个凸块。
在所述的芯片封装件中，在所述芯片封装件上具有第二芯片，并且其中，在所述第二芯片和所述基板之间具有第二凸块结构，其中，所述第二凸块结构的焊料层将所述基板上的凸块与所述第二芯片上的凸块连接起来。
在所述的芯片封装件中，所述第一凸块结构的多于一个凸块和所述第二凸块结构的所述基板上的所述凸块具有大约相同的尺寸。
在所述的芯片封装件中，所述基板上的多于一个凸块的宽度在约5μm至约30μm的范围内。
在所述的芯片封装件中，所述基板上的多于一个凸块包括2、3、4、5、6、7或者8个凸块。
在所述的芯片封装件中，所述第一凸块结构包括所述第一芯片的一个凸块，其中，所述第一芯片上的凸块的宽度大于约40μm且等于或者小于约120μm。
在所述的芯片封装件中，所述第一芯片是存储芯片。
在所述的芯片封装件中，所述基板是中介层。
在所述的芯片封装件中，所述基板是中介层，其中，所述基板上的多于一个凸块包括铜柱凸块。
在所述的芯片封装件中，所述第一凸块结构包括所述第一芯片的一个凸块，其中，所述第一芯片上的凸块是包括至少铜层的可控塌陷芯片连接(C4)凸块。
在所述的芯片封装件中，所述基板上的多于一个凸块的宽度在约2μm至约10μm的范围内，并且其中，所述第一芯片上的凸块的宽度大于约10μm且等于或者小于约40μm。
另一方面，本发明提供了一种多芯片封装件，包括：第一凸块结构，位于所述芯片封装件的第一芯片和基板之间，其中，所述第一凸块结构的第一焊料层覆盖所述基板上的多于一个凸块；以及第二芯片，位于所述芯片封装件上，并且其中，在所述第二芯片和所述基板之间具有第二凸块结构，其中，所述第二凸块结构的焊料层将所述基板上的凸块与所述第二芯片上的凸块连接起来。
又一方面，本发明提供了一种形成芯片封装件的方法，包括：提供具有C4凸块的第一芯片；提供具有多个凸块的基板；以及通过将所述C4凸块和所述基板的多个凸块接合起来形成第一凸块结构。
所述的方法还包括：提供具有铜柱凸块的第二芯片；以及通过将所述铜柱凸块和所述基板上的另一凸块接合起来形成第二凸块结构。
在所述的方法中，形成所述第一凸块结构和所述第二凸块结构包括对每个凸块结构中的焊料层进行回流以形成经过回流的焊料层。
在所述的方法中，所述第一芯片的C4凸块的宽度大于约40μm且等于或者小于约120μm，并且所述基板的多个凸块的宽度在约5μm至约30μm的范围内。
所述的方法还包括：在提供所述第一芯片之前，在所述第一芯片上形成存储器器件。
所述的方法还包括：在提供所述基板之前，在所述基板上形成硅通孔(TSV)。
所述的方法还包括：提供具有铜柱凸块的第二芯片；以及通过将所述铜柱凸块和所述基板上的另一凸块接合起来形成第二凸块结构，其中，通过同时对所述第一凸块结构和所述第二凸块结构中的焊料进行回流形成所述第一凸块结构和所述第二凸块结构。
附图说明
为了更充分地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1A和图1B示出根据一些实施例的用于在集成电路(IC)管芯(或者芯片)和基板之间形成凸块结构的工艺步骤的截面图。
图1C和图1D示出根据一些实施例的两个凸块结构的截面图。
图2A示出根据一些实施例具有接合到基板的若干芯片的多芯片封装件的俯视图。
图2B示出根据一些实施例沿线P-P截取图2A的多芯片封装件的一部分的截面图。
图2C和图2D示出根据一些实施例的两个凸块结构的截面图。
图3A和图3B示出根据一些实施例的用于在芯片和基板之间形成凸块结构的工艺步骤的截面图。
图3C和图3D示出根据一些实施例的用于在芯片和基板之间形成凸块结构的工艺步骤的截面图。
图3E示出根据一些实施例的用于接合到较大倒装芯片凸块的不同数量和布置的微凸块的俯视图。
图4示出根据一些实施例的形成多芯片封装件的工艺流程。
具体实施方式
在下面详细论述本发明的实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅是示例性的，而不用于限制本发明的范围。
图1A示出根据一些实施例在分别形成凸块121和凸块126之后的集成电路(IC)管芯(或者芯片)120和基板125的截面图。如图1A所示，通过凸块下金属化(UBM)层145C和145S将凸块121和凸块126分别连接到金属焊盘128C和128S。凸块121与凸块126对准用于接合。凸块121的宽度是W。在一些实施例中，凸块126的宽度与凸块121的宽度大约相同。基板125可以是半导体晶圆或者晶圆的一部分。基板125可以包含硅、砷化镓、绝缘体上硅(“SOI”)或者其他类似的材料。基板125也可以包括诸如电阻器、电容器、电感器等无源器件，或者诸如晶体管的有源器件。基板125可以是中介层并且还可以包括基板通孔(TSV)135，如图1A所示。此外，在可选实施例中，基板125也可以是其他材料。例如，可以使用多层电路板。基板125也可以包含双马来酰亚胺三嗪(BT)树脂、FR-4(由纺织玻纤布和环氧树脂粘合剂组成的耐燃复合材料)、陶瓷、玻璃、塑料、胶带、膜或者可以承载接收用于倒装芯片IC管芯120的连接器终端115所需的导电焊盘或接合盘(land)的其他支撑材料。
图1B示出根据一些实施例接合到基板125以形成封装件122的芯片120的截面图。通过焊料层123将凸块121和凸块126连接在一起以形成凸块结构127，焊料层123由凸块121和凸块126的焊料形成。图1B中的凸块结构127具有间距P和凸块127之间的间隔(或者距离)S。
为了先进封装具有许多功能电路的IC管芯，凸块121和凸块126的尺寸相对较小以使更多的凸块连接到芯片120的输入/输出端(I/O)。在一些实施例中，根据一些实施例，凸块121和凸块126的宽度在约5μm至约40μm的范围内。这些凸块也可以被称为微凸块。在一些其他实施例中，凸块121和凸块126的宽度更小，并且在约2μm到约10μm的范围内。微凸块可以包括铜柱并且可以被称为铜柱(或者支柱)凸块。根据一些实施例，凸块(微凸块)121和126的间距P在约10μm至约60μm的范围内。根据一些实施例，凸块(微凸块)121和126的间隔S在约5μm至约30μm的范围内。在一些其他实施例中，当凸块121和凸块126的宽度在约2μm至约10μm的范围内时，凸块(微凸块)121和126的间隔S在约1.5μm至约10μm的范围内。
图1C示出根据一些实施例的具有基板110的凸块结构100。基板110可以是诸如体硅基板的半导体基板，虽然其可以包括其他半导体材料，诸如III族、IV族和/或V族元素。基板110可以包括硅、砷化镓、绝缘体上硅(“SOI”)或者其他类似的材料。可以在基板110的表面形成半导体器件114，诸如晶体管。基板110也可以包括诸如电阻器、电容器、电感器等的无源器件或者诸如晶体管的有源器件。在示例性实施例中，基板110可以包括其他集成电路。基板110可以是中介层。此外，在可选的实施例中，基板110也可以是其他材料。例如，可以使用多层电路板。基板110也可以包含双马来酰亚胺三嗪(BT)树脂、FR-4(由纺织玻纤布和环氧树脂粘合剂组成的耐燃复合材料)、陶瓷、玻璃、塑料、胶带、膜或者其他支撑材料。
在基板110上方形成互连结构112，其包括在其中形成并且连接到半导体器件114的金属线和通孔(未显示)。金属线和通孔可以由铜或铜合金形成，并且可以采用公知的镶嵌工艺形成。互连结构112可以包括公知的层间电介质(ILD)和金属间电介质(IMD)。
在互连结构112上方形成金属焊盘128。金属焊盘128可以包含铝，并因此也可以被称为铝焊盘128，但是其也可以由其他材料形成或者包括其他材料，诸如铜、银、金、镍、钨、它们的合金、和/或它们的多层。可以例如通过下面的互连结构112将金属焊盘128电连接到半导体器件114。金属焊盘128可以是顶部金属层或者再分布层(RDL)。在一些实施例中，形成钝化层130以覆盖金属焊盘128的边部。钝化层130可以由聚酰亚胺或者其他合适的介电材料形成。可以在互连结构112上方以及在与金属焊盘128同一水平面或者在金属焊盘128上方形成其他钝化层。其他钝化层可以由诸如氧化硅、氮化硅、未掺杂的硅酸盐玻璃(USG)、聚酰亚胺、和/或它们的多层的材料形成。
根据一些实施例，凸块结构100包括扩散阻挡层140和薄晶种层142。扩散阻挡层140可以是钛层、氮化钛层、钽层或氮化钽层。晶种层142的材料可以包括铜或铜合金，并因此在下文中被称为铜晶种层142。但是，也可以包括其他金属，诸如银、金、铝和它们的组合。扩散阻挡层140和铜晶种层142的组合也可以被称为凸块下金属化(UBM)层145。
在一些实施例中，凸块结构100还包括铜层150、金属层152和焊料层160。根据一些实施例，通过采用限定开口的光掩模进行电镀形成铜层150、金属层152和焊料层160。在一些实施例中，金属层152是含镍层，包括例如通过电镀的镍层或者镍合金层。金属层152防止在铜和焊料之间形成金属间化合物(IMC)。焊料层160可以是由例如SnAg形成的无铅预焊料层或者焊接材料，包括锡、铅、银、铜、镍、铋的合金或者它们的组合。在图1A中，通过回流，焊料层160变成圆的。在一些实施例中，凸块结构100不包括焊料层160。在一些实施例中，凸块结构100不包括焊料层160和金属层152。
当铜层150的厚度大于焊料层160的厚度时，凸块结构被称为铜柱(或者支柱)凸块。用于先进的芯片封装，减小了凸块间距和凸块宽度。铜柱凸块能够减小凸块间距和宽度。图1A示出的实施例仅是实例；凸块的其他实施例也是可能的。关于凸块形成工艺的更多细节可以在于2010年7月23日提交的名称为“Preventing UBM Oxidation in Bump Formation Processes(防止凸块形成工艺中的UBM氧化)”的美国专利申请第12/842,617号和于2010年7月29日提交的名称为“Mechanisms for Forming Copper PillarBumps(形成铜柱凸块的机制)”的美国专利申请第12/846,353号找到，将这两个申请以其全部内容并入本文中。
图1D示出根据一些其他实施例的凸块结构150。凸块结构150具有许多与凸块结构100类似的部件。对于类似的层或结构采用相同的编号。凸块结构150不具有焊料层160。此外，形成金属层152”以覆盖铜层150的整个表面。去除在UBM层145之后形成的并且从铜层150的边界延伸的铜层150。
随着手持式电子器件的日益普及，存储芯片封装有(一个或多个)逻辑芯片以提高封装件的形状因数。具有多于一个芯片的芯片封装件被称为多芯片封装件。一些芯片，诸如存储芯片具有较少数量的输入/输出(I/O)连接件。由于需要相对较少数量的I/O连接件，制造具有较大凸块的芯片。此外，更大的凸块更容易制造并且可以通过不太先进的加工技术来制造。图2A示出根据一些实施例的具有接合到基板210的若干芯片201-205的多芯片封装件200的俯视图。基板210具有与芯片201-205上的凸块相接合的凸块。尽管在一些实施中，基板210上的凸块具有不同的尺寸，但是随着不同尺寸凸块的数量的增加，制造工艺更复杂并且更昂贵。因此，在一些实施例中，基板210上的凸块具有大约相同的尺寸。
与具有更多数量的凸块的芯片205相比，芯片201-204是具有少量I/O连接件(凸块)的芯片，诸如存储芯片。例如，芯片205可以是逻辑芯片，其需要大量的I/O连接件来实现其功能。结果，使用具有细间距和尺寸的凸块(诸如微凸块)进行外部连接。相比之下，存储芯片201-204不需要这些凸块，因为需要的凸块数量少得多。这也可能使存储芯片201-204的凸块尺寸和间距与逻辑芯片205的相同；但是，不是每一个存储器制造商都具有制造较小凸块诸如微凸块的能力。在单个基板上接合具有不同凸块尺寸的芯片是具有挑战的。
图2B示出根据一些实施例沿线P-P截取的图2A的多芯片封装件200的一部分的截面图。图2B示出在具有比用于芯片205的凸块结构222更大的凸块结构221的基板210上安装芯片201。虽然图2B示出在接合之后，芯片201和芯片205处于同一高度，但这不是必需的。芯片201和芯片205在接合之后可以处于不同的高度。为了简明，在图2B中，凸块结构221和222用圆形表示。示例性凸块结构222是凸块结构127，其形成工艺已在上面描述了并且示出在图1A和图1B中。下面描述如何形成凸块结构221的细节。
图2C示出根据一些实施例用于芯片201的倒装芯片凸块100*的截面图。倒装芯片凸块100*的各层与上面描述的微凸块100(图1C)的各层类似。凸块100*的宽度大于凸块100，根据一些实施例凸块100是微凸块。在一些实施例中，凸块100*的宽度大于约40μm且等于或者小于约120μm。凸块100*也可以被称为C4凸块。C4代表可控塌陷芯片连接。此外，凸块100*的铜层150*的厚度与焊料层160*的厚度的比值不同于凸块100的比值。凸块100*具有比铜层150*更厚的焊料层160*，并且凸块100*不是铜柱凸块。相比之下，微凸块100是具有比焊料层160更厚的铜层150的铜柱凸块。在一些实施例中，凸块100*的铜层150*的厚度在约5μm至约50μm的范围内。根据一些实施例，焊料层160*的厚度在约15μm至约60μm的范围内。
图2D示出根据一些实施例的用于芯片201的倒装芯片凸块100’的截面图。倒装芯片凸块100’的各层与上面描述的凸块100*的各层类似。但是，凸块100’不具有图2C的铜层150*和金属层152*。焊料层160’直接沉积在UBM层145’上。由于回流，焊料层160’变成圆形的。在一些实施例中，UBM层145’不包括铜晶种层142’。倒装芯片100’的宽度范围类似于倒装芯片100*。在一些实施例中，焊料层160’的厚度在约15μm至约120μm的范围内。
图3A示出根据一些实施例的设置在具有微凸块241A和242A的基板210A上方的具有凸块231A的芯片201A的截面图。凸块231A具有图2C中所述的结构。已经在图1C中描述了微凸块241A和242A的结构。在一些实施例中，微凸块241A和242A不具有焊料层160A和金属层152A。然后将芯片201A和基板210A按压在一起从而允许凸块231A接触到微凸块241A和242A。然后，对凸块231A、241A和242A的焊料层进行回流以形成单层(或者整体)233A，根据一些实施例，其是如图3B示出的凸块结构245A的一部分。通过使用基板210A的多于一个微凸块(凸块241A和242A)来收缩芯片201A的倒装芯片凸块231A，凸块结构245A比仅包含单个微凸块(仅具有凸块241A或者凸块242A)的凸块结构更结实。此外，微凸块241A和242A可以分担向凸块231A或者从凸块231A载流。
图3C示出根据一些实施例的设置在具有微凸块241B和242B的基板210B上方的具有凸块231B的芯片201B的截面图。凸块231B具有图2D中所述的结构。已经在图1D中描述了微凸块241B和242B的结构。在一些实施例中，微凸块241B和242B不具有金属层152B。然后将芯片201B和基板210B按压在一起从而允许凸块231B接触到微凸块241B和242B。然后，对凸块231B的焊料层160B进行回流使其成为层233B，根据一些实施例，如图3D所示，层233B包围微凸块241B和242B并且形成凸块结构245B。图3A至图3D中描述的芯片和基板上的凸块以及形成的凸块结构仅是实例。也可以使用其他类型的凸块以及芯片和基板上的凸块的组合来形成不同变化的凸块结构。
上面在图3B和图3D中描述的凸块结构245A和245B在每个结构中仅包括两个微凸块。可选地，可以使用多于两个微凸块来连接倒装芯片凸块。图3E示出用于接合到较大的倒装芯片凸块的不同数量和布置的微凸块的示例性俯视图。图3E(I)示出均匀间隔的3个微凸块。图3E(II)示出均匀间隔的4个微凸块。图3E(III)和图3E(IV)示出用于接合倒装芯片凸块的5个微凸块的两种不同布置。图3E(V)示出均匀间隔的6个微凸块。但是，也可以使用不均匀间隔的微凸块。图3E中示出的微凸块的数目和布置仅是实例。也可以使用其他数目和/或不同布置的微凸块。
虽然在上面将图2A和图2B的芯片201-204以及图3A至图3D的芯片201A和201B描述为存储芯片，芯片201-204以及芯片201A和201B可以是具有比芯片205上的凸块更大的倒装芯片凸块的任何芯片。通过将大凸块与两个或两个以上的小凸块接合形成凸块结构的机制可以应用于各种封装的器件。基板210上的较小凸块210A和/或210B不需要是微凸块。它们仅需要比芯片201-204上的凸块201A和210B小。该机制可以适用于将芯片上凸块与基板上具有不同尺寸的凸块接合起来。例如，较大凸块可以是宽度在约10μm至约40μm范围内的微凸块，并且较小凸块可以是小于微凸块的凸块，其宽度在约2μm至约10μm的范围内。在上面描述的机制中，可以将小于微凸块的两个或两个以上的这样的凸块接合到微凸块。
图4示出根据一些实施例形成多芯片封装件的工艺流程400。在操作401中，提供了具有不同凸块尺寸的两个芯片。芯片上的每个凸块具有大约相同的尺寸。一个芯片具有的凸块尺寸比另一芯片的凸块尺寸大得多，诸如等于或者大于约1.5倍。在操作402中，提供用于与两个芯片相接合的基板。基板具有尺寸与具有较小凸块的芯片相同的凸块。在一些实施例中，基板上的凸块的间距与具有较小凸块的芯片上的间距大约相同。可以颠倒操作401和402的顺序。在操作403中，在基板上设置芯片，其中芯片上的凸块在基板上的凸块的上方对准。在基板上的多于一个凸块上方设置具有较大凸块的芯片上的每个凸块。之后，在操作404中，将凸块按压在一起并且对对准的凸块之间的焊料进行回流以在芯片和基板之间形成凸块结构。因而形成多芯片封装件。可以实施其他加工来完成封装工艺。例如，可以形成底部填充物来填充芯片与基板之间的间隔。
上面所述的用于形成多芯片封装件的机制使具有不同凸块尺寸的芯片能够封装到公共基板。可以将具有较大凸块的芯片与基板上的两个或者两个以上的较小凸块接合起来。相反，可以将芯片上的两个或者两个以上的小凸块与基板上的大凸块接合起来。通过允许将具有不同尺寸的凸块接合在一起，可以将具有不同凸块尺寸的芯片封装在一起，从而形成多芯片封装件。
根据一些实施例，提供了芯片封装件。芯片封装件包括位于芯片封装件的第一芯片和基板之间的第一凸块结构。第一凸块结构的第一焊料层覆盖基板上的多于一个凸块。
根据一些实施例，提供了多芯片封装件。多芯片封装件包括位于芯片封装件的第一芯片和基板之间的第一凸块结构，并且第一凸块结构的第一焊料层覆盖基板上的多于一个凸块。多芯片封装件还包括芯片封装件上的第二芯片，并且在第二芯片和基板之间具有第二凸块结构。第二凸块结构的焊料层将基板上的凸块与第二芯片上的凸块连接起来。
根据一些实施例，提供了一种形成芯片封装件的方法。该方法包括提供具有C4凸块的第一芯片，以及提供具有多个凸块的基板。该方法还包括通过将C4凸块与基板的多个凸块接合来形成第一凸块结构。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的精神和范围的情况下，在其中进行各种改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易地理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种芯片封装件，包括：
第一凸块结构，位于所述芯片封装件的第一芯片和基板之间，其中，所述第一凸块结构的第一焊料层覆盖所述基板上的多于一个凸块。
2.根据权利要求1所述的芯片封装件，其中，所述第一凸块结构包括所述第一芯片的一个凸块。
3.根据权利要求1所述的芯片封装件，其中，在所述芯片封装件上具有第二芯片，并且其中，在所述第二芯片和所述基板之间具有第二凸块结构，其中，所述第二凸块结构的焊料层将所述基板上的凸块与所述第二芯片上的凸块连接起来，并且其中，所述基板上的多于一个凸块的宽度在约5μm至约30μm的范围内。
4.根据权利要求1所述的芯片封装件，其中，所述第一凸块结构的多于一个凸块和所述第二凸块结构的所述基板上的所述凸块具有大约相同的尺寸。
5.根据权利要求1所述的芯片封装件，其中，所述基板是中介层。
6.根据权利要求5所述的芯片封装件，其中，所述基板上的多于一个凸块包括铜柱凸块。
7.根据权利要求1所述的芯片封装件，其中，所述基板上的多于一个凸块的宽度在约2μm至约10μm的范围内，并且其中，所述第一芯片上的凸块的宽度大于约10μm且等于或者小于约40μm。
8.一种多芯片封装件，包括：
第一凸块结构，位于所述芯片封装件的第一芯片和基板之间，其中，所述第一凸块结构的第一焊料层覆盖所述基板上的多于一个凸块；以及
第二芯片，位于所述芯片封装件上，并且其中，在所述第二芯片和所述基板之间具有第二凸块结构，其中，所述第二凸块结构的焊料层将所述基板上的凸块与所述第二芯片上的凸块连接起来。
9.一种形成芯片封装件的方法，包括：
提供具有C4凸块的第一芯片；
提供具有多个凸块的基板；以及
通过将所述C4凸块和所述基板的多个凸块接合起来形成第一凸块结构。
10.根据权利要求9所述的方法，还包括：
提供具有铜柱凸块的第二芯片；以及
通过将所述铜柱凸块和所述基板上的另一凸块接合起来形成第二凸块结构。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104701246A (zh) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 芯片及形成方法、封装成品、提高封装成品良率的方法
CN105023882A (zh) * 2014-04-22 2015-11-04 矽品精密工业股份有限公司 半导体中介板及封装结构
CN106328608A (zh) * 2015-07-02 2017-01-11 台湾积体电路制造股份有限公司 用于芯片封装件的结构和形成方法
CN107039406A (zh) * 2015-11-18 2017-08-11 株式会社村田制作所 电子器件
US9941240B2 (en) 2013-07-03 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor chip scale package and manufacturing method thereof
CN109643708A (zh) * 2016-09-30 2019-04-16 英特尔Ip公司 用于微电子器件的互连结构
TWI727918B (zh) * 2014-01-08 2021-05-21 大陸商珠海越亞半導體股份有限公司 具有超細間距倒裝芯片凸點的基板
CN112861464A (zh) * 2021-03-16 2021-05-28 上海壁仞智能科技有限公司 集成电路芯片的设计方法和集成电路芯片
CN113764286A (zh) * 2020-06-01 2021-12-07 天芯互联科技有限公司 芯片组装方法及组件

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2971081B1 (fr) * 2011-02-02 2013-01-25 Commissariat Energie Atomique Procédé de fabrication de deux substrats relies par au moins une connexion mécanique et électriquement conductrice obtenue
JPWO2014033977A1 (ja) * 2012-08-29 2016-08-08 パナソニックＩｐマネジメント株式会社 半導体装置
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
US9508674B2 (en) 2012-11-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of semiconductor die package
KR101366461B1 (ko) * 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9343419B2 (en) * 2012-12-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
TW201432826A (zh) * 2013-02-01 2014-08-16 Chipbond Technology Corp 半導體封裝製程及其結構
US9070644B2 (en) 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9646894B2 (en) 2013-03-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
FR3003688B1 (fr) * 2013-03-22 2016-07-01 Commissariat Energie Atomique Procede d'assemblage flip chip comportant le pre-enrobage d'elements d'interconnexion
JP2015072996A (ja) * 2013-10-02 2015-04-16 新光電気工業株式会社 半導体装置
KR102237870B1 (ko) * 2013-10-25 2021-04-09 엘지이노텍 주식회사 인쇄회로기판 및 그 제조방법과 이를 이용하는 반도체 패키지
US9147661B1 (en) * 2014-02-03 2015-09-29 Xilinx, Inc. Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same
US9356009B2 (en) 2014-05-27 2016-05-31 Micron Technology, Inc. Interconnect structure with redundant electrical connectors and associated systems and methods
CN105990282B (zh) * 2015-02-27 2019-03-01 华为技术有限公司 一种转接板及电子组件
US10115703B2 (en) 2015-03-17 2018-10-30 Toshiba Memory Corporation Semiconductor device and manufacturing method thereof
US20180166419A1 (en) * 2016-12-12 2018-06-14 Nanya Technology Corporation Semiconductor package
US10510722B2 (en) * 2017-06-20 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
IT201700087318A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
TWI636533B (zh) 2017-09-15 2018-09-21 Industrial Technology Research Institute 半導體封裝結構
US10685935B2 (en) * 2017-11-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Forming metal bonds with recesses
US10957665B2 (en) 2018-01-19 2021-03-23 International Business Machines Corporation Direct C4 to C4 bonding without substrate
US11177065B2 (en) * 2020-03-30 2021-11-16 Qualcomm Incorporated Thermal paths for glass substrates
KR20220000294A (ko) * 2020-06-25 2022-01-03 삼성전자주식회사 반도체 패키지
US20230197658A1 (en) * 2021-12-21 2023-06-22 International Business Machines Corporation Electronic package with varying interconnects
US20230307398A1 (en) * 2022-03-25 2023-09-28 Sensors Unlimited, Inc. Hybridization bumps for fine pitch sensor arrays

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447264A (en) * 1994-07-01 1995-09-05 Mcnc Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
CN1258098A (zh) * 1998-12-04 2000-06-28 日本电气株式会社 背面电极型电子部件和将其装于印刷电路板上的电子组件
US20070013063A1 (en) * 2005-06-23 2007-01-18 Intel Corporation Self alignment features for an electronic assembly
CN101286491A (zh) * 2007-04-09 2008-10-15 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4416054A (en) * 1980-07-01 1983-11-22 Westinghouse Electric Corp. Method of batch-fabricating flip-chip bonded dual integrated circuit arrays
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5860585A (en) * 1996-05-31 1999-01-19 Motorola, Inc. Substrate for transferring bumps and method of use
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) * 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6220499B1 (en) * 1998-09-29 2001-04-24 International Business Machines Corporation Method for assembling a chip carrier to a semiconductor device
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
JP3886405B2 (ja) 2002-04-12 2007-02-28 株式会社リコー はんだバンプ形成方法及びはんだバンプ形成装置
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
JP3891297B2 (ja) * 2003-10-02 2007-03-14 セイコーエプソン株式会社 半導体装置製造用治具
KR20050033254A (ko) 2003-10-06 2005-04-12 학교법인 한양학원 칩 접합방법
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
JP4191167B2 (ja) * 2005-05-16 2008-12-03 エルピーダメモリ株式会社 メモリモジュールの製造方法
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US8237271B2 (en) * 2007-06-19 2012-08-07 International Business Machines Corporation Direct edge connection for multi-chip integrated circuits
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US20090174069A1 (en) * 2008-01-04 2009-07-09 National Semiconductor Corporation I/o pad structure for enhancing solder joint reliability in integrated circuit devices
US8178970B2 (en) * 2009-09-18 2012-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strong interconnection post geometry
US8609526B2 (en) 2009-10-20 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Preventing UBM oxidation in bump formation processes
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8227334B2 (en) * 2010-07-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Doping minor elements into metal bumps

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447264A (en) * 1994-07-01 1995-09-05 Mcnc Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
CN1258098A (zh) * 1998-12-04 2000-06-28 日本电气株式会社 背面电极型电子部件和将其装于印刷电路板上的电子组件
US20070013063A1 (en) * 2005-06-23 2007-01-18 Intel Corporation Self alignment features for an electronic assembly
CN101286491A (zh) * 2007-04-09 2008-10-15 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941240B2 (en) 2013-07-03 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor chip scale package and manufacturing method thereof
CN104701246A (zh) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 芯片及形成方法、封装成品、提高封装成品良率的方法
CN104701246B (zh) * 2013-12-10 2018-03-23 展讯通信（上海）有限公司 芯片及形成方法、封装成品、提高封装成品良率的方法
TWI727918B (zh) * 2014-01-08 2021-05-21 大陸商珠海越亞半導體股份有限公司 具有超細間距倒裝芯片凸點的基板
CN105023882A (zh) * 2014-04-22 2015-11-04 矽品精密工业股份有限公司 半导体中介板及封装结构
CN105023882B (zh) * 2014-04-22 2017-12-01 矽品精密工业股份有限公司 半导体中介板及封装结构
CN106328608B (zh) * 2015-07-02 2019-08-30 台湾积体电路制造股份有限公司 用于芯片封装件的结构和形成方法
CN106328608A (zh) * 2015-07-02 2017-01-11 台湾积体电路制造股份有限公司 用于芯片封装件的结构和形成方法
CN107039406A (zh) * 2015-11-18 2017-08-11 株式会社村田制作所 电子器件
CN107039406B (zh) * 2015-11-18 2020-01-03 株式会社村田制作所 电子器件
CN109643708A (zh) * 2016-09-30 2019-04-16 英特尔Ip公司 用于微电子器件的互连结构
CN113764286A (zh) * 2020-06-01 2021-12-07 天芯互联科技有限公司 芯片组装方法及组件
CN112861464A (zh) * 2021-03-16 2021-05-28 上海壁仞智能科技有限公司 集成电路芯片的设计方法和集成电路芯片

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