TW201432826A - 半導體封裝製程及其結構 - Google Patents

半導體封裝製程及其結構 Download PDF

Info

Publication number
TW201432826A
TW201432826A TW102104103A TW102104103A TW201432826A TW 201432826 A TW201432826 A TW 201432826A TW 102104103 A TW102104103 A TW 102104103A TW 102104103 A TW102104103 A TW 102104103A TW 201432826 A TW201432826 A TW 201432826A
Authority
TW
Taiwan
Prior art keywords
metal bump
substrate
bump
metal
abutting portion
Prior art date
Application number
TW102104103A
Other languages
English (en)
Inventor
Lung-Hua Ho
Fei-Jain Wu
Chih-Ming Kuo
Shih-Chieh Chang
Chia-Jung Tu
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to TW102104103A priority Critical patent/TW201432826A/zh
Priority to CN201310054918.XA priority patent/CN103972114A/zh
Priority to KR1020130026162A priority patent/KR101469589B1/ko
Priority to US13/833,347 priority patent/US20140217578A1/en
Priority to JP2013060046A priority patent/JP2014150235A/ja
Publication of TW201432826A publication Critical patent/TW201432826A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H01L2224/81898—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Abstract

一種半導體封裝製程，其包含下列步驟：提供一第一基板，該第一基板具有至少一第一金屬凸塊，該第一金屬凸塊具有一對接部，該對接部具有一第一軟化點；提供一第二基板，該第二基板具有至少一第二金屬凸塊，該第二金屬凸塊具有一第二軟化點，且該第一金屬凸塊之該第一軟化點小於該第二金屬凸塊之該第二軟化點，該第二金屬凸塊具有一頂面及一側壁；進行一加熱步驟，以使該第一金屬凸塊之該對接部呈軟化狀態；以及壓合該第一基板與該第二基板，以該第二金屬凸塊嵌入呈軟化狀態之該對接部，以使呈軟化狀態之該對接部受壓延伸包覆該第二金屬凸塊之該頂面及該側壁。

Description

半導體封裝製程及其結構
本發明係有關於一種半導體封裝製程，特別係有關於一種具有高品質及低成本之半導體封裝製程。
目前半導體前段封裝技術之微機電系統(Micro Electro Mechanical Systems, MEMS)封裝技術已由結合打線技術與玻璃膠逐漸演變為金屬與金屬對封,然受限於經微機電系統封裝技術之封裝結構於後段製程中不能有助焊劑或高溫製程，因此無法採用成本較低之表面黏著技術(Surface Mount Technology, SMT)進行後段封裝，使得整體封裝成本無法降低。
本發明之主要目的係在於提供一種半導體封裝製程，其藉由加熱第一基板之第一金屬凸塊的對接部，使對接部呈軟化狀態，再壓合第一基板與第二基板，使第二基板之第二金屬凸塊嵌入呈軟化狀態之對接部，並延伸包覆第二金屬凸塊之頂面及側壁。
本發明之一種半導體封裝製程，其包含下列步驟：提供一第一基板，該第一基板具有一第一表面及至少一第一金屬凸塊，該第一金屬凸塊形成於該第一表面上，該第一金屬凸塊具有一底部及一對接部，該底部位於該對接部與該第一基板之間，該對接部具有一第一軟化點（first softening point）；提供一第二基板，該第二基板具有一第二表面及至少一第二金屬凸塊，該第二金屬凸塊形成於該第二表面上，該第二金屬凸塊具有一第二軟化點（second softening point），且該第一金屬凸塊之該第一軟化點小於該第二金屬凸塊之該第二軟化點，該第二金屬凸塊具有一頂面及一側壁；進行一加熱步驟，以使該第一金屬凸塊之該對接部呈軟化狀態；以及壓合該第一基板與該第二基板，該第一表面朝向該第二表面，以該第二金屬凸塊嵌入呈軟化狀態之該第一金屬凸塊的該對接部，以使呈軟化狀態之該對接部受壓延伸包覆該第二金屬凸塊之該頂面及該側壁，該第一金屬凸塊之該底部則位於該第二金屬凸塊與該第一基板之間。
本發明之半導體封裝製程係藉由加熱步驟使該第一基板之該第一金屬凸塊的該對接部呈軟化狀態，再壓合該第一基板及該第二基板，使該第二基板之該第二金屬凸塊嵌入呈軟化狀態之該對接部，並使呈軟化狀態之該對接部受壓延伸包覆該第二金屬凸塊之該頂面及該側壁以形成一金屬間化合物（Intermetallic Compound, IMC），使該第一基板不需助焊劑即可與該第二基板形成電性連接，因此於後段製程中不需助焊劑清洗步驟，且可承受高於壓合溫度之熱製程或環境測試，達到高品質低成本之封裝需求。
請參閱第1A至1D圖，其係本發明之第一實施例，一種半導體封裝製程係包含下列步驟：首先，請參閱第1A圖，提供一第一基板110，該第一基板110具有一第一表面111及至少一第一金屬凸塊112，該第一金屬凸塊112形成於該第一表面111上，在本實施例中，該第一基板110另具有至少一第一凸塊下金屬層113及一接合層114，該第一凸塊下金屬層113形成於該第一表面111且該第一金屬凸塊112覆蓋該第一凸塊下金屬層113，該第一金屬凸塊112具有一底部112a及一對接部112b，該對接部112b具有一第一軟化點（first softening point），該底部112a位於該對接部112b與該第一基板110之間，該接合層114係位於該第一金屬凸塊112之該底部112a與該第一基板110之間，以減少該第一金屬凸塊112之使用量，該第一金屬凸塊112之材質選自於金，該接合層114之材質選自於銅；接著，請參閱第1B圖，提供一第二基板120，該第二基板120具有一第二表面121及至少一第二金屬凸塊122，該第二金屬凸塊122形成於該第二表面121上，在本實施例中，該第二基板120另具有至少一第二凸塊下金屬層123，該第二凸塊下金屬層123形成於該第二表面121且該第二金屬凸塊122覆蓋該第二凸塊下金屬層123，該第二金屬凸塊122包含有一基底層122a及一外罩層122b，該外罩層122b覆蓋該基底層122a，該基底層122a之材質選自於銅，該外罩層122b之材質係選自於錫或錫銀合金，該第二金屬凸塊122具有一第二軟化點（second softening point），且該第一金屬凸塊112之該第一軟化點小於該第二金屬凸塊122之該第二軟化點，該第二金屬凸塊122具有一頂面122c及一側壁122d；之後，請參閱第1C圖，進行一加熱步驟，以使該第一金屬凸塊112’之該對接部112b’呈軟化狀態；最後，請參閱第1D圖，壓合該第一基板110與該第二基板120，該第一表面111朝向該第二表面121，以該第二金屬凸塊122嵌入呈軟化狀態之該第一金屬凸塊112’的該對接部112b’，以使呈軟化狀態之該對接部112b’受壓延伸包覆該第二金屬凸塊122之該頂面122c及該側壁122d，以形成一半導體封裝結構100，該第一金屬凸塊112’之該底部112a’則位於該第二金屬凸塊122與該第一基板110之間。
本發明係利用加熱及壓合步驟使具有該第二軟化點之該第二金屬凸塊122嵌入具有該第一軟化點之該第一金屬凸塊112，由於該第一金屬凸塊112的該對接部112b之該第一軟化點小於該第二金屬凸塊122之該第二軟化點，因此經加熱及壓合步驟後，該第二金屬凸塊122係可嵌入呈軟化狀態之該第一金屬凸塊112’的該對接部112b’，以使呈軟化狀態之該對接部112b’受壓延伸包覆該第二金屬凸塊122之該頂面122c及該側壁122d，以電性連接該第一基板110與該第二基板120，且該第一金屬凸塊112’之該底部112a’則位於該第二金屬凸塊122與該第一基板110之間，以形成不需助焊劑且於後段製程中可承受高於壓合溫度之熱製程或環境測試及不需助焊劑清洗步驟之該半導體封裝結構100，進而達到高品質低成本之封裝需求。
請再參閱第1D圖，其係本發明之一種半導體封裝結構100，其至少包含有一第一基板110以及一第二基板120，該第一基板110具有一第一表面111、至少一第一金屬凸塊112’、至少一第一凸塊下金屬層113及一接合層114，該第一金屬凸塊112’形成於該第一表面111上，該第一凸塊下金屬層113形成於該第一表面111且該第一金屬凸塊112’覆蓋該第一凸塊下金屬層113，該第一金屬凸塊112’具有一底部112a’及一對接部112b’，該對接部112b’具有一第一軟化點，該底部112a’位於該對接部112b’與該第一基板110之間，該接合層114係位於該第一金屬凸塊112’之該底部112a’與該第一基板110之間，在本實施例中，該第一金屬凸塊112’之材質選自於金，該接合層114之材質選自於銅，該接合層114係用以減少該第一金屬凸塊112’之使用量，該第二基板120具有一第二表面121、至少一第二金屬凸塊122及至少一第二凸塊下金屬層123，該第二表面121朝向該第一表面111且該第二金屬凸塊122形成於該第二表面121上，該第二凸塊下金屬層123形成於該第二表面121且該第二金屬凸塊122覆蓋該第二凸塊下金屬層123，該第二金屬凸塊122具有一頂面122c、一側壁122d及一第二軟化點，該第一金屬凸塊112’的該對接部112b’之該第一軟化點係小於該第二金屬凸塊122之該第二軟化點，在本實施例中，該第二金屬凸塊122包含有一基底層122a及一外罩層122b，該外罩層122b覆蓋該基底層122a，該基底層122a之材質選自於銅，該外罩層122b之材質係選自於錫或錫銀合金，其中該第二金屬凸塊122嵌入呈軟化狀態之該第一金屬凸塊112’的該對接部112b’，以使呈軟化狀態之該對接部112b’受壓延伸包覆於該第二金屬凸塊122之該頂面122c及該側壁122d，該第一金屬凸塊112’之該底部112a’則位於該第二金屬凸塊122與該第一基板110之間。由於呈軟化狀態之該對接部112b’受壓延伸包覆於該第二金屬凸塊122之該頂面122c及該側壁122d，因此該半導體封裝結構100不需助焊劑即可完成該第一基板110與該第二基板120之電性連接，省略後續助焊劑清洗之步驟，且當該第一金屬凸塊112’之材質為金時，更具有防氧化之功效。
此外，請參閱第2圖，其係為本發明之第二實施例，其與本發明之第一實施例不同之處在於該第一基板110另具有一間隔層115，該間隔層115係位於該第一金屬凸塊112’之該底部112a’與該接合層114之間，該間隔層115之材質係選自於鎳以防止該接合層114與該第一金屬凸塊112’過度結合。或者，請參閱第3圖，其係為本發明之第三實施例，其與本發明之第一實施例不同之處在於該第一基板110僅具有該第一金屬凸塊112’及該第一凸塊下金屬層113。或者，在另一實施例中，該第二基板120之該第二金屬凸塊122僅具有該基底層122a（圖未繪出）。
另，請參閱第4圖，其係為本發明之第四實施例，其與本發明之第三實施例不同之處在於該第二金屬凸塊122之該頂面122c係呈弧狀。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
100．．．半導體封裝結構
110．．．第一基板
111．．．第一表面
112．．．第一金屬凸塊
112a．．．底部
112b．．．對接部
112’．．．軟化狀態之第一金屬凸塊
112a’．．．軟化狀態之底部
112b’．．．軟化狀態之對接部
113．．．第一凸塊下金屬層
114．．．接合層
115．．．間隔層
120．．．第二基板
121．．．第二表面
122．．．第二金屬凸塊
122a．．．基底層
122b．．．外罩層
122c．．．頂面
122d．．．側壁
123．．．第二凸塊下金屬層
第1A至1D圖：依據本發明之第一較佳實施例，一種半導體封裝製程之截面示意圖。 第2圖：依據本發明之第二較佳實施例，一種半導體封裝結構之截面示意圖。 第3圖：依據本發明之第三較佳實施例，一種半導體封裝結構之截面示意圖。 第4圖：依據本發明之第四較佳實施例，一種半導體封裝結構之截面示意圖。
110．．．第一基板
111．．．第一表面
112’．．．軟化狀態之第一金屬凸塊
112a’．．．軟化狀態之底部
112b’．．．軟化狀態之對接部
113．．．第一凸塊下金屬層
114．．．接合層
120．．．第二基板
121．．．第二表面
122．．．第二金屬凸塊
122a．．．基底層
122b．．．外罩層
122c．．．頂面
122d．．．側壁
123．．．第二凸塊下金屬層

Claims (10)

  1. 一種半導體封裝製程，其至少包含： 　　提供一第一基板，該第一基板具有一第一表面及至少一第一金屬凸塊，該第一金屬凸塊形成於該第一表面上，該第一金屬凸塊具有一底部及一對接部，該底部位於該對接部與該第一基板之間，該對接部具有一第一軟化點（first softening point）； 　　提供一第二基板，該第二基板具有一第二表面及至少一第二金屬凸塊，該第二金屬凸塊形成於該第二表面上，該第二金屬凸塊具有一第二軟化點（second softening point），且該第一金屬凸塊之該第一軟化點小於該第二金屬凸塊之該第二軟化點，該第二金屬凸塊具有一頂面及一側壁； 　　進行一加熱步驟，以使該第一金屬凸塊之該對接部呈軟化狀態；以及 　　壓合該第一基板與該第二基板，該第一表面朝向該第二表面，以該第二金屬凸塊嵌入呈軟化狀態之該第一金屬凸塊的該對接部，以使呈軟化狀態之該對接部受壓延伸包覆該第二金屬凸塊之該頂面及該側壁，該第一金屬凸塊之該底部則位於該第二金屬凸塊與該第一基板之間。
  2. 如申請專利範圍第1項所述之半導體封裝製程，其中該第一基板另具有一接合層，該接合層係位於該第一金屬凸塊之該底部與該第一基板之間。
  3. 如申請專利範圍第2項所述之半導體封裝製程，其中該第一基板另具有一間隔層，該間隔層係位於該第一金屬凸塊之該底部與該接合層之間。
  4. 如申請專利範圍第1項所述之半導體封裝製程，其中該第二金屬凸塊包含有一基底層及一外罩層，該外罩層覆蓋該基底層。
  5. 一種半導體封裝結構，其至少包含： 　　一第一基板，其具有一第一表面及至少一第一金屬凸塊，該第一金屬凸塊形成於該第一表面上，該第一金屬凸塊具有一底部及一對接部，該底部位於該對接部與該第一基板之間，該對接部具有一第一軟化點（first softening point）；以及 　　一第二基板，其具有一第二表面及至少一第二金屬凸塊，該第二表面朝向該第一表面，且該第二金屬凸塊形成於該第二表面上，該第二金屬凸塊具有一頂面及一側壁，且該第二金屬凸塊具有一第二軟化點（second softening point），該對接部之該第一軟化點小於該第二金屬凸塊之該第二軟化點，其中該第二金屬凸塊嵌入呈軟化狀態之該第一金屬凸塊的該對接部，以使呈軟化狀態之該對接部受壓延伸包覆於該第二金屬凸塊之該頂面及該側壁，該第一金屬凸塊之該底部則位於該第二金屬凸塊與該第一基板之間。
  6. 如申請專利範圍第5項所述之半導體封裝結構，其中該第二金屬凸塊包含有一基底層及一外罩層，該外罩層覆蓋該基底層。
  7. 如申請專利範圍第5項所述之半導體封裝結構，其中該第一基板另具有一接合層，該接合層係位於該第一金屬凸塊之該底部與該第一基板之間。
  8. 如申請專利範圍第7項所述之半導體封裝結構，其中該第一基板另具有一間隔層，該間隔層係位於該第一金屬凸塊之該底部與該接合層之間。
  9. 一種半導體封裝製程，其至少包含： 　　提供一第一基板，該第一基板具有一第一表面及至少一第一金屬凸塊，該第一金屬凸塊形成於該第一表面上，該第一金屬凸塊具有一底部及一對接部，該底部位於該對接部與該第一基板之間； 　　提供一第二基板，該第二基板具有一第二表面及至少一第二金屬凸塊，該第二金屬凸塊形成於該第二表面上，該第二金屬凸塊具有一頂面及一側壁； 　　進行一加熱步驟，以使該第一金屬凸塊之該對接部呈軟化狀態；以及 　　壓合該第一基板與該第二基板，該第一表面朝向該第二表面，以該第二金屬凸塊嵌入呈軟化狀態之該第一金屬凸塊的該對接部，以使呈軟化狀態之該對接部受壓延伸包覆該第二金屬凸塊之該頂面及該側壁，該第一金屬凸塊之該底部則位於該第二金屬凸塊與該第一基板之間。
  10. 一種半導體封裝結構，其至少包含： 　　一第一基板，其具有一第一表面及至少一第一金屬凸塊，該第一金屬凸塊形成於該第一表面上，該第一金屬凸塊具有一底部及一對接部，該底部位於該對接部與該第一基板之間；以及 　　一第二基板，其具有一第二表面及至少一第二金屬凸塊，該第二表面朝向該第一表面，且該第二金屬凸塊形成於該第二表面上，該第二金屬凸塊具有一頂面及一側壁，其中該第二金屬凸塊嵌入呈軟化狀態之該第一金屬凸塊的該對接部，以使呈軟化狀態之該對接部受壓延伸包覆於該第二金屬凸塊之該頂面及該側壁，該第一金屬凸塊之該底部則位於該第二金屬凸塊與該第一基板之間。
TW102104103A 2013-02-01 2013-02-01 半導體封裝製程及其結構 TW201432826A (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW102104103A TW201432826A (zh) 2013-02-01 2013-02-01 半導體封裝製程及其結構
CN201310054918.XA CN103972114A (zh) 2013-02-01 2013-02-20 半导体封装制造过程及其结构
KR1020130026162A KR101469589B1 (ko) 2013-02-01 2013-03-12 반도체 패키징 공정 및 그 구조
US13/833,347 US20140217578A1 (en) 2013-02-01 2013-03-15 Semiconductor package process and structure thereof
JP2013060046A JP2014150235A (ja) 2013-02-01 2013-03-22 半導体装置および半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW102104103A TW201432826A (zh) 2013-02-01 2013-02-01 半導體封裝製程及其結構

Publications (1)

Publication Number Publication Date
TW201432826A true TW201432826A (zh) 2014-08-16

Family

ID=51241474

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102104103A TW201432826A (zh) 2013-02-01 2013-02-01 半導體封裝製程及其結構

Country Status (5)

Country Link
US (1) US20140217578A1 (zh)
JP (1) JP2014150235A (zh)
KR (1) KR101469589B1 (zh)
CN (1) CN103972114A (zh)
TW (1) TW201432826A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158667A (zh) * 2015-02-11 2016-11-23 旭德科技股份有限公司 封装基板及其制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6278498B1 (ja) * 2017-05-19 2018-02-14 日本新工芯技株式会社 リング状部材の製造方法及びリング状部材
WO2022209978A1 (ja) * 2021-03-30 2022-10-06 三井金属鉱業株式会社 多層基板の製造方法及び配線基板

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2782914B2 (ja) * 1990-04-26 1998-08-06 日本電気株式会社 バンプ電極結合の形成方法
JPH07169790A (ja) * 1993-12-15 1995-07-04 Fujitsu Ltd フリップチップ接合方法
JP2780631B2 (ja) * 1994-03-09 1998-07-30 日本電気株式会社 電子部品の接続構造およびその製造方法
JPH10270498A (ja) * 1997-03-27 1998-10-09 Toshiba Corp 電子装置の製造方法
US5861678A (en) * 1997-12-23 1999-01-19 Micron Technology, Inc. Method and system for attaching semiconductor dice to substrates
JPH11233561A (ja) * 1998-02-12 1999-08-27 Oki Electric Ind Co Ltd 半導体チップ部品の実装構造
US6543674B2 (en) * 2001-02-06 2003-04-08 Fujitsu Limited Multilayer interconnection and method
US6583517B1 (en) * 2002-04-09 2003-06-24 International Business Machines Corporation Method and structure for joining two substrates with a low melt solder joint
JP2004119773A (ja) * 2002-09-27 2004-04-15 Toshiba Corp 半導体装置及びその製造方法
JP4104490B2 (ja) * 2003-05-21 2008-06-18 オリンパス株式会社 半導体装置の製造方法
JP4171492B2 (ja) * 2005-04-22 2008-10-22 松下電器産業株式会社 半導体装置およびその製造方法
US7946331B2 (en) * 2005-06-14 2011-05-24 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
JP2007043010A (ja) * 2005-08-05 2007-02-15 Matsushita Electric Ind Co Ltd 電子部品の実装方法
JP2009105119A (ja) * 2007-10-22 2009-05-14 Spansion Llc 半導体装置及びその製造方法
KR20090096184A (ko) * 2008-03-07 2009-09-10 주식회사 하이닉스반도체 반도체 패키지
KR101054294B1 (ko) * 2008-04-14 2011-08-08 홍익대학교 산학협력단 접착제로 국부적으로 둘러싸인 범프/패드 접속부를 갖는플립칩 패키지와 그 제조방법
KR20120122637A (ko) * 2011-04-29 2012-11-07 에스케이하이닉스 주식회사 기판, 플립칩 패키지 및 그 제조방법
US8779588B2 (en) * 2011-11-29 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for multi-chip packaging

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158667A (zh) * 2015-02-11 2016-11-23 旭德科技股份有限公司 封装基板及其制作方法
CN106158667B (zh) * 2015-02-11 2018-09-28 旭德科技股份有限公司 封装基板及其制作方法

Also Published As

Publication number Publication date
CN103972114A (zh) 2014-08-06
KR101469589B1 (ko) 2014-12-05
US20140217578A1 (en) 2014-08-07
KR20140099159A (ko) 2014-08-11
JP2014150235A (ja) 2014-08-21

Similar Documents

Publication Publication Date Title
JP5366674B2 (ja) 実装構造体および実装方法
JP5690652B2 (ja) ２個の接合素子の低温加圧焼結接合方法およびそれによって製造される構成体
CN102148206A (zh) 半导体装置封装件及其制造方法
US8866273B2 (en) Lead frame and semiconductor package structure thereof
JP2016131082A5 (zh)
TW201301561A (zh) Led覆晶結構及其製造方法
JPWO2007142052A1 (ja) 半導体パッケージ、その製造方法、半導体装置、及び電子機器
JP2008021751A (ja) 電極、半導体チップ、基板、半導体チップの電極接続構造、半導体モジュールおよびその製造方法
JP2015115419A5 (zh)
TWI600213B (zh) 軟性電路板裝置及相機模組
JP2010287710A5 (ja) 半導体装置の製造方法
TW201432826A (zh) 半導體封裝製程及其結構
TWI553788B (zh) Modified composite wafer carrier structure
CN106024823A (zh) Cmos图像传感器的封装方法
TW201606947A (zh) 晶片之正、背面間電性連接結構及其製造方法
JP2011187635A (ja) 半導体装置およびその製造方法
JP6597056B2 (ja) 半導体実装装置の加熱ヘッダ及び半導体の接合方法
JP5812123B2 (ja) 電子機器の製造方法
TWI415707B (zh) 銅製銲線、銲線接合結構及銲線接合方法
CN104425312A (zh) 半导体制造装置
TW201344864A (zh) 晶片組裝結構及晶片組裝方法
CN100521171C (zh) 一种元件的封装接合结构
TWI529881B (zh) The structure and method of composite carrier board for chip - scale wafer - level package
TWI228305B (en) Structure of stacked chip packaging structure and manufacture method of the same
TWI399974B (zh) 攝像模組之組裝方法