CN104425312A - 半导体制造装置 - Google Patents

半导体制造装置 Download PDF

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CN104425312A
CN104425312A CN201410006086.9A CN201410006086A CN104425312A CN 104425312 A CN104425312 A CN 104425312A CN 201410006086 A CN201410006086 A CN 201410006086A CN 104425312 A CN104425312 A CN 104425312A
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chip
fixture
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semiconductor chip
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深山真哉
尾山幸史
筑山慧至
福田昌利
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Abstract

本发明提供可抑制在半导体芯片产生弯曲应力的半导体制造装置。半导体制造装置具备：夹具，其吸附在主面设有凸起的半导体芯片；和驱动机构，其驱动夹具，使吸附的半导体芯片在安装基板或者其他半导体芯片上载置，夹具在半导体芯片的吸附面设有避免与凸起抵接的凹部。

Description

半导体制造装置
相关申请
本申请以日本专利申请2013-186100号(申请日:2013年9月9日)为基础申请，享受优先权。本申请通过参照该基础申请，包含该基础申请的全部内容。
技术领域
本发明涉及制造半导体装置的半导体制造装置。
背景技术
半导体封装进一步小型化、薄型化。因而，在封装内可能层叠多个半导体芯片(以下，称为芯片)。层叠的各芯片间往往通过接合线电气连接，但是近年来，开发了层叠的各芯片间通过贯通通孔连接的技术。
但是，为了通过贯通通孔连接各芯片间，必须在芯片的两主面(表面及背面)具备凸起。但是，若在芯片的两主面设置凸起，则拾取机的吸附面与凸起形成干涉。因而，吸附时在芯片产生弯曲应力。另外，芯片层叠时，向芯片施加负荷的同时将凸起彼此连接，但是此时负荷集中到凸起。其结果，在芯片产生损坏，芯片和/或芯片间的连接可靠性降低。
发明内容
本发明的实施方式提供可抑制在半导体芯片产生弯曲应力的半导体制造装置。
实施方式的半导体制造装置具备：夹具(collet)，其吸附在主面形成有凸起的半导体芯片；和驱动机构，其驱动夹具，使吸附的半导体芯片在安装基板或者其他半导体芯片上载置。夹具在半导体芯片的吸附面设有用于避免与凸起抵接的凹部。
附图说明
图1(a)～(b)是实施方式的半导体制造装置的构成图。
图2(a)～(b)是实施方式的半导体制造装置具备的夹具的构成图。
图3是实施方式的夹具吸附了芯片的截面图。
图4是比较例的夹具吸附了芯片的截面图。
图5是半导体芯片的俯视图。
图6是实施方式的夹具吸附芯片时的变形量的示图。
图7是比较例的夹具吸附芯片时的变形量的示图。
标号说明：
100…半导体制造装置，110，110A…夹具，110R…背面，110a…孔，111…沟，112…凹部，112a…弹性体，113…加热器，120…驱动机构，B…凸起，C…芯片，M…安装基板。
具体实施方式
以下，参照图1到图7说明半导体装置的制造方法及半导体造装置的实施方式。另外，各实施方式中，基本相同的构成部位附上相同的符号，说明省略。但是，图面是示意图，厚度和平面尺寸的关系、各层的厚度的比率等不同于现实。说明中表示上下等的方向的用语指示以后述的半导体基板的电路形成面侧为上时的相对方向，可能不同于以重力加速度方向为基准的现实的方向。
(实施方式)
图1是实施方式的半导体制造装置100的构成图。半导体制造装置100是将半导体芯片(以下，称为芯片)与安装基板和/或其他芯片进行倒装芯片连接的倒装芯片接合机。
半导体制造装置100至少具备：真空吸附芯片C的夹具110；驱动夹具110，使在夹具110真空吸附的芯片C在安装基板M或者其他芯片C上载置的驱动机构120。半导体制造装置100通过真空吸附拾取芯片C(参照图1(a))，将该拾取的芯片C在安装基板M或者其他芯片C上安装(参照图1(b))。
芯片C的两主面(表面及背面)设有连接用的凸起B。另外，两主面的凸起B通过没有图示的贯通通孔电连接。该实施方式中，通过将在两主面设置的凸起B彼此连接，使芯片C层叠并电连接。另外，如图1(b)所示，层叠的芯片C中，对于以安装基板M的相反侧为上时的最上级层叠的芯片C，可以省略顶面侧的凸起B。
图2是夹具110的构成图。图2(a)是夹具110的俯视图(背面侧)，图2(b)是图2(a)的线段X-X中的夹具110的截面图。如图2(a)所示，夹具110的背面110R配合芯片C的形状，在俯视图中形成矩形状。夹具110的背面110R成为芯片C的吸附面，设有用于真空吸附芯片C的沟111。
如图2(b)所示，在夹具110内部，设有与在背面110R设置的沟111连通的孔110a。该孔110a与没有图示的真空泵连接。通过对孔110a抽真空，可以在夹具110的背面110R真空吸附芯片C。
而且，在夹具110的背面110R，设有用于与芯片C的凸起B抵接的凹部112。图2(a)中，凹部112设置在背面110R的周围及中央，但是设置凹部112的位置任意，可以根据设置在芯片C的凸起B的位置适宜变更。
凹部112内设有弹性体112a。通过在凹部112内设置弹性体112a，可以抑制在芯片C产生弯曲应力，向芯片C充分施加压力。为了使后述的加热器113的热向芯片C传递，弹性体112a优选采用热传导率性及耐热性高的材料，例如硅树脂和/或氟树脂、乙烯-乙酸乙烯基酯等的橡胶或这些的泡沫材料。另外，弹性体112a表面和背面110R形成近似平坦。
弹性体112a的厚度T优选在10μm以上50μm以下。弹性体112a过厚，则热难以传递到芯片C。弹性体112a过薄，则难以抑制在芯片C产生弯曲应力。另外，即使在没有弹性体112a的状态下也可以向芯片C充分施加压力时，弹性体112a不一定是必要的。
夹具110内，内置镍铬合金线和/或陶瓷等的没有图示的加热器。通过对加热器通电，夹具110被加热到100～300℃左右。将芯片C在安装基板M和/或其他芯片C上安装时，在向芯片C施加向下的压力的状态下，通过上述加热器113进行加热。该加热使焊料熔化，连接芯片C的凸起B。
图3是在夹具110吸附芯片C的截面图。图4是在比较例的夹具110A吸附芯片C的截面图。图3中，在夹具110的背面110R设置用于与芯片C的凸起B抵接的凹部112。通过该凹部112，夹具110和凸起B不直接抵接。另外，通过弹性体112a，吸收并缓和由凸起B产生的应力。因而，可以抑制在芯片C产生弯曲应力。
另一方面，图4中，在夹具110的背面110R没有设置用于与芯片C的凸起B抵接的凹部112。因而，夹具110和凸起B直接抵接，在芯片C产生弯曲应力。
如上所述，半导体制造装置100具备：真空吸附在主面设有凸起B的芯片C的夹具110；驱动夹具110，使真空吸附的芯片C在安装基板M或者其他芯片C上载置的驱动机构120。夹具110在芯片C的吸附面即背面110R设有用于避免与凸起B抵接的凹部112。因而，可以抑制在芯片C产生弯曲应力。
另外，凹部112内设有弹性体112a。因而，芯片C进行倒装芯片连接时，可以向芯片C施加充分压力。因而，凸起连接的可靠性提高。
而且，弹性体112a的厚度T设为10μm以上，因此，可以抑制在芯片C产生弯曲应力。另外，弹性体112a的厚度T设为50μm以下，因此，可以抑制热难以传递到芯片C的情况。因而，芯片C的连接可靠性进一步提高。
接着，说明实施方式。该实施方式中，在参照图2说明的为了避免与凸起抵接而在背面设有凹部的夹具(实施方式)和没有设置用于避免与凸起抵接的凹部的夹具(比较例)中，测定芯片吸附时的芯片的变形量。另外，实施方式的夹具的凹部没有填充弹性体。
图5是芯片的俯视图。图5用实线及虚线表示测定芯片的变形量的处所。如图5所示，该实施方式中，沿芯片的对角线测定芯片的变形量。
图6表示用实施方式的夹具(有凹部)吸附时的芯片的变形量。另外，图6中，图5中实线表示的对角线的变形量用实线表示，虚线表示的对角线的变形量用虚线表示。如图6所示，实施方式的夹具中，由于凹部，在芯片设置的凸起与夹具不抵接。因而，芯片的变形量在凸起存在的区域(0-2μm及10-12μm)中抑制为3μm左右。
图7表示用比较例的夹具(无凹部)吸附时的芯片的变形量。图7中，图5中实线表示的对角线的变形量用实线表示，虚线表示的对角线的变形量用虚线表示。如图7所示，比较例的夹具中，由于无凹部，在芯片设置的凸起与夹具抵接，在芯片产生弯曲应力。因而，芯片的变形量在凸起存在的区域(0-2μm及10-12μm)中急剧上升。
如上所述，该实施方式中，通过在夹具的芯片吸附面(背面)设置用于避免与凸起抵接的凹部，可以有效抑制在芯片产生弯曲应力。
虽然说明了本发明的几个实施方式，但是各实施方式所示的构成不限于各种条件，这些实施方式只是例示，而不是限定发明的范围。这些新实施方式可以各种形态实施，在不脱离发明的要旨的范围，可以进行各种省略、置换、变更。这些实施方式及其变形是发明的范围和要旨所包含的，也是权利要求书记载的发明及其均等的范围所包含的。

Claims (4)

1.一种半导体制造装置，其特征在于，具备：
夹具，其吸附在主面形成有凸起的半导体芯片；和
驱动机构，其驱动上述夹具，使吸附的上述半导体芯片在安装基板或者其他半导体芯片上载置，
上述夹具在上述半导体芯片的吸附面设有凹部，
在上述凹部内设有厚度为10μm以上且50μm以下的弹性体。
2.一种半导体制造装置，其特征在于，具备：
夹具，其真空吸附在主面设有凸起的半导体芯片；和
驱动机构，其驱动上述夹具，使真空吸附的上述半导体芯片在安装基板或者其他半导体芯片上载置，
上述夹具在上述半导体芯片的吸附面设有避免与上述凸起抵接的凹部。
3.根据权利要求2所述的半导体制造装置，其特征在于，
在上述凹部内设有弹性体。
4.根据权利要求3所述的半导体制造装置，其特征在于，
上述弹性体的厚度为10μm以上且50μm以下。
CN201410006086.9A 2013-09-09 2014-01-07 半导体制造装置 Pending CN104425312A (zh)

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CN109727903A (zh) * 2017-10-31 2019-05-07 上海微电子装备（集团）股份有限公司 吸附组件、键合片拆解装置与方法，和半导体封装系统

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