CN102148206A - 半导体装置封装件及其制造方法 - Google Patents

半导体装置封装件及其制造方法 Download PDF

Info

Publication number
CN102148206A
CN102148206A CN2011100216214A CN201110021621A CN102148206A CN 102148206 A CN102148206 A CN 102148206A CN 2011100216214 A CN2011100216214 A CN 2011100216214A CN 201110021621 A CN201110021621 A CN 201110021621A CN 102148206 A CN102148206 A CN 102148206A
Authority
CN
China
Prior art keywords
chip
substrate
bridging
semiconductor device
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011100216214A
Other languages
English (en)
Other versions
CN102148206B (zh
Inventor
张效铨
蔡宗岳
赖逸少
郑明祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN102148206A publication Critical patent/CN102148206A/zh
Application granted granted Critical
Publication of CN102148206B publication Critical patent/CN102148206B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/30154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/30155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3018—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/30181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73151—Location prior to the connecting process on different surfaces
    • H01L2224/73153—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体装置封装件及其制造方法。半导体装置封装件包括基板、缓冲结构、二主动芯片及桥接芯片。基板具有凹部及相对的第一面与第二面。凹部从第一面往第二面延伸，缓冲结构设于凹部。二主动芯片机械性地设置于且电性连接于第一面，二主动芯片环绕凹部，其中，二主动芯片皆具有第一主动面。桥接芯片设于凹部及缓冲结构之上，其中桥接芯片具有第二主动面，第二主动面面向第一主动面且部分地重迭于第一主动面，桥接芯片用以提供二主动芯片之间的相邻通信。

Description

半导体装置封装件及其制造方法
技术领域
本发明是有关于一种装置封装件，且特别是有关于一种半导体装置封装件。
背景技术
目前来讲，半导体技术应用于不胜枚举的产品，例如是存储卡、计算机、移动电话、监视器等。由于半导体组件的尺寸细微及脆弱特性，半导体工艺对精密度要求较高。因此，如果发生错误，每个步骤严格地被监控。然而，即使半导体相关产品的良率及质量有限，客户对产品功能的要求仍逐渐地提高。
在制造上，半导体装置封装件在芯片受到应力时，容易因为封装的芯片的裂缝而损坏。芯片的裂缝大多因为加工细微特征或由于芯片的易脆特性而导致。因此有必要去寻求以上问题的解决方法。
发明内容
本发明有关于一种半导体装置封装件及其制造方法。半导体装置封装件具有缓冲结构，其用以控制芯片与基板之间的间隙，以及吸收对芯片的冲击，可避免芯片的损坏，因此提升相关产品的良率及质量。
根据本发明第一方面，提出一种半导体装置封装件。半导体装置封装件包括一基板、一缓冲结构(buffer structure)、二主动芯片及一桥接芯片(bridge chip)。基板具有一凹部及相对的一第一面与一第二面，其中，凹部从第一面往第二面延伸。缓冲结构设于凹部。二主动芯片机械性地设置于且电性连接于第一面，二主动芯片环绕凹部，其中，二主动芯片皆具有一第一主动面。桥接芯片设于凹部及缓冲结构之上，其中桥接芯片具有一第二主动面，第二主动面面向第一主动面且部分地重迭于第一主动面，桥接芯片用以提供二主动芯片之间的一相邻通信(proximitycommunication)。
根据本发明第二方面，提出一种半导体装置封装件的制造方法。制造方法包括以下步骤。提供一芯片组件，该芯片组件包括二主动芯片及一桥接芯片，其中该桥接芯片具有一主动面，该主动面各别地面向且部分地重迭于二主动芯片的数个主动面，藉以提供二主动芯片之间的一相邻通信；形成一发泡材料于一基板或该桥接芯片的一背面；机械性地且电性地连接二主动芯片至基板，以使发泡材料设于基板与桥接芯片的背面之间；以及，经由加热基板，扩张发泡材料以形成一缓冲结构填满基板与桥接芯片之间的间隙。
为让本发明的上述内容能更明显易懂，下文特举实施例，并配合附图，作详细说明如下：
附图说明
图1绘示依照本发明一实施例的半导体装置封装件的示意图。
图2绘示依照本发明另一实施例的半导体装置封装件的示意图。
图3绘示依照本发明再一实施例的半导体装置封装件的示意图。
图4绘示依照本发明一实施例的半导体装置封装件的制造方法流程图。
图5A至5C绘示图1的半导体装置封装件的制造步骤。
图6A至6C绘示图2的半导体装置封装件的制造步骤。
主要组件符号说明：
100、200、200′：半导体装置封装件
100a、200a：芯片组件
101、201：基板
101a、201a：第一面
101b、201b：第二面
103、203：缓冲结构
103a、203a：发泡材料
105、107、205、207：主动芯片
105a、107a、109a、205a、207a、209a：信号接垫
109、209：桥接芯片
109b：背面
111：凹部
113、115、215、217：黏贴层
117a、119a：焊块
121、123、125、221、223、225：主动面
211、213：柱体组
219：底胶
203a′：缓冲突部
具体实施方式
图1绘示依照本发明一实施例的半导体装置封装件的示意图。半导体装置封装件100包括一基板101、一缓冲结构103、二主动芯片105、107及一桥接芯片109。基板101具有一凹部111及相对的一第一面101a与一第二面101b。凹部111从第一面101a往第二面101b延伸，且缓冲结构103设于凹部111。主动芯片105及107机械性地设于第一面101a且连接于第一面101a，主动芯片105及107环绕凹部111。主动芯片105及107皆具有一主动面。桥接芯片109设于凹部111及缓冲结构103之上。桥接芯片109具有一主动面，其面向主动芯片105及107的主动面且部分地重迭于主动芯片105及107的主动面。因此，桥接芯片109可用以提供主动芯片105与107之间的相邻通信(proximity communication)。
缓冲结构103包括一发泡材料(vesicant material)，其较佳地一热固性材料(thermosetting material)。例如，发泡材料隙一热移除胶(heat release tape)。特别地，热移除胶Revalpha#3195MS热移除胶。其结合强度在约90℃至约150°C之间时降低，Revalpha#3195MS热移除胶来自于日本大阪的Nitto Denko。缓冲结构103可帮助控制主动芯片105与107之间的间隙、避免桥接芯片109在制造过程中直接接触基板101以及支撑桥接芯片109。
如图1所示，半导体装置封装件100包括二黏贴层113及115。黏贴层113设于主动芯片105与桥接芯片109之间，而黏贴层115设于主动芯片107与桥接芯片109之间。黏贴层113及115用以结合主动芯片105、107与桥接芯片109。黏贴层113及115由底胶(underfill)组成。在一实施例，黏贴层113及115可包括阻隔球(spacer ball)以帮助控制主动芯片与桥接芯片之间的间隙。以电容耦接(capacitivecoupling)的传送为例，主动芯片105及107皆具有数个信号接垫，例如是信号接垫105及107a，其至少部分地且各别地对齐设于桥接芯片109上的数个信号接垫109a，如此，因为主动芯片105及107的信号接垫电容或电感耦合于桥接芯片109的信号接垫，而提供主动芯片105、107与桥接芯片109之间的信号通信，主动芯片105及107的一对信号接垫与桥接芯片109之间产生电容效应。电容耦合提供主动芯片105与桥接芯片109之间及主动芯片107与桥接芯片109之间的信号路径。一信号接垫的表面金属的电位能改变导致包括对应的信号接垫的金属的电位能改变。个别芯片的适当的传送电路的驱动器及接受电路的感测电路可透过尽可能小的电容产生通信。
如图1所示，主动芯片105及107分别透过焊块(solder bump)117a及119a机械性地且电性地连接至基板101的第一面101a上的触点或接垫(未绘示)。芯片与基板之间的间隙被底胶117及119密封，藉以强化及稳地芯片与基板之间的连接以及增加芯片与基板之间焊料的接合可靠度。
此外，主动芯片105及107透过金属凸块可机械性地且电性地连接至第一面101a，金属凸块于芯片的接合接垫与及异方性导电胶膜(anisotropic conductiveadhesive film，ACF)的接合过程中预形成。适于形成异方性导电胶膜的一种异方性黏剂一般z轴异方性黏剂(z-axis anisotropic adhesive)。z轴异方性黏剂由导电粒子填充至一低阶层(low level)，以使粒子不沿xy平面接触。因此，材料沿z方向压缩后建立电性路径。
图2绘示依照本发明另一实施例的半导体装置封装件的示意图。半导体装置封装件200包括基板201、缓冲结构203、二主动芯片205及207、桥接芯片209及二柱体组211及213。基板201具有相对的第一面201a与第二面201b。缓冲结构203设于第一面201a。柱体组211及213分别设于缓冲结构203的二侧，且柱体组211与213中每一者具有数个柱体。柱体组211与213的该些柱体可以是由铜、银、金等制成的导电柱。
主动芯片205及207设于柱体组211及213且经由柱体组211及213电性连接于第一面201a。主动芯片205及207皆具有主动面。主动芯片205及207分别具有数个信号接垫，例如是信号接垫205a及207a。桥接芯片209设于缓冲结构203及主动芯片205及207的下。桥接芯片209具有一主动面及数个信号接垫209a。桥接芯片209的主动面面向主动芯片205及207的主动面且信号接垫205a及207a对齐位于桥接芯片209的主动面上的信号接垫209a，以使桥接芯片209可提供主动芯片205与207之间的相邻通信。
如图2所示，半导体装置封装件200包括二黏贴层215及217。黏贴层215设于主动芯片205与桥接芯片209之间，用以结合主动芯片205与桥接芯片209。黏贴层217设于主动芯片207与桥接芯片209之间，用以结合主动芯片207与桥接芯片209。黏贴层215及217由底胶材料所形成。在一实施例，黏贴层215及217可包括阻隔球以帮助控制主动芯片与桥接芯片之间的间隙。
半导体装置封装件200包括底胶219。底胶219设于柱体组211、213与基板201之间且填充于柱体组211及213内的空间。底胶219用以提升柱体组211及213连接至基板201的连接性以及保护柱体组211及213的柱体。
上述所揭露的缓冲结构层结构，然本发明实施例不限于此。图3绘示依照本发明再一实施例的半导体装置封装件的示意图。半导体装置封装件200’与半导体装置封装件200不同之处在于缓冲结构，而相同组件使用相同标号，不重复赘述。缓冲结构203’包括数个缓冲部(knob)203a’。桥接芯片209设于缓冲突部203a’上。
图4绘示依照本发明一实施例的半导体装置封装件的制造方法流程图。制造方法包括步骤S11至S14且描述图1的半导体装置封装件100的制造过程。图5A至5C绘示图1的半导体装置封装件100的制造步骤。
首先，于步骤S11中，如图5A所示，提供芯片组件100a。芯片组件100a包括二主动芯片105及107及桥接芯片109。其中，桥接芯片109具有一主动面125，其面向且部分地重迭于主动芯片105及107的主动面121及123，藉以提供主动芯片105与107之间的相邻通信。主动芯片105及107透过二黏贴层113及115连接至桥接芯片109。
接着，于步骤S12中，如图5A所示，发泡材料103a形成于基板101，或者发泡材料103a形成于桥接芯片109的背面109b。基板101具有凹部111，其用以容纳桥接芯片109。较佳地，发泡材料103a涂布于易定位的凹部111。
接着，于步骤S13中，如图5B所示，主动芯片105及107机械地且电性地连接至基板101，使发泡材料103a设于基板101与桥接芯片109的背面109b之间。本步骤一开始，倒置芯片组件100a(绘示于图5A)，且在连接主动芯片105及107至基板101之前，将桥接芯片109对齐凹部111。在桥接芯片109位于凹部111之后，执行回焊(reflow)工艺以熔化预形成于主动芯片105及107上的焊块117a及119a，以形成一相对应的芯片上的接垫或触点与基板之间的焊接合，藉以机械性地且电性地设置主动芯片105及107至基板101。并且，主动芯片105、107及基板101之间的间隙受到底胶117及119的密封，藉以强化及稳定芯片与基板之间的连接以及增加芯片与基板之间焊料的接合可靠度。
接着，于步骤S14中，经由加热基板101，扩张发泡材料103a，以形成缓冲结构103填满基板101与桥接芯片109之间的间隙，如图5C所示。至此，完成半导体装置封装件100的制造。
图6A至6C绘示图2的半导体装置封装件100的制造步骤。如图6A所示，提供芯片组件200a。芯片组件200a包括二主动芯片205及207及桥接芯片209。其中，桥接芯片209具有一主动面225，其面向且部分地重迭于主动芯片205及207的主动面221及223，藉以提供主动芯片205与207之间的相邻通信。主动芯片205及207透过二黏贴层215及217连接至桥接芯片109。芯片组件200a更包括二柱体组211及213，其分别设于主动经片205及207，且位于桥接芯片209的二侧。
接着，一发泡材料203a形成于基板201的第一面201。
接着，主动芯片205及207机械性地且电性地连接于基板201，使发泡材料203a设于基板201与桥接芯片209之间，且二柱体组211及213位于发泡材料203a及桥接芯片209的二侧。
接着，经由加热基板201，扩张发泡材料203a，以形成缓冲结构203填充基板201与桥接芯片209之间的间隙，如图6B所示。
接着，提供一底胶材料填充柱体组211及219内的空间，以形成底胶219，如图6C所示，藉以提升柱体组211及219连接至基板201的结合性，以及保护柱体组211及219的该些柱体。至此，完成半导体装置封装件200的制造。图3的半导体装置封装件200’的制造相似于半导体装置封装件200的制造，容此不再重复赘述。
本发明上述实施例的半导体装置封装件及其制造方法，半导体装置封装件具有一缓冲结构填充桥接芯片与基板之间的间隙，以提供桥接芯片的支撑，避免桥接芯片直接接触基板，因此消除作用于桥接芯片的作用力导致半导体装置封装件的应力发生的可能性。此外，缓冲结构可形成一层或数个缓冲突部，其可吸收对桥接芯片的机械冲击。如此一来，可提升半导体装置封装件的质量及良率。
综上所述，虽然本发明已以实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (10)

1.一种半导体装置封装件，包括：
一基板，具有一凹部及相对的一第一面与一第二面，其中，该凹部从该第一面往该第二面延伸；
一缓冲结构，设于该凹部；
二主动芯片，机械性地设置于且电性连接于该第一面，其中，该二主动芯片皆具有一第一主动面；以及
一桥接芯片，设于该凹部及该缓冲结构之上，其中该桥接芯片具有一第二主动面，该第二主动面面向该第一主动面且部分地重迭于该第一主动面，该桥接芯片用以提供该二主动芯片之间的一相邻通信。
2.如权利要求1所述的半导体装置封装件，其中该缓冲结构包括一发泡材料。
3.如权利要求2所述的半导体装置封装件，其中该发泡材料一热固型材料。
4.如权利要求1所述的半导体装置封装件，其中该缓冲结构包括数个突部。
5.如权利要求1所述的半导体装置封装件，更包括：
数个焊块，设于该二主动芯片与该第一面之间。
6.如权利要求1所述的半导体装置封装件，其中各该二主动芯片包括一第一信号接垫，该第一信号接垫设于该第一主动面，该桥接芯片包括二第二信号接垫，该二第二信号接垫设于该第二主动面且电容耦合或电感耦合于该些第一信号接垫。
7.一种半导体装置封装件的制造方法，包括：
提供一芯片组件，该芯片组件包括二主动芯片及一桥接芯片，其中该桥接芯片具有一主动面，该主动面面向且部分地重迭于该二主动芯片的数个主动面，藉以提供该二主动芯片之间的一相邻通信；
形成一发泡材料于一基板或该桥接芯片的一背面；
机械性地且电性地连接该二主动芯片至该基板，以使该发泡材料设于该基板与该桥接芯片的该背面之间；以及
经由加热该基板，扩张该发泡材料以形成一缓冲结构填满该基板与该桥接芯片之间的间隙。
8.如权利要求7所述的制造方法，其中该基板更具有一凹部，该发泡材料涂布于该凹部。
9.如权利要求7所述的制造方法，其中该芯片组件更包括：
二柱体组，设于该二主动芯片且位于该桥接芯片的二侧，该发泡材料位于该二柱体组之间。
10.如权利要求9所述的制造方法，其中于连接该二主动芯片至该基板的该步骤之后，该制造方法更包括：
经由一底胶，填充该二柱体组内的空间。
CN2011100216214A 2010-03-29 2011-01-04 半导体装置封装件及其制造方法 Active CN102148206B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/749,191 US8274149B2 (en) 2010-03-29 2010-03-29 Semiconductor device package having a buffer structure and method of fabricating the same
US12/749,191 2010-03-29

Publications (2)

Publication Number Publication Date
CN102148206A true CN102148206A (zh) 2011-08-10
CN102148206B CN102148206B (zh) 2013-04-03

Family

ID=44422366

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011100216214A Active CN102148206B (zh) 2010-03-29 2011-01-04 半导体装置封装件及其制造方法

Country Status (2)

Country Link
US (1) US8274149B2 (zh)
CN (1) CN102148206B (zh)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733436A (zh) * 2013-12-18 2015-06-24 英特尔公司 具有嵌入式桥的集成电路封装
CN104952838A (zh) * 2014-03-26 2015-09-30 英特尔公司 局部高密度基底布线
CN104051420B (zh) * 2013-03-14 2017-08-15 英特尔公司 用于嵌入式互连桥封装的直接外部互连
CN107210288A (zh) * 2015-02-13 2017-09-26 高通股份有限公司 并排半导体封装
CN107301978A (zh) * 2016-04-14 2017-10-27 美光科技公司 具有多个共面中介元件的半导体封装
US9831169B2 (en) 2013-10-16 2017-11-28 Intel Corporation Integrated circuit package substrate
US9929119B2 (en) 2012-12-06 2018-03-27 Intel Corporation High density substrate routing in BBUL package
CN108292654A (zh) * 2015-12-11 2018-07-17 英特尔公司 具有利用嵌入微电子衬底中的微电子桥连接的多个微电子器件的微电子结构
US10366951B2 (en) 2012-09-28 2019-07-30 Intel Corporation Localized high density substrate routing
CN110176445A (zh) * 2016-01-27 2019-08-27 艾马克科技公司 电子装置

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7969009B2 (en) * 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
US8368216B2 (en) * 2010-08-31 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor package
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
US8742576B2 (en) * 2012-02-15 2014-06-03 Oracle International Corporation Maintaining alignment in a multi-chip module using a compressible structure
US9236366B2 (en) 2012-12-20 2016-01-12 Intel Corporation High density organic bridge device and method
US9147663B2 (en) 2013-05-28 2015-09-29 Intel Corporation Bridge interconnection with layered interconnect structures
US9041205B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Reliable microstrip routing for electronics components
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9396300B2 (en) * 2014-01-16 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof
KR101595216B1 (ko) * 2014-03-14 2016-02-26 인텔 코포레이션 로컬화된 고밀도 기판 라우팅
US9583426B2 (en) 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US10074630B2 (en) * 2015-04-14 2018-09-11 Amkor Technology, Inc. Semiconductor package with high routing density patch
US10283492B2 (en) 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects
US9595495B1 (en) * 2015-09-28 2017-03-14 Altera Corporation Multi-level signaling for on-package chip-to-chip interconnect through silicon bridge
US9852994B2 (en) 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges
KR102632563B1 (ko) * 2016-08-05 2024-02-02 삼성전자주식회사 반도체 패키지
WO2018125080A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Enabling long interconnect bridges
US10580738B2 (en) 2018-03-20 2020-03-03 International Business Machines Corporation Direct bonded heterogeneous integration packaging structures
US11848272B2 (en) * 2021-08-16 2023-12-19 International Business Machines Corporation Interconnection between chips by bridge chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030042589A1 (en) * 2001-08-30 2003-03-06 Joon Ki Hong Stack chip module
US6731015B2 (en) * 2001-08-01 2004-05-04 Siliconware Precision Industries Co., Ltd. Super low profile package with stacked dies
CN101232008A (zh) * 2007-01-03 2008-07-30 育霈科技股份有限公司 多晶粒封装及其方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070158826A1 (en) * 2005-12-27 2007-07-12 Yamaha Corporation Semiconductor device
US20080197474A1 (en) * 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
JP2009135221A (ja) * 2007-11-29 2009-06-18 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法ならびに半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6731015B2 (en) * 2001-08-01 2004-05-04 Siliconware Precision Industries Co., Ltd. Super low profile package with stacked dies
US20030042589A1 (en) * 2001-08-30 2003-03-06 Joon Ki Hong Stack chip module
CN101232008A (zh) * 2007-01-03 2008-07-30 育霈科技股份有限公司 多晶粒封装及其方法

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12107042B2 (en) 2012-09-28 2024-10-01 Intel Corporation Localized high density substrate routing
US10796988B2 (en) 2012-09-28 2020-10-06 Intel Corporation Localized high density substrate routing
US10366951B2 (en) 2012-09-28 2019-07-30 Intel Corporation Localized high density substrate routing
US11515248B2 (en) 2012-09-28 2022-11-29 Intel Corporation Localized high density substrate routing
US11984396B2 (en) 2012-09-28 2024-05-14 Intel Corporation Localized high density substrate routing
US10438915B2 (en) 2012-12-06 2019-10-08 Intel Corporation High density substrate routing in package
US10199346B2 (en) 2012-12-06 2019-02-05 Intel Corporation High density substrate routing in package
US9929119B2 (en) 2012-12-06 2018-03-27 Intel Corporation High density substrate routing in BBUL package
US10861815B2 (en) 2012-12-06 2020-12-08 Intel Corporation High density substrate routing in package
US11251150B2 (en) 2012-12-06 2022-02-15 Intel Corporation High density substrate routing in package
CN104051420B (zh) * 2013-03-14 2017-08-15 英特尔公司 用于嵌入式互连桥封装的直接外部互连
US10325843B2 (en) 2013-10-16 2019-06-18 Intel Corporation Integrated circuit package substrate
US9831169B2 (en) 2013-10-16 2017-11-28 Intel Corporation Integrated circuit package substrate
US10770387B2 (en) 2013-10-16 2020-09-08 Intel Corporation Integrated circuit package substrate
US10068852B2 (en) 2013-12-18 2018-09-04 Intel Corporation Integrated circuit package with embedded bridge
US9716067B2 (en) 2013-12-18 2017-07-25 Intel Corporation Integrated circuit package with embedded bridge
CN104733436A (zh) * 2013-12-18 2015-06-24 英特尔公司 具有嵌入式桥的集成电路封装
CN104952838A (zh) * 2014-03-26 2015-09-30 英特尔公司 局部高密度基底布线
CN107210288A (zh) * 2015-02-13 2017-09-26 高通股份有限公司 并排半导体封装
CN111883519A (zh) * 2015-02-13 2020-11-03 高通股份有限公司 并排半导体封装
US11075166B2 (en) 2015-12-11 2021-07-27 Intel Corporation Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate
CN108292654A (zh) * 2015-12-11 2018-07-17 英特尔公司 具有利用嵌入微电子衬底中的微电子桥连接的多个微电子器件的微电子结构
CN110176445A (zh) * 2016-01-27 2019-08-27 艾马克科技公司 电子装置
CN110176445B (zh) * 2016-01-27 2023-09-01 艾马克科技公司 电子装置
US10529689B2 (en) 2016-04-14 2020-01-07 Micron Technology, Inc. Semiconductor package with multiple coplanar interposers
US11469210B2 (en) 2016-04-14 2022-10-11 Micron Technology, Inc. Semiconductor package with multiple coplanar interposers
CN107301978B (zh) * 2016-04-14 2018-08-03 美光科技公司 具有多个共面中介元件的半导体封装
CN107301978A (zh) * 2016-04-14 2017-10-27 美光科技公司 具有多个共面中介元件的半导体封装

Also Published As

Publication number Publication date
US20110233764A1 (en) 2011-09-29
CN102148206B (zh) 2013-04-03
US8274149B2 (en) 2012-09-25

Similar Documents

Publication Publication Date Title
CN102148206B (zh) 半导体装置封装件及其制造方法
KR100408616B1 (ko) 반도체 장치, 전자 기기의 제조 방법, 전자 기기 및 휴대정보 단말
KR100299885B1 (ko) 반도체장치및그의제조방법
KR102245003B1 (ko) 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
KR100698527B1 (ko) 금속 범프를 이용한 기둥 범프를 구비하는 칩 적층 패키지및 그의 제조방법
KR20090018852A (ko) 반도체 패키지, 그 제조 방법, 반도체 장치 및 전자 기기
CN105280577A (zh) 芯片封装结构以及芯片封装结构的制作方法
CN102136434A (zh) 在引线键合的芯片上叠置倒装芯片的方法
CN101388383A (zh) 半导体封装及其制造方法
US20220352121A1 (en) Semiconductor package having passive support wafer
JPWO2006070863A1 (ja) 半導体チップの実装構造体およびその製造方法
TW451376B (en) Production of semiconductor device
US20110073357A1 (en) Electronic device and method of manufacturing an electronic device
US8217517B2 (en) Semiconductor device provided with wire that electrically connects printed wiring board and semiconductor chip each other
WO2012171320A1 (zh) 一种新的接触式智能卡的封装方法
US7821139B2 (en) Flip-chip assembly and method of manufacturing the same
CN106486457B (zh) 芯片载体、器件及方法
US20120049360A1 (en) Semiconductor Package And Method For Making The Same
US20070216003A1 (en) Semiconductor package with enhancing layer and method for manufacturing the same
CN113851437B (zh) 倒装芯片和芯片封装结构
JP2001345418A (ja) 両面実装構造体の製造方法及びその両面実装構造体
JP2004094839A (ja) Ｒｆｉｄタグ
CN111554628B (zh) 一种芯片封装方法
JP3753984B2 (ja) 非接触通信機器用モジュール及びその製造方法
CN108288608B (zh) 芯片封装体及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant