CN101232008A - 多晶粒封装及其方法 - Google Patents

多晶粒封装及其方法 Download PDF

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CN101232008A
CN101232008A CNA2008100000275A CN200810000027A CN101232008A CN 101232008 A CN101232008 A CN 101232008A CN A2008100000275 A CNA2008100000275 A CN A2008100000275A CN 200810000027 A CN200810000027 A CN 200810000027A CN 101232008 A CN101232008 A CN 101232008A
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crystal grain
rdl
dielectric layer
substrate
grain
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杨文焜
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Abstract

本发明提出一多晶粒封装结构，其包含一基板具有容纳凹槽于其上表面中，与一第一通孔结构其中之终端接点于第一通孔之下，一第一晶粒放置于容纳凹槽，且一第一介电层形成于第一晶粒与基板之上，一第一重布导电层(RDL)形成于第一介电层之上。一第二介电层形成于第一RDL之上，一第三介电层形成于一第二晶粒之下，一第二重布导电层(RDL)形成于第三导电层之下，一第四介电层形成于此第二RDL之下。导电凸块接合此第一RDL与此第二RDL，一围阻材料环绕于此第二晶粒，此第二晶粒藉由此第一RDL、第二RDL以及此导电凸块，导通至此第一晶粒。

Description

多晶粒封装及其方法
技术领域
本发明系关于一种系统级封装(SIP)结构，尤系指一平板尺寸封装(PSP)之系统级封装
背景技术
于半导体组件领域，组件密度持续地增加且组件尺寸持续地缩小，封装或连结技术于上述之高密度组件上，日益重要。传统之覆晶黏着方式一数组锡凸块形成于晶粒表面上，锡凸块之构成，藉由使用一含锡之复合材料，经由钢板制作一意欲之锡凸块图案。芯片封装之功能包含功率分配、讯号分配、散热、保护以及芯片支撑。当半导体芯片变得更复杂时，传统封装方式，例如导线架封装、软板封装以及硬板封装技术，便无法应付更小尺寸、更高密度之IC封装需求。
现今之多晶粒模块或混合电路，一般而言，将晶粒黏着于一机板上且密封于一外壳中。此一般使用一多层基板，其中包含多层导线与界电层以三明治结构形成。多层基板传统上以迭片技术制作，其中金属导体各自形成于介电层上，接着将之堆栈并连结。
为满足高密度、高性能速度需求，故而发展系统单芯片(SIP)与系统级封装(SIP)，而多晶粒模块广泛应用于多种功能芯片整合。多晶粒模块或多晶粒封装技术，提供多个黏着未封装集成电路(IC)(“裸晶”)方式于一基材上，其多个晶粒被”封装”于一整个密封材料或其它聚合物，多晶粒模块提供一高密度模块，其于计算机主板需求面积小，多晶粒模块亦提供整合性功能测试之好处。
更进一步，因为传统封装技术必须将晶圆切割成为个别晶粒，再各自封装，此技术于制程中消耗大量时间。因为芯片封装技术受到集成电路研发影响甚巨，故而当电路之面积成为必要，封装技术亦受其影响。由于以上所述，封装技术由球状矩阵(BGA)、倒装芯片(FC-BGA)、芯片尺寸级封装(CSP)演进至今日之晶圆尺寸级封装(WLP)。“晶圆尺寸级封装”顾名思义，整个封装与其晶圆上之内部联机，以及其它制程步骤，皆完成于分割(切割)成为芯片(晶粒)前。一般而言，当完成整个组装制程或封装制程后，单个的半导体封装于晶圆上被分开，成为多个半导体晶粒，此晶圆尺寸级封装具有极小面积，并具有极佳之电器特性。
晶圆尺寸级封装技术为一种先进封装技术，其晶粒于晶圆上同时制造并测试，其后将其切割分开并组装用于表面黏着产线。因为晶圆尺寸级封装技术利用整个晶圆，并非使用单颗芯片或晶粒，因此于执行切削制程前，封装与测试业已完成，更进一步，晶圆尺寸级封装技术之先进，使得打线、黏晶与填充等制程可省略。使用晶圆尺寸级封装技术，可降低制造成本，其尺寸与晶粒相当，此一技术可符合电子组件极小化之需求。
虽然晶圆尺寸级封装技术有上述之优点，某些因素依然影响此技术之接受度。例如，虽然晶圆尺寸级封装技术，可降低集成电路与基板连接间(增层build up layers-重布层RDL)之热膨胀系数(CTE)不匹配之影响，但是无法于芯片尺寸间允许更高球数。当组件尺寸为最小，其终端接点数将被限制。更进一步，此晶圆尺寸级封装，一复数个焊垫形成于半导体晶粒上作为重布，藉由传统重布制程，其中包含之重布层，接入一数组型态之多个金属垫。锡球直接熔接于金属垫上，藉由重布制程，其形成一数组型态。一般而言，所有堆栈之重布层形成，位于晶粒以及增层之上，因此增加封装厚度，此与降低芯片尺寸之需求相冲突。
因此本发明提出一以堆栈与相邻排列结构，作为WLP(板材晶圆)扇出之多晶粒封装。
发明内容
本发明于在其一观点中，提供一SIP封装其具有较高之可靠度以及较低之价格优势。
本发明提供一多芯片封装结构，其基板具有一芯片容纳凹槽形形成于基板之上表面，以及一通孔结构以构成电子线路，于通孔下方连结终端接点形成导通。一第一晶粒放置(黏着)于容纳槽中，一第一介电层形成于第一晶粒与此基板之上，并且将之填充入槽中晶粒与侧壁间隙。一第一重布导电层(RDL)形成于第一介电层之上，其中之第一RDL已通孔方式连结，第一芯片与终端接点。一第一介电层形成于第一RDL之上，以露出接点(其包含一金属垫层(UBM)结构，图中未显示)。一第二芯片被放置。一第三介电层形成于第二芯片之下(于主动面侧)，一第二重布导电层(RDL)形成于此第三导电层之上，其中第二RDL与此第二芯片接合。一第四介电层形成于第二RDL之下，以露出接点(其包含一金属垫层(UBM)结构，图中未显示)，导电凸块形成于第一芯片与第二芯片间，以作为结合第一介电层之接点与第二介电层之接点。此外，一包覆材料布满于第二芯片四周，可为一选择性结构设计。
此第一RDL之扇出，由此第一芯片之金属(铝)垫至终端垫，经由基板之金属通孔，并由第一晶粒耦合电气讯号。
此第二晶粒之上方结构，可以硅基之晶圆尺寸级封装制成，其具有之一增层(第二RDL)与导电凸块，其制作于晶粒切割之前。晶粒切割后，于板材晶圆制程(并与第一RDL、接点-包含UMB结构)，使用覆晶黏着方式黏着此第二晶粒(WLP-CSP)。
此外，此多芯片封装结构包含一基板，其至少具有两晶粒，且通孔结构形成导通，其中导线具有终端垫，形成于通孔结构之下。一第一晶粒与第二晶粒被放置(黏着)于至少两分开之晶粒容纳槽。一第一介电层形成于第一晶粒之上、第二晶粒与其基板间，并且将之填充入槽中晶粒边缘与侧壁间隙一第一重布导电层(RDL)形成于第一导电层之上，其中此第一RDL，藉由通孔结构，与第一晶粒、第二晶粒与终端垫接合。一第二介电层形成于第一RDL之上以裸露接点(其包含一金属垫层(UBM)结构，图中未显示)。接着为一第三晶粒，一第三介电层形成于第三晶粒之下(于主动面上)。一第二重布导电层(RDL)形成于第三介电层之下，其中其第二RDL接合至第三晶粒，一第四介电层形成于第二RDL之下，以为裸露接点(其包含一金属垫层(UBM)结构，图中未显示)。导电凸块介于此第一晶粒且/或与第二晶粒与第三晶粒间形成，藉由此第一RDL与第二RDL接合。
此第三晶粒之上方结构，其可为硅基之晶圆尺寸级封装(WLP)制成，其具有其增层(第二RDL)，且其导电凸块之制作先于晶粒切割。晶粒切割之后，于已处理之面板上(具有第一RDL与接点-包含其金属垫层UBM结构)以覆晶黏着方式黏着此第二晶粒(WLP-CSP)。
此第一介电层其包含一弹性介电层。另一实施方式，此第一与第二介电层包含一硅基介电材料，苯环丁烯BCB或聚亚酰胺(PI)，其中之硅基介电材料其包含硅氧烷高分子(SINR)，道康宁(Dow Corning)WL5000系列或其复合物。其第一与第二介电层可包含一光敏(光图形转移photo-patternable)层。
此基板之材料包含环氧树脂型之FR5、FR4、BT等PCB(印刷电路板)、合金、玻璃、硅、陶瓷或金属。另一方式，此基板材料包含合金42(Alloy42)(42％镍-58％铁)。
本发明进一步提供一方法以形成半导体组件封装，包含提供一基板具有一晶粒容纳槽形成于一基板之上表面，且一通孔结构形成导通，其中之导线电路于通孔之下具有终端接点。接着至少一第一晶粒被重布，以一取放对位系统工具，使其具有设计过之线宽。黏性材料至少黏于第一晶粒之背面，且接着此基材被黏着(于真空状态)于晶粒背面，且此晶粒位于基板凹槽，藉由工具散布于板上。紧接着一第一介电层涂布于第一晶粒与此基板之上，并填入于此晶粒边缘与凹槽侧壁之间隙。一第一RDL接着形成于此第一介电层上，接着一第二介电层被形成于第一RDL上，且裸露接点与此UBM结构。一第二晶粒制作，且一第三介电层被形成于第二晶粒之下(于主动面一侧)，一第三RDL接着形成于第三介电层之下。紧接着第四介电层被形成于第二RDL之下，以形成接触金属电极(包含UBM制程)并作为此第二RDL之保护。导电凸块被形成于第一晶粒与第二晶粒间，以作为接合此第一RDL与此第二RDL，最后一围阻材料布满于第二芯片四周，可为一选择性结构设计。
于上述制程形成一第二晶粒之方法，包含一硅基晶圆具有第二晶粒。
附图说明
图1显示根据本发明之堆栈SIP之扇出结构之剖面视图
图1A为基板
图2显示根据本发明之平行(并排)SIP之扇出结构之剖面视图
图3显示根据本发明之另一堆栈SIP之扇出结构之剖面视图
图中：
2    基板
4    容纳凹槽
6    通孔
8    终端接点
8a   导电凸块
10   导电线路
12   保护层
14   黏性(黏晶)材料
18   晶粒
20   接点
22   介电层
24   第一重布传导层
24a  重布传导层
26   介电层
28a  切割道
30   第二芯片
32   介电层
34   第二重布传导层
36   第二接点
38   介电层
40   导电(焊接)凸块
42   保护层
50   上层被动组件
60   上层被动组件
70   下层芯片
具体实施方式
本发明将以较佳之实施例及观点加以详细叙述，而此类叙述系解释本发明之结构及程序，只用以说明而非用以限制本发明之申请专利范围。因此，除说明书中之较佳实施例之外，本发明亦可广泛实行于其它实施例。
本发明揭露一圆尺寸级封装(WLP)结构，利用一基板其具有预先设计通孔之电路于其中，且于基板中具一凹槽。一光敏材料覆盖于晶粒与先前之基板上，较佳之光敏材料为具弹性材料。
图1显示根据本发明之一平板级封装(panel scale package，PSP)用于系统级封装(SIP)之剖面视图，如图1所示，此系统级封装包含一基板2其具有一晶粒容纳凹槽4于其中，放置一晶粒18。此基板2可为圆形例如晶圆形状，其直径可为200、300mm或更大，其亦可为方形形状如平板状。图1显示预先成形基板2之剖面图，一切割道28a为一晶圆尺寸级封装之切割点或面。如图所示，此基板2形成一凹槽4，且具有电路10，通孔6结构由金属灌注其中。复数个通孔被建制，由基板上表面至下表面，贯穿基板2。一导电材料将被重新灌入通孔6以作为电路连结，终端接点8位于基板之下表面，且藉由导电材料与通孔6连接。一导电线路10被制作于基板2之下表面，一保护层12例如环氧树脂锡膏罩幕，形成于导电线路10上以作为保护。
晶粒18放置于此基板2之容纳凹槽4内，且以黏性(黏晶)材料14固定，一般接点(金属焊垫)形成于晶粒18之上。一光敏层或介电层22形成于晶粒18之上，且注入晶粒18与凹槽4侧壁间之空间。复数个开口以微影制程或曝光显影制程，形成于介电层22，此复数个开口各自对准接触面通孔6以及晶粒18之接触或I/O接点20。此重布层RDL24提供作为传导线路24，其以选择性移除部分介电层22，形成于介电层22之上。其中之RDL24作为晶粒18导通至I/O接点20之电气连结。藉由于通孔上之接触导通面金属以及于焊垫上之接点金属，一部份之RDL将在填入于介电层22之开口。一介电层26形成并覆盖于RDL 24，此介电层26形成于晶粒18、基板2与介电层22之顶上，复数个开口形成于介电层26中，且与RDL 24曝光部分对齐。
一第二芯片30具有第二接点36，介电材料32被形成(覆盖)于一芯片30之表面，以裸露芯片30之晶垫36，一种子金属层与第二重布传导层34，通过介电层32连接至接点36。此重布传导层34为导通连结晶粒30之用，其它介电材料38具有开口被形成(覆盖)于重布层34，以裸露重布层34接点(锡球接点)，以及保护晶粒30。此开口之制作使用传统方式且对准重布传导层34，覆晶球下金属层(UBM)形成于接点开口之上，导电(焊接)凸块40接合RDL 24与RDL 34，此结构与终端接点8为栅格数组封装(LGA)形式之SIP(系统级封装)或SIP-LGA。若是导电凸块加入，此为BGA(球栅数组)之SIP(系统级封装)或SIP-BGA。此处之表面其具有两芯片，其为相互面对面。
一保护层42覆盖于芯片30以及导电凸块之上，保护层42之材质可为环氧树脂、橡胶、树脂、塑料或陶瓷等。
其须注意，此第一芯片18可经由导电凸块40与第二芯片30、第一RDL 40与第二RDL 38导通，其配置为选择性。由此可见，此第一芯片18置于一凹槽4中，以降低整个SIP高度。此第一RDL配置为一散出形式，以增加球间距，致使增加可靠度与散热性。
此基板2之材料较佳为环氧树脂型，FR5、B一三氮树脂(Bismaleimide triazine，BT)，PCB具有被定义之凹槽或金属，合金42具有预先蚀刻之电路。有机基板其具有高玻璃转化态温度为环氧树脂型，FR5、B一三氮树脂(Bismaleimide triazine，BT)形基板其较适用，为其介电材料烘烤必须不高于基板2之玻璃转化态温度，以防止基板性质改变。其合金42之组成为42％镍与58％铁，柯华合金(Kovar)以可被使用，其组成为29％镍、17％钴、54％铁，金属铜亦可使用，而玻璃、陶瓷、硅可作为降低热膨胀系数之用。
于本发明一实施例中，此介电层22为一弹性介电材质较佳，其为硅基介电材料，包含硅氧烷高分子(SINR)，道康宁WL5000系列与其组合物，且其弹性材料可用于释放、缓冲热机械应力。于另一实施例中，此介电层可为聚亚酰胺(PI)或硅氧树脂(silicone resin)，此为一光敏层较佳，以作为简化制程。
于本发明另一实施例中，此弹性介电层22为一种CTE大于100(ppm/℃)之材料，伸长速率约为40％(30％-50％较佳)，且其硬度介于塑料与橡胶间，其中介电层22厚度，取决于温度循环测试，RDL/介电层间之应力累积。
于本发明另一实施例中，此RDL 24、34材料包含钛/铜/金之合金或钛/铜/镍/金之合金，其RDL 24之厚度由2微米至15微米，钛/铜/合金以溅度技术制成，其种子金属层亦然，且其铜/金或铜/镍/金合金由电镀方式形成，利用电镀技术制作RDL，其可使RDL之厚度，于温度循环中，足以承受CTE失配。此金属接点20、36可为铝或铜或其混合物。若此FO-WLP结构使用SINR作为弹性介电层与以铜作为RDL金属，其RDL/介电层接口之应力即可被降低。
参照图标二，此第一芯片18与此第二芯片30被放置于容纳凹槽4中，于基板2中其具有不同之尺寸，且各自固定于一黏着(黏晶)材料14与28。于图2之上半部，第一芯片18与第二芯片30并未设计为堆栈结构，此第二芯片30位于第一芯片18接邻，且两芯片藉由一横向导通线24相互连结，而非藉由通孔结构。如图所示，此基板至少包含两凹槽，以作为分别容纳第一与第二芯片。BGA封装之导电凸块8a，LGA封装之终端接点8，显示于图中。若是导电凸块省略，则其为LGA形式之SIP(系统级封装)或SIP-LGA。其它之部件类同于图1，因此其它类同之部件被省略。
此外，本实施例中之图3为结合图1与图2之观念，至少三芯片排列于SIP封装，其上层芯片30可经由RDL 24、34以及导电凸块40联通芯片18，其下层芯片18与70可经由RDL 24a接合，且其上层被动组件50与60可经由RDL 24与下层芯片70联通。
其上层芯片30具有增层与焊锡凸块，先晶粒切割制程(后晶圆制程)，其制程为晶圆级封装，且其为晶圆级晶粒尺寸封装(WLP-CSP)结构与制程。此上层芯片30可为倒置黏着方式，藉由覆晶黏晶机将之置于下层芯片(板状晶圆)之上，藉由表面黏着技术(SMT)制程之红外线回焊焊接，且其被动组件50与60可与下层芯片一并黏着。
一保护层42形成附带于此第二芯片30，此被动组件50、60以及导电凸块40为选择性结构，其保护层42之材料可为可为环氧树脂、橡胶、树脂、塑料或陶瓷等。
如图1-3所示，此晶粒扇出RDLs 24、24a，藉由通孔结构，其向下联通至终端接点8。此其不同于习知之多晶粒封装(MCP)技术，其堆栈晶粒各层，致使增加封装厚度。然而，其违反晶粒封装厚度之法则。相反地，本案其中端接点位于晶粒焊垫侧之另一面。其联通线路藉由通孔穿过基板2，且将讯号连至终端接点8，因此其晶粒封装厚度可有效之缩减，本发明之封装将薄于习知技术。进一步，其基板于封装前预先备置，此凹槽4与导线电路10亦是预先决定，因此其产能将比先前提升。本发明揭露之WLP扇出，亦无堆栈增层于RDL上。
于晶圆制程后且将其背面研磨至所欲之厚度，其晶圆切割成晶粒。其基板预先形成内建线路于其中，且至少具一凹槽。其基板材料为具有较高玻璃转化态温度Tg性质之FR5/BT印刷电路板较佳，其基板可具有不同面积之凹槽(例如，等于晶粒面积加各侧边约100微米)，以容纳不同尺寸之晶粒，且其凹槽深度大于晶粒厚度约20至30微米，以容纳黏晶材料厚度。其内部连结接点可被重布，以较适之面积放宽线宽尺寸，增加产出良率。
本发明所述之制程其包含对准工具(板)，于其上具有对准图案，接着胶水图案涂布于工具上(作为黏着晶粒表面)，接着使用精密取放对位系统，以覆晶方式将已知良裸晶粒(known good dies)以期望之间距置于工具上。其黏胶图案将芯片黏于工具上，紧接着晶粒黏着材料涂布于晶粒背面，其基板上表面除了凹槽外亦图布黏胶图案，接着真空固化其晶粒黏着材料，接着由工具与板材晶圆(板材晶圆意指其晶粒被黏着于基板之凹槽内)将其分开。晶粒黏着材料以热烘烤确保其晶粒固着于基板上。
另一方式，黏晶机以精密对位方式，且晶粒黏着材料以图布于基板凹槽内，亦即上层之覆晶芯片已放置于板材晶圆上(下层芯片具有增层)，接着回焊炉焊接覆晶与/或制程中置于板材晶圆之被动组件，其上层芯片(粒)于制程后具有一覆晶凸块结构(WLP-CSP)。
因为晶粒已于基板上重布，接着执行一清洁制程，以干式与/或湿式清洁制程，清洁晶粒表面。下一步，为涂布介电材料于板材表面，接着藉由真空程序以确保无气泡残存于板材上。紧接着实施微影制程以露出接触面与金属(铝)焊垫与/或切割道，接着施行电浆清洁制程，以清洁接触面与金属(铝)焊垫。下一步骤为以溅镀钛/铜作为金属层种子，并接着涂布光阻于介电层与金属层种子上，以形成重布层(RDL)图案。接着施行电镀制程以形成铜/金或铜/镍/金作为重布层金属，接着移去光阻并干蚀刻金属层以及露出接触金属垫，以形成RDL金属走线。紧接着，其下一步为披覆或涂布上介电层以及露出焊料图块之金属垫与/或切割道，此即完成其第一层板材制程。
后续程序可重复上述之步骤，以形成多层金属与介电层，以完成第二层晶粒。溅镀钛/铜步骤以形成金属种子层，且涂布PR以形成RDL图案，接着电镀步骤以形成铜/金于RDL图案，接着剥除PR且以湿蚀刻种子金属，以形成第二重布重布金属走线，一上介电层型成以保护其第二RDL走线。
越薄之晶粒(约50-127微米)，可得较佳制程特性与可靠性，其制程进一步包含藉由覆晶黏晶机黏着上层芯片(CSP)。之后其上层芯片(CSP)被黏着，以热回焊制程作焊接，接着导电(焊接)凸块(球)连结于第一RDL与第二RDL。
接着执行测试，以垂直测试卡作板材晶圆级最后测试。经测试后，其基板被切割为单一封装，成为具有多晶粒之单独SIP单元，此封装为分开地包装，经取放封装(组件)至托盘、胶带或卷带。
本发明所述具有之优点：
其前制备基板具有预先成型之凹槽；其凹槽大约等于晶粒大小加上两侧边各50至100微米裕度，此可以填充弹性介电材料，以吸收硅晶粒与基板间(FR5/BT)CTE差异所产生之热机械应力，作为应力缓冲释放区域。肇因于于晶粒与基板上表面简单增层，此SIP封装之产能将被增加(生产时间减少)。其导线电路与终端接点于晶粒之主动面之另一侧，其晶粒放置程序与现今同。本发明之制程无须填入砂心黏糊(树脂、环氧化合物、[聚]硅氧橡胶等)，亦无焊料与母板PCB造成CTE差异。其晶粒与基板FR4深度差异约为20微米至30微米(作为晶粒黏着材料裕度)，晶粒黏着于基板之凹槽后，其晶粒与基板表面基准相同，以利增层程序。只有当硅基介电材料(SINR较佳)涂布于主动面与基板(FR45或BT较佳)表面，其接触面结构以光罩制程露出，只有当介电材料(SINR)为光敏材料作为接触面露出。真空制程用于SINR涂布时减少气泡因素。于晶粒连结于基板前，其晶粒黏着材料先涂布于晶粒背面。本发明于封装级与基板级之可靠度皆优于往昔，尤其于板级之温度循环测试，其归因于基板与PCB母板之CTE相同，因此无热机械应力产生至焊料凸块/球极。其成本低且制程简单，亦于制作结封装(多晶粒封装)。
虽然已详述本发明之较佳实施例，在不背离本发明之精神与范畴的前提下，关于本发明多种的改变与取代是可施行的。本发明只受下述之申请专利范围与其等效范畴所限制。

Claims (9)

1.一多晶粒封装结构，其特征在于：所述多晶粒封装结构，其包含：
一基板其具有一晶粒容纳凹槽形成于此基板之上表面且一通孔结构贯通形成，其中具一导线电路具终端接点形成于此通孔结构之下；
一第一晶粒放置于此晶粒容纳凹槽内；
一第一介电层形成于此第一晶粒与此基板之上；
一第一重布传导层(RDL)形成于此第一介电层之上，其中第一RDL藉由此通孔结构接合此第一晶粒与此终端接点；
一第二介电层形成于此第一RDL之上；
一第二晶粒；
一第三介电层形成于此第二晶粒之下；
一第二重布传导层(RDL)形成于此第三介电层之下，于此第二重布传导层RDL接合此第二晶粒；
一第四介电层形成于此第二重布传导层RDL之下；
导电凸块形成于第一晶粒与第二晶粒间，以接合此第一重布传导层RDL与此第二重布传导层RDL。
2.根据权利要求1所述的多晶粒封装结构，其特征在于：其中此第一介电层包含一弹性介电层。
3.根据权利要求1所述的多晶粒封装结构，其特征在于：进一步包含一围阻材料形成于此第二晶粒之周围。
4.一多晶粒封装，其特征在于：所述多晶粒封装，其包含：
一基板其至少具有两晶粒容纳凹槽形成于此基板上表面以容纳至少两晶粒且通孔结构形成于其间贯通，其中导线电路具有终端接点形成于此通孔结构之下；
一第一晶粒与第二晶粒放置于此分开之至少两晶粒容纳凹槽；
一第一介电层形成于此第一晶粒，第二晶粒与此基板之上，一第一重布导电层RDL形成于此第一介电层之上，其中此第一RDL藉由此通孔结构为接合此第一晶粒、第二晶粒与终端接点；
一第二介电层形成于此第一RDL之上；
一第三晶粒；
一第三介电层形成于此第三晶粒之下；
一第二重布导电层(RDL)形成于此第三介电层之下，其中此第二RDL接合此第三晶粒；
一第四介电层形成于此第二RDL之下；
导电凸块形成于此第一晶粒与此第三晶粒以接合此第一RDL与第二RDL。
5.根据权利要求4所述的多晶粒封装，其特征在于：进一步包含至少一被动组件黏着并连接于此第一RDL之接点。
6.根据权利要求4所述的多晶粒封装，其特征在于：进一步包含一围阻材料形成于此第三晶粒之周围。
7.一形成半导体元间封装之方法，其特征在于：所述形成半导体元间封装之方法，其包含：
提供一基板其具有晶粒容纳凹槽形成于此基板之上表面，且一通孔结构形成贯通其中，于此通孔之下，其中具有终端接点之导线电路；
于工具上至少重布一第一晶粒，藉由精密取放对位系统使具有所欲之线宽；
涂布黏着材料至少于此第一晶粒之背面；
黏着此基板至此晶粒背面，且此晶粒放置于此基板之此凹槽上，且藉由此工具分开形成板材晶圆；
涂布一第一介电层至少于此第一晶粒与此基板，并且将之填充入此凹槽中晶粒边缘与侧壁间隙；
形成一第一RDL于此第一介电层之上；
形成一第二介电层于此第一RDL之上，以作为露出接触点；
施行一第二晶粒；
形成一第三介电层于此第二晶粒之下；
形成一第二RDL于此第三介电层之下；
形成一第四介电层于此第二RDL之下，以作为保护此第二RDL并露出第二第二接点；且
形成一导电凸块于此第一晶粒与此第二晶粒之间，以连接此第一RDL之此第一接点与此第二RDL之第二接点。
8.根据权利要求7所述的形成半导体元间封装之方法，其特征在于：进一步包含一围阻材料形成于此第二晶粒之周围。
9.根据权利要求7所述的形成半导体元间封装之方法，其特征在于：其中此第二晶粒由晶圆尺寸级封装制成(WLP)并具有增层(RDL)，且焊料凸块/球极于晶粒之上方表面，接着利用覆晶黏着方式黏着此第二晶粒(WLP-CSP)于基材晶圆制程上，以回焊焊料凸块/球极以接合此第一RDL之第一接点以及此第二RDL之第二接点。
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