TWI474444B - 超薄多層基板之封裝方法 - Google Patents

超薄多層基板之封裝方法 Download PDF

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Publication number
TWI474444B
TWI474444B TW100149376A TW100149376A TWI474444B TW I474444 B TWI474444 B TW I474444B TW 100149376 A TW100149376 A TW 100149376A TW 100149376 A TW100149376 A TW 100149376A TW I474444 B TWI474444 B TW I474444B
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Taiwan
Prior art keywords
ultra
multilayer substrate
package
bonding
thin
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TW100149376A
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English (en)
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TW201327737A (zh
Inventor
Yeong Yan Guu
Ying Jer Shih
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Princo Corp
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Application filed by Princo Corp filed Critical Princo Corp
Priority to TW100149376A priority Critical patent/TWI474444B/zh
Priority to CN201210087730.0A priority patent/CN103187318B/zh
Priority to US13/665,950 priority patent/US8501502B2/en
Priority to EP12195729.4A priority patent/EP2610905B1/en
Priority to KR1020120147840A priority patent/KR101418282B1/ko
Priority to JP2012283118A priority patent/JP5489133B2/ja
Publication of TW201327737A publication Critical patent/TW201327737A/zh
Application granted granted Critical
Publication of TWI474444B publication Critical patent/TWI474444B/zh

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Description

超薄多層基板之封裝方法
本發明係與多層基板之封裝方法有關，特別是與一種適用於採用超薄、高密度之封裝多層基板，用於多元件整合複雜封裝的晶圓級封裝方法有關。
隨著IC晶片的積集度追趕著摩爾定律的飛快發展，相應的封裝技術亦不斷地達到前所未有、創新的技術水準。而在眾多創新出來的封裝技術當中，晶圓級封裝(WLP,Wafer Level Packaging or CSP,Chip Scale Package)是IC晶片封裝的其中一種方式，也亦為具有指標性視為革命性技術突破的一環。與先前之技術最大之不同點在於：晶圓級封裝的概念係直接在晶圓上進行且完成積體電路封裝技術之製造，而非切割晶圓後再個別對IC晶片組裝的傳統封裝製程。晶圓級封裝後，IC晶片的尺寸與晶粒原有尺寸相同，因此業界亦稱謂晶圓級晶片尺寸封裝(WLCSP,Wafer Level Chip Scale Package)。
但由於前述現有WLP尺寸限制了布局(layout)扇出(Fan-out)的範圍，因此現今業界亦發展出Fan-out WLP，如：infinion的eWLB(Embedded wafer level ball grid array)的技術，或是Renasas的SiWLP(System in Wafer-Level Package)與SMARFTI(SMArt chip connection with Feed-Through Interposer)的技術。
請參考第1A圖~第1F圖，係用以說明扇出晶圓級封裝(FO-WLP)的簡單示意圖。然即如前所述，目前業界所謂扇出晶圓級封裝並未有標準製程，各種相關技術間會略有所差異，但其技術概念大體上相同。
如第1A圖，提供一暫時性載具100，以晶圓級封裝而言，此暫時性載具即可為一晶圓。
如第1B圖，於該暫時性載具上製作多層線路，包括製作金屬層102、106之線路以及製作介電層104，於交替製作金屬層102、106與介電層104，以形成多層線路(即封裝IC晶片的多層基板)。於第1B圖僅顯示部分以簡化說明。實際上可能形成3~5層。
如第1C圖，於該多層線路上表面形成多個焊墊層108(Ball Pad Layer)，如第1C圖中所示，焊墊層108係透過導孔金屬110與下方多層線路的金屬層106連接。
如第1D圖，透過該些焊墊層108，對晶片150(裸晶,Die)進行封裝112，封裝112的方式例如為眾所週知之覆晶凸塊封裝(Flip chip bump bonding)或者是微凸塊銲接(MBB,micro bump bonding)或表面黏著球閘陣列(SMT BGA,Surface Mount Ball Grid Array)封裝。
如第1E圖，接著，對已封裝完成的晶片進行模封152(Molding)。
如第1F圖，使完成模封之晶片150及多層線路與該暫時性載具100分離後，對多層線路下表面進行植球114(BGA Ball mounting)。
前述關於扇出晶圓級封裝之說明係為簡化之描述，然基本概念皆係在晶圓100上製作多層線路，封裝晶片150後，自暫時性載具100(晶圓)分離，再進行切割製程(Dice or Sigulation)，始完成個別IC晶片150的封裝。然，而前述封裝製程良率主要取決於其個別封裝構成部分之良率之總和而決定。前述晶圓級封裝而言，必須先對整個晶圓100實施封裝(wafer molding)後，方能進行切割製程(Dice or Sigulation)。而無法避免當中的多層線路(即封裝IC晶片的多層基板)造成個別IC晶片封裝的失敗，仍需在切割製程(Dice or Sigulation)後才挑選出封裝合格的IC晶片。
再者，以Renasas所提出之SMAFTI封裝方法，用於封裝記憶體晶片(Memory Chip)及系統單晶片(SoC,System-On-a-Chip)或邏輯晶片(Logic Chip)為例；首先，在晶圓表面製作多層線路(FTI,Feed-Through Interposer)，即所謂中介層。
對記憶體晶片(Memory Chip)進行封裝(bonding)。
對整個晶圓實施封裝(wafer molding)。
移除晶圓(Silicon Wafer)。
透過中介層(FTI,Feed-Through Interposer)，對系統單晶片(SoC,System-On-a-Chip)或邏輯晶片(Logic Chip)進行封裝(bonding)。整個完成封裝的產品(封裝記憶體晶片及系統單晶片或邏輯晶片)則採用球閘陣列(BGA)以連接至外部之系統電路板(PCB)。
封裝製程之整體良率主要取決於其各別構成部分之良率之總和而決定。以前述為例即為1.製作多層線路(FTI,Feed-Through Interposer)；2.封裝記憶體晶片；3.封裝系統單晶片或邏輯晶片三個部分之良率。
而以前述SMAFTI製程而言，多層線路(FTI,Feed-Through Interposer)的良率必然為封裝製程整體良率之其中一個主要因素並且無法避免。即便對多層線路(FTI,Feed-Through Interposer)先行測試，由於其係採用晶圓模封(wafer molding)。而無法選擇性地對個別IC晶片決定封裝(bonding)或者是模封(molding)。不僅對封裝製程整體良率的提升有所阻礙，更是導致成本無謂增加的主要因素。
並且，前述晶圓級封裝之技術亦多僅限用於先對單一種裸晶進行封裝(Flip Chip)，目前封裝技術業界並未就超薄的軟性多層基板的封裝進行多種元件整合封裝的應用有具體的解決方案。並且，如前述晶圓級封裝中的多層基板先用以對系統單晶片(SoC,System-On-a-Chip)或邏輯晶片(Logic Chip)進行封裝(bonding)後，再利用多層基板的另外一側球閘陣列(BGA)以連接至外部之系統電路板(PCB)，方完成整個封裝的產品。當封裝製程的複雜度、整合密度不斷提高時，採用軟性多層基板的封裝製程也逐漸不斷地開發出更多封裝技術的可能性，已被視為未來次世代的封裝技術。若仍採用前述相同習知晶圓級封裝的製程概念，即存在無法對多層線路(FTI,Feed-Through Interposer)先行測試的缺點，同樣地無法實現先行完整測試。而因採用軟性多層基板的封裝製程能應用於多元件整合複雜封裝的晶圓級封裝的優點亦無從發揮起，也仍存在良率亟待提升的問題。
是以，勢必需發展一軟性超薄多層基板封裝製程的全方位解決方案，針對測試、封裝、模封而完成成品的各製程步驟，提出一超薄多層基板之封裝及測試方法。
本發明之主要目的在於提供一種超薄多層基板之封裝及測試方法，可先行測試多層基板，適用於複雜度高、整合密度高之封裝製程，不僅能提升晶圓級封裝製程的整體良率，更能有效低進一步減少無謂的製作材料成本。
本發明之超薄多層基板之封裝方法的第一實施例包括：提供一暫時性載板；交替形成複數個金屬層及複數個介電層，用以製作該超薄多層基板，該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片；於該超薄多層基板表面形成複數個焊墊層；將該超薄多層基板與該暫時性載板分離；對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；以不具有缺陷的該些封裝單元，各別以覆晶接合方式與該些晶片接合；以及對該超薄多層基板上已覆晶接合之該些晶片進行全體模封。
本發明之超薄多層基板之封裝方法的第二實施例包括：提供一暫時性載板；交替形成複數個金屬層及複數個介電層，用以製作該超薄多層基板，該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片；於該超薄多層基板表面形成複數個焊墊層；將該超薄多層基板與該暫時性載板分離；對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；以不具有缺陷的該些封裝單元以覆晶接合方式與該些晶片接合；以模封板之尺寸為單位，切割該超薄多層基板；以及對該模封板上已覆晶接合之該些晶片進行模封。
本發明之超薄多層基板之封裝方法的第三實施例包括：提供一暫時性載板；交替形成複數個金屬層及複數個介電層，用以製作該超薄多層基板，該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片；於該超薄多層基板表面形成複數個焊墊層；將該超薄多層基板與該暫時性載板分離；對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；以模封板之尺寸為單位，切割該超薄多層基板，用以篩選出不具有缺陷的該些封裝單元；以不具有缺陷的該些封裝單元各別以覆晶接合方式與該些晶片接合；以及對該模封板上已覆晶接合之該些晶片進行模封。
本發明之超薄多層基板之封裝方法的第四實施例包括：提供一暫時性載板；交替形成複數個金屬層及複數個介電層，用以製作該超薄多層基板，該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片；於該超薄多層基板表面形成複數個焊墊層；將該超薄多層基板與該暫時性載板分離；對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；以不具有缺陷的該些封裝單元各別以覆晶接合方式與該些晶片接合；以及對該些封裝單元各別與複數個錫球接合形成一球閘陣列。
本發明之超薄多層基板之封裝方法的第五實施例包括：提供一暫時性載板；交替形成複數個金屬層及複數個介電層，用以製作該超薄多層基板，該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片；於該超薄多層基板表面形成複數個焊墊層；將該超薄多層基板與該暫時性載板分離；對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；以該些封裝單元為單位，切割該超薄多層基板，用以篩選出不具有缺陷的該些封裝單元；以模封板之尺寸為單位，重組不具有缺陷的該些封裝單元後，各別以覆晶接合方式與該些晶片接合；以及對該模封板上已覆晶接合之該些晶片進行模封。
本發明超薄多層基板之封裝方法可先行測試多層基板，適用於複雜度高、整合密度高之封裝製程之特點，並且多採用移轉模封(Transfer Molding)，相較於不僅能提升晶圓級封裝製程的整體良率，更能有效低進一步減少無謂的製作成本之優點。
請參考本發明第2A圖至第2D圖，係表示本發明超薄多層基板之封裝方法前四個步驟之簡單示意圖。
如第2A圖所示，提供一暫時性載板200，以晶圓級封裝而言，此暫時性載板可為一晶圓。
如第2B圖所示，於該暫時性載具上交替形成複數個金屬層202、206及複數個介電層204，用以製作本發明之超薄多層基板，超薄多層基板具有複數個封裝單元，如圖中所顯示為超薄多層基板中之單一個封裝單元，用以封裝單一個IC晶片。例如：以金屬剝離製程製作金屬層202、206之線路，以聚醯亞胺(polyimide)製作介電層204。交替製作金屬層202、206與介電層204，以形成多層線路(即用以封裝IC晶片的超薄多層基板)。並且利用形成之導孔金屬208連接金屬層202、206等之金屬線路。
如第2C圖所示，於超薄多層基板表面形成複數個焊墊層210(Ball Pad)。
如第2D圖所示，將製作完成之超薄多層基板與暫時性載板100分離後，使焊墊層210(Ball Pad)朝下，即能以覆晶接合方式與IC晶片接合。值得注意的是，本發明中所製作金屬層202，亦能作為焊墊層，因此利用本發明，可視電路設計所需亦能採用金屬層202以覆晶接合方式與IC晶片、其他封裝完成電子元件、被動元件或外部電路等接合。相較於習知技術，本發明之製程彈性大，藉由本發明，封裝電路設計亦能更為靈活。
接著，由於超薄多層基板已經與暫時性載板100分離，因此能對超薄多層基板進行完整之良率測試，即能汰選具有缺陷的封裝單元，予以標記。以篩選出不具有缺陷的封裝單元，進而提高整體封裝良率。
如前述本發明在超薄多層基板製作完成後將從暫時性載板100上取下進行測試，本發明多層基板厚度僅30~200um，一般常見厚度在50~100um之間，質地非常的柔軟。因此測試方式也與前述習知晶圓級封裝迥異。前述習知晶圓級封裝由於具有穩定的形體，因此僅需簡單固定後即能採用一般飛針測試機(flying probe)或是板卡測試機(探針卡,probe card)進行測試。
然而，針對多層基板進行測試的主要客體，即要找出的多層基板的主要電性缺陷為兩組線路網(net)短路、線路網斷路、線路電阻偏移以及線路結構缺陷導致的潛在缺陷(latent fault)。本發明針對多層基板進行的電性測試有電容法測試或是電阻法測試。
電容法測試係僅需一個測試接點。電容法測試係比對待測線路網的電容值與正確線路網的電容值，若兩組線路網(net)短路，則待測線路網的電容值較高；若線路網斷路，則待測線路網的電容值將較低。但電容法測試的缺點在於無法量測線路電阻偏移，線路結構缺陷導致的潛在缺陷(latent fault)。
電阻法測試則必須有兩個接點。電阻法測試係比對待測的線路網電阻值與正確線路網的電阻值，若兩組線路網(net)短路，將發現正常兩組線路網斷路變為有電阻數值；若線路網斷路，則將發現正常線路網的電阻數值變為斷路；若線路電阻偏移，則能比對出與正常電阻值的偏移量；若有潛在缺陷(latent fault)，則能輸入高頻訊號偵測出高頻數值的變化。即能進行所謂完整測試，提高多層基板的良率。而前述習知晶圓級封裝製程在以多層基板對裸晶封裝後，多層基板僅有單一面未覆蓋，若欲對多層基板單獨進行測試，則僅電容法測試能採用，因為電容法測試僅需單一測試接點，此亦實務上前述習知晶圓級封裝製程不會也無法先行對多層基板單獨進行完整測試的原因，因為若要先行對多層基板單獨進行完整的測試，必需多層基板獨立存在、未與其他元件接合的狀態下，方能具備兩個接點進行測試，且唯有電阻法測試方能實現完整的測試。是以本發明於此同時亦提出本發明超薄多層基板之測試方法。
請參考本發明第3A圖至第3D圖係本發明超薄多層基板在進行封裝前以測探針卡對超薄多層基板進行完整之良率測試之簡單示意圖。如第3A圖的俯視圖、第3B圖的側視圖所示，本發明對第2D圖中的超薄多層基板20進行測試前，由於如前述本發明超薄多層基板厚度僅30~200um，一般常見厚度在50~100um之間，質地非常的柔軟，因此係需利用夾持系統300。夾持系統300包括外周部310、挾持部320、調整彈簧330以及緊固螺絲340。外周部310係配合超薄多層基板的形狀製作而成之治具。挾持部320係用以挾持超薄多層基板的邊緣。調整彈簧330可進一步精確地調整超薄多層基板固定在外周部310內的位置，並且配合緊固螺絲340，使夾持系統300給予超薄多層基板20適當的張力，使超薄多層基板20受適當張力，以利進行測試。
並且，前述張力必需控制得宜，為能使測試時，對超薄多層基板的接觸電阻在5ohm以下，較佳為1ohm以下，夾持系統300必需使超薄多層基板20受一定張力。然而，超薄多層基板20所受的張力應在0~40,000 N/m之間，較佳為0.1~1000 N/m。超薄多層基板所受張力的限制隨基板厚度與彈性係數(Young’s modules)而改變。變形量應小於1000ppm(每公分距離變形<10μm)，以使探針卡400的測試針401能確實接觸超薄多層基板20的焊墊202等。目的不僅為能使測試時，對超薄多層基板的接觸電阻在5ohm以下，較佳為1ohm以下，更由於若超薄多層基板所受張力超過前述限度，既可能造成其不可逆的形變，進而導致內部線路的損毀，超薄多層基板必需報廢。再者，軟性超薄多層基板經過測試後，會於焊墊表面形成測試扎痕(probe mark)，依照不同測試方法與下壓力量，測試扎痕的大小在5~50um，深度在100nm~3000nm之間，而如前述為能使探針卡400的測試針401能確實接觸超薄多層基板20的焊墊202等，此種測試扎痕於測試中係必然之現象。且由測試扎痕可觀察得之，測試扎痕過小，將造成接觸不良使測試失敗，測試扎痕過大，將會使焊墊表面損傷使接合面產生孔隙，使後續接合製程接合不良，甚至焊墊表面損傷後產生氧化物，導致接合面氧化降低接合強度。是以，依據本發明即能實現前述張力控制得宜，滿足軟性超薄多層基板之測試需前述電性、基板所受張力、避免焊墊表面損傷等諸多方技術層面之考量。
再者，如第3C圖的側視圖所示，係本發明可採用另外一種夾持超薄多層基板的夾持系統301之示意圖。夾持系統301包括下挾持板311、上挾持板312以及緊固螺絲341。下挾持板311具有吸附孔313，可利用真空吸附(suction)的方式更進一步固定挾持在下挾持板311與上挾持板312之間的超薄多層基板20。
再者，如第3D圖的側視圖所示，係本發明可採用另外一種夾持超薄多層基板的夾持系統302之示意圖。夾持系統302包括下挾持板314、上挾持板315以及緊固螺絲341。與第3C圖所示的夾持系統301不同的是，夾持系統302的下挾持板314與上挾持板315並非如下挾持板311與上挾持板312係完全中空露出超薄多層基板的一套挾持板。而是在超薄多層基板的切割道或防焊層覆蓋區域等無效區域同樣有挾持板，僅露出超薄多層基板所需測試區域的一套挾持板。下挾持板314亦可具有吸附孔313，可利用真空吸附(suction)的方式更進一步固定挾持在下挾持板314與上挾持板315之間的超薄多層基板20。
本發明第3A圖至第3D圖雖以圓形為例，但本發明並未以此形狀為限定，本發明的夾持系統300能依照超薄多層基板的形狀所需，製作成長方形或矩形皆可，本發明並未有特別的限定。
請參考本發明第2A圖至第2D圖、第3A圖至第3D圖及第4圖。第4圖係表示本發明超薄多層基板之封裝方法第一實施例之流程圖。封裝方法主要分位兩個部份，裸晶接合與元件接合。裸晶接合(bare die bonding)例如可以採用覆晶封裝(Flip chip)或打線封裝(wire bonding)。元件接合則例如可以採用表面黏著封裝(Surface Mounting Tech.,Thin Small Outline Package,Quad Flat No leads,Ball Grid Array)。
以下詳細說明本發明超薄多層基板之封裝方法的各步驟：步驟S101，如第2A圖所示，提供一暫時性載板200；步驟S102，如第2B圖所示，交替形成複數個金屬層202、206及複數個介電層204，用以製作超薄多層基板，介電層204例如：能以聚醯亞胺(Polyimide)為材料，以旋轉塗佈法(Spin Coating)而形成；金屬層202、206則以金屬剝離製程(Metal Lift Off)形成。該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片。於單一超薄多層基板封裝的晶片數目可以為單個或多個，多晶封裝例如可以為2維平面多顆封裝(Multi Chip Module)或3維堆疊多顆封裝(Stacking Packaging)，於此實施例中係以單晶封裝作說明；步驟S103，如第2C圖所示，於超薄多層基板表面形成複數個焊墊層210，第2A~2D圖中所示係以一個封裝單元能藉由焊墊層210，如同第1D圖中透過微凸塊銲接(MBB,micro bump bonding)對一個晶片150(裸晶,Die)進行封裝；步驟S104，如第2D圖所示，將超薄多層基板與暫時性載板100分離；步驟S105，如第3A圖至第3D圖所示，對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；步驟S106，接著於進行晶片之覆晶接合(Flip Chip bonding)時，即以不具有缺陷的該些封裝單元透過該些焊墊層(Ball Pad)，各別以覆晶接合(Flip Chip Bonding)方式與該些晶片接合，避免將良好的IC晶片接合封裝於測試結果具有缺陷的封裝單元上。前述覆晶接合封裝技術之封裝密度高，可以選擇金凸塊(Gold bump)覆晶接合，或是銅柱凸塊(copper pillar)覆晶接合，其中金凸塊(Gold bump)或金打線凸塊(Gold stud bump)覆晶接合不需要助焊劑且接合溫度低(130℃~200℃)，不易造成軟性的超薄多層基板變形。銅柱凸塊(copper pillar)覆晶接合則需要印刷助焊劑，亦適用於本發明；步驟S107，對該超薄多層基板上已覆晶接合之該些晶片進行全體熱壓模封(Wafer Level Compression Molding)，於本發明此實施例中，此步驟所進行之模封即為使該些IC晶片為成品之模封(Package Molding)；步驟S108，對該超薄多層基板具有該些焊墊層(Ball Pad)的另一表面，例如第2D圖所示之金屬層202進行植球(BGA Ball mounting)，進行植球即為各別對該些封裝單元與複數個錫球進行之接合，形成球閘陣列，即所謂的球閘陣列封裝(BGA Package)，或與外界的一球閘陣列封裝元件進行接合。此步驟中前述與錫球或元件接合的封裝技術之封裝密度較低，且在封裝接合前需錫膏(solder paste)或助焊劑(flux)的印刷。於此實施例中錫球的球閘陣列係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合的另一表面進行接合，但並非以此為限。本發明亦能在同一表面進行裸晶接合後再實施與錫球的球閘陣列之接合。並且，亦可先進行錫球的球閘陣列接合後，再進行裸晶接合，或者同時進行裸晶接合及錫球的球閘陣列接合。
前述與外界的一球閘陣列封裝元件進行之接合，亦能有以下之結構變化，球閘陣列封裝元件係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合之同一表面進行接合，或者，本發明亦能在不同表面進行裸晶接合後再實施球閘陣列封裝元件接合。並且，亦可先進行球閘陣列封裝元件接合後，再進行裸晶接合，或者同時進行裸晶接合及球閘陣列元件接合；步驟S109，以該些封裝單元為單位，依照該些晶片的該些封裝單元(即模封；Package Molding)之尺寸，切割(Dicing)該超薄多層基板，使該些IC晶片即為封裝完成之成品；步驟S110，各別對該些已模封(Package Molding)之晶片進行測試(PKG Test)。
請參考本發明第2A圖至第2D圖、第3A圖至第3D圖及第5圖。第5圖係表示本發明超薄多層基板之封裝方法第二實施例之流程圖。下述裸晶接合(bare die bonding)例如可以採用覆晶封裝(Flip chip)或打線封裝(wire bonding)。元件接合則例如可以採用表面黏著封裝(Surface Mounting Tech.,Thin Small Outline Package,Quad Flat No leads,Ball Grid Array)。
以下詳細說明本發明超薄多層基板之封裝方法的各步驟：步驟S201，如第2A圖所示，提供一暫時性載板200；步驟S202，如第2B圖所示，交替形成複數個金屬層202、206及複數個介電層204，用以製作超薄多層基板，介電層204例如：能以聚醯亞胺(Polyimide)為材料，以旋轉塗佈法(Spin Coating)而形成；金屬層202、206則能以銅為材料，以金屬剝離製程(Metal Lift Off)形成。該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片。於單一超薄多層基板封裝的晶片數目可以為單個或多個，多晶封裝例如可以為2維平面多顆封裝(Multi Chip Module)或3維堆疊多顆封裝(Stacking Packaging)，於此實施例中係以單晶封裝作說明；步驟S203，如第2C圖所示，於超薄多層基板表面形成複數個焊墊層210，第2A~2D圖中所示係以一個封裝單元能藉由焊墊層210，如同第1D圖中透過微凸塊銲接(MBB,micro bump bonding)對一個晶片150(裸晶，Die)進行封裝；步驟S204，如第2D圖所示，將超薄多層基板與暫時性載板100分離。本發明製作之超薄多層基板單一層之厚度可小於20μm甚至10μm，且由於介電層採用單一材質，多層基板之各層間之應力一致性高，較能避免超薄多層基板自暫時性載板100分離後發生翹曲的問題；步驟S205，如第3A圖至第3D圖所示，對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；步驟S206，於此步驟進行晶片之覆晶接合(Flip Chip bonding)時，即以不具有缺陷的該些封裝單元以覆晶接合(Flip Chip Bonding)方式與該些晶片接合。前述覆晶接合封裝技術之封裝密度高，可以選擇金凸塊(Gold bump)覆晶接合，或是銅柱凸塊(copper pillar)覆晶接合，其中金凸塊(Gold bump)或金打線凸塊(Gold stud bump)覆晶接合不需要助焊劑且接合溫度低(130℃~200℃)，不易造成軟性的超薄多層基板變形。銅柱凸塊(copper pillar)覆晶接合則需要印刷助焊劑，亦適用於本發明；步驟S207，以模封板之尺寸(Molding Panel Size)為單位，切割(Dicing)該超薄多層基板，請參見圖1E的模封152(Molding)，所謂的模封板係指用樹酯材料將晶片元件以模封方式包覆住時，受限於單次模封可包覆之面積範圍不同，本發明將會切割超薄多層基板並固定於特定大小的金屬框架上，此金屬框架即為模封板，此面積大小即為模封板之尺寸，由於不同模封的製程方法對於模封模具大小限制有所不同，模封板之尺寸也有所不同；步驟S208，對該模封板(Molding Panel)上已覆晶接合之該些晶片進行模封。於此步驟，本發明係採用移轉模封(Transfer Molding)，且即為使該些IC晶片為成品之保護模封(Package Molding)，相較晶圓級封裝之現有技術中，因採用晶圓大小的全體模封(Wafer Level Compression Molding)，軟性多層基板特別是超薄多層基板非常容易發生翹曲的問題，並且大面積之模封樹酯也非常容易發生翹曲的問題，導致封裝體扭曲而報廢，由於本發明具有模封板之設計能採用精確度高之移轉模封(Transfer Molding)，因此能控制翹曲在很小的範圍內，一般控制翹曲於60~500um範圍，較佳條件為10~300um；步驟S209，對該超薄多層基板具有該些焊墊層(Ball Pad)的另一表面，例如第2D圖所示之金屬層202進行植球(BGA Ball mounting)，進行植球即為各別對該些封裝單元與複數個錫球進行之接合，形成錫球的球閘陣列，即所謂的球閘陣列封裝(BGA Package)，或與外界的一球閘陣列封裝元件進行接合。此步驟中前述與錫球或元件接合的封裝技術之封裝密度較低，且在封裝接合前需錫膏(solder paste)或助焊劑(flux)的印刷。於此實施例中錫球的球閘陣列係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合的另一表面進行錫球之接合，但並非以此為限，本發明亦能在同一表面進行裸晶接合後再實施與錫球的球閘陣列之接合。並且，亦可先進行錫球的球閘陣列接合後，再進行裸晶接合，或者同時進行裸晶接合及錫球的球閘陣列接合。
前述與外界的一球閘陣列封裝元件進行之接合，亦之有以下之結構變化，球閘陣列封裝元件係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合之同一表面進行接合，或者，本發明亦能在不同表面進行裸晶接合後再實施球閘陣列封裝元件接合。並且，亦可先進行球閘陣列封裝元件接合後，再進行裸晶接合，或者同時進行裸晶接合及球閘陣列元件接合；步驟S210，以該些封裝單元為單位，依照該些晶片的各別封裝單元之尺寸，切割該模封板(Molding Panel)；步驟S211，各別對該些已模封(Package Molding)之晶片進行測試(PKG Test)。
請參考本發明第2A圖至第2D圖、第3A圖至第3D圖及第6圖。第6圖係表示本發明超薄多層基板之封裝方法第三實施例之流程圖。裸晶接合(bare die bonding)例如可以採用覆晶封裝(Flip chip)或打線封裝(wire bonding)。元件接合則例如可以採用表面黏著封裝(Surface Mounting Tech.,Thin Small Outline Package,Quad Flat No leads,Ball Grid Array)。
以下詳細說明本發明超薄多層基板之封裝方法的各步驟：步驟S301，如第2A圖所示，提供一暫時性載板200；步驟S302，如第2B圖所示，交替形成複數個金屬層202、206及複數個介電層204，用以製作超薄多層基板，介電層204例如：能以旋轉塗佈法(Spin Coating)製作；金屬層202、206則以金屬剝離製程(Metal Lift Off)製作。該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片。於單一超薄多層基板封裝的晶片數目可以為單個或多個，多晶封裝例如可以為2維平面多顆封裝(Multi Chip Module)或3維堆疊多顆封裝(Stacking Packaging)，於此實施例中係以單晶封裝作說明；步驟S303，如第2C圖所示，於超薄多層基板表面形成複數個焊墊層210，第2A~2D圖中所示係以一個封裝單元能藉由焊墊層210，如同第1D圖中透過微凸塊銲接(MBB,micro bump bonding)對一個晶片150(裸晶,Die)進行封裝；步驟S304，如第2D圖所示，將超薄多層基板與暫時性載板100分離。本發明製作之超薄多層基板單一層之厚度可小於20μm甚至10μm，且由於介電層採用單一材質，多層基板之各層間之應力一致性高，較能避超薄多層基板自暫時性載板100分離後發生翹曲的問題；步驟S305，如第3A圖至第3D圖所示，對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；步驟S306，於本發明此實施例之此步驟中，以模封板之尺寸(Molding Panel Size)為單位，切割該超薄多層基板，即先以篩選出不具有缺陷的該些封裝單元；步驟S307，於此步驟進行晶片之覆晶接合(Flip Chip bonding)時，即以不具有缺陷的該些封裝單元各別以覆晶接合(Flip Chip Bonding)方式與該些晶片接合。前述覆晶接合封裝技術之封裝密度高，可以選擇金凸塊(Gold bump)覆晶接合，或是銅柱凸塊(copper pillar)覆晶接合，其中金凸塊(Gold bump)或金打線凸塊(Gold stud bump)覆晶接合不需要助焊劑且接合溫度低(130℃~200℃)，不易造成軟性的超薄多層基板變形。銅柱凸塊(copper pillar)覆晶接合則需要印刷助焊劑，亦適用於本發明；步驟S308，對該模封板(Molding Panel)上已覆晶接合之該些晶片進行模封。於此步驟，本發明係採用移轉模封(Transfer Molding)，且此步驟之模封即為使該些IC晶片為成品之保護模封(Package Molding)，相較晶圓級封裝之現有技術中，因採用全體模封(Wafer Level Compression Molding)，軟性多層基板特別是超薄多層基板非常容易發生翹曲的問題，由於本發明能採用精確度高之移轉模封(Transfer Molding)，因此能控制翹曲在很小的範圍內；步驟S309，對該超薄多層基板具有該些焊墊層(Ball Pad)的另一表面，例如第2D圖所示之金屬層202進行植球(BGA Ball mounting)，進行植球即為各別對該些封裝單元與複數個錫球進行之接合，形成球閘陣列，即所謂的球閘陣列封裝(BGA Package)，或與外界的一球閘陣列封裝元件進行接合。此步驟中前述與錫球或元件接合的封裝技術之封裝密度較低，且在封裝接合前需錫膏(solder paste)或助焊劑(flux)的印刷。於此實施例中錫球的球閘陣列係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合的另一表面進行錫球之接合，但並非以此為限，本發明亦能在同一表面進行裸晶接合後再實施與錫球的球閘陣列之接合。並且，亦可先進行錫球的球閘陣列接合後，再進行裸晶接合，或者同時進行裸晶接合及錫球球閘陣列接合；前述與外界的一球閘陣列封裝元件進行之接合，亦能有以下之結構變化，球閘陣列封裝元件係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合之同一表面進行接合，或者，本發明亦能在不同表面進行裸晶接合後再實施球閘陣列封裝元件接合。並且，亦可先進行球閘陣列封裝元件接合後，再進行裸晶接合，或者同時進行裸晶接合及球閘陣列元件接合；步驟S310，以該些封裝單元為單位，依照該些晶片的各別封裝單元之尺寸，切割該模封板(Molding Panel)；步驟S311，各別對該些已模封(Package Molding)之晶片進行測試(PKG Test)。
請參考本發明第2A圖至第2D圖、第3A圖至第3D圖及第7圖。第7圖係表示本發明超薄多層基板之封裝方法第四實施例之流程圖。下述裸晶接合(bare die bonding)例如可以採用覆晶封裝(Flip chip)或打線封裝(wire bonding)。元件接合則例如可以採用表面黏著封裝(Surface Mounting Tech.,Thin Small Outline Package,Quad Flat No leads,Ball Grid Array)。
以下詳細說明本發明超薄多層基板之封裝方法的各步驟：步驟S3011，如第2A圖所示，提供一暫時性載板200；步驟S3021，如第2B圖所示，交替形成複數個金屬層202、206及複數個介電層204，用以製作超薄多層基板，介電層204例如：能以旋轉塗佈法(Spin Coating)製作；金屬層202、206則以金屬剝離製程(Metal Lift Off)製作。該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片。於單一超薄多層基板封裝的晶片數目可以為單個或多個，多晶封裝例如可以為2維平面多顆封裝(Multi Chip Module)或3維堆疊多顆封裝(Stacking Packaging)，於此實施例中係以單晶封裝作說明；步驟S3031，如第2C圖所示，於超薄多層基板表面形成複數個焊墊層210，第2A~2D圖中所示係以一個封裝單元能藉由焊墊層210，如同第1D圖中透過微凸塊銲接(MBB,micro bump bonding)對一個晶片150(裸晶,Die)進行封裝；步驟S3041，如第2D圖所示，將超薄多層基板與暫時性載板100分離。本發明製作之超薄多層基板單一層之厚度可小於20μm甚至10μm，且由於介電層採用單一材質，多層基板之各層間之應力一致性高，較能避超薄多層基板自暫時性載板100分離後發生翹曲的問題；步驟S3051，如第3A圖至第3D圖所示，對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；步驟S3061，於本發明此實施例中，此步驟係具可選擇性，即可以模封板之尺寸(Molding Panel Size)或者封裝單元為單位，切割該超薄多層基板，即先以篩選出不具有缺陷的該些封裝單元，或者，亦可在執行步驟S3051後即進行下述步驟S3071，抑或，亦可在執行步驟S3081後再進行本步驟S3061；步驟S3071，於此步驟進行晶片之覆晶接合(Flip Chip bonding)時，即以不具有缺陷的該些封裝單元各別以覆晶接合(Flip Chip Bonding)方式與該些晶片接合。前述覆晶接合封裝技術之封裝密度高，可以選擇金凸塊(Gold bump)覆晶接合，或是銅柱凸塊(copper pillar)覆晶接合，其中金凸塊(Gold bump)或金打線凸塊(Gold stud bump)覆晶接合不需要助焊劑且接合溫度低(130℃~200℃)，不易造成軟性的超薄多層基板變形。銅柱凸塊(copper pillar)覆晶接合則需要印刷助焊劑，亦適用於本發明；步驟S3081，對該些晶片各別進行植球(BGA Ball mounting)，進行植球即為各別對該些封裝單元與複數個錫球進行之接合，形成球閘陣列，即所謂的球閘陣列封裝(BGA Package)，此步驟中前述元件接合的封裝技術之封裝密度較低，且在封裝接合前需錫膏(solder paste)或助焊劑(flux)的印刷。於此實施例中錫球的球閘陣列封裝係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合的另一表面進行錫球之接合。
請參考本發明第2A圖至第2D圖、第3A圖至第3D圖及第8圖。第8圖係表示本發明超薄多層基板之封裝方法第五實施例之流程圖。下述裸晶接合(bare die bonding)例如可以採用覆晶封裝(Flip chip)或打線封裝(wire bonding)。元件接合則例如可以採用表面黏著封裝(Surface Mounting Tech.,Thin Small Outline Package,Quad Flat No leads,Ball Grid Array)。
以下詳細說明本發明超薄多層基板之封裝方法的各步驟：步驟S401，如第2A圖所示，提供一暫時性載板200；步驟S402，如第2B圖所示，交替形成複數個金屬層202、206及複數個介電層204，用以製作超薄多層基板，該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片。於單一超薄多層基板封裝的晶片數目可以為單個或多個，多晶封裝例如可以為2維平面多顆封裝(Multi Chip Module)或3維堆疊多顆封裝(Stacking Packaging)，於此實施例中係以單晶封裝作說明；步驟S403，如第2C圖所示，於超薄多層基板表面形成複數個焊墊層210，超薄多層基板的一個封裝單元如同第1D圖中透過微凸塊銲接(MBB,micro bump bonding)對一個晶片150(裸晶,Die)進行封裝；步驟S404，如第2D圖所示，將超薄多層基板與暫時性載板100分離。本發明製作之超薄多層基板單一層之厚度可小於20μm甚至10μm，且由於介電層採用單一材質，多層基板之各層間之應力一致性高，較能避超薄多層基板自暫時性載板100分離後發生翹曲的問題；步驟S405，如第3A圖至第3D圖所示，對該超薄多層基板進行測試，用以汰選具有缺陷的該些封裝單元；步驟S406，於本發明此實施例之此步驟中，以封裝單元尺寸為單位，切割該超薄多層基板，即先以篩選出不具有缺陷的該些封裝單元；步驟S407，接著，以模封板尺寸(Molding Panel Size，亦即前述封裝單元尺寸)為單位，重組不具有缺陷的該些封裝單元後，各別以覆晶接合(Flip Chip bonding)方式與該些晶片接合。前述覆晶接合封裝技術之封裝密度高，可以選擇金凸塊(Gold bump)覆晶接合，或是銅柱凸塊(copper pillar)覆晶接合，其中金凸塊(Gold bump)或金打線凸塊(Gold stud bump)覆晶接合不需要助焊劑且接合溫度低(130℃~200℃)，不易造成軟性的超薄多層基板變形。銅柱凸塊(copper pillar)覆晶接合則需要印刷助焊劑，亦適用於本發明；步驟S408，對該模封板上已覆晶接合之該些晶片進行模封(Molding)。於此步驟中，本發明係採用移轉模封(Transfer Molding)，且此步驟之模封即為使該些IC晶片為成品之模封(Package Molding)，由於本發明能採用精確度高之移轉模封(Transfer Molding)，因此能有效控制軟性多層基板特別是超薄多層基板非常容易發生翹曲的問題；步驟S409，對該超薄多層基板具有該些焊墊層(Ball Pad)的另一表面，例如第2D圖所示之金屬層202進行植球(BGA Ball mounting)，進行植球即為各別對該些封裝單元與複數個錫球進行之接合，形成球閘陣列，即所謂的球閘陣列封裝(BGA Package)，或與外界的一球閘陣列封裝元件進行接合。此步驟中前述與錫球或元件接合的封裝技術之封裝密度較低，且在封裝接合前需錫膏(solder paste)或助焊劑(flux)的印刷。於此實施例中錫球的球閘陣列係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合的另一表面進行錫球之接合，但並非以此為限，本發明亦能在同一表面進行裸晶接合後再實施錫球的球閘陣列接合。並且，亦可先進行錫球的球閘陣列接合後，再進行裸晶接合，或者同時進行裸晶接合及錫球的球閘陣列接合；前述與外界的一球閘陣列封裝元件進行之接合，亦能有以下之結構變化，球閘陣列封裝元件係在該超薄多層基板(該些封裝單元)進行裸晶的覆晶接合之同一表面進行接合，或者，本發明亦能在不同表面進行裸晶接合後再實施球閘陣列封裝元件接合。並且，亦可先進行球閘陣列封裝元件接合後，再進行裸晶接合，或者同時進行裸晶接合及球閘陣列元件接合；步驟S410，以該些封裝單元為單位，依照該些晶片的各別封裝單元之尺寸，切割該模封板(Molding Panel Size)；步驟S411，各別對該些已模封(Package Molding)之晶片進行測試(PKG Test)。
如前所述，封裝製程之整體良率主要取決於其各別構成部分之良率之總和而決定。然因超薄多層基板之複雜度高，其整合密度亦漸高之趨勢下，發生缺陷而導致整體封裝後的IC晶片不合格失效的可能性也愈趨增加。而現有晶圓級封裝之技術中，超薄多層基板(例如前述SMAFTI之中介層)係為連接、封裝記憶體晶片與邏輯晶片之重要關鍵元件，但由於晶圓級封裝技術本身的製程限制，無法對多層基板先行測試後即能進行預先篩選，仍需先對整個晶圓實施模封(wafer molding)，進行切割製程(Dice or Sigulation)切割製程(Dice or Sigulation)後，方能挑選出封裝合格的IC晶片。就成本而言，超薄多層基板之製作成本僅為模封(Package Molding)製作成本的1/3，IC晶片的1/10。然若因超薄多層基板的缺陷而導致整體封裝後的IC晶片不合格失效，則所需付出的成本即僅非單單超薄多層基板之製作成本而已。是以，確有提升晶圓級封裝製程的整體良率，更能有效低進一步減少無謂的製作材料成本之必要。
並且，前述提及裸晶接合與元件接合之順序並未有特別的限定。一般而言多係進行裸晶接合在先，後進行元件接合。原因為裸晶接合之技術多為不可逆之封裝製程，亦不會因後續製程所需升溫而脫焊。而如前述後進行的元件接合在封裝接合前需錫膏(solder paste)或助焊劑(flux)的印刷。若裸晶接合與元件接合係在超薄多層基板的同一表面實施，為避開已完成封裝於超薄多層基板上的裸晶，此時即需採用所謂三維錫膏印刷，以具立體性、可覆蓋裸晶的印刷擋板，避免元件接合用的印刷錫膏接觸到已完成封裝之裸晶。若整體封裝密度較低，則可先行元件接合後再實施裸晶接合，即無需採用三維錫膏印刷，可簡化封裝製程。再者，若裸晶接合可使用錫凸塊(solder bump)或頂部沾錫的銅柱凸塊(copper pillar bump)，以裸晶接合(覆晶接合)方式與元件接合(表面黏著接合)能以同時進行的同一回焊製程(refolw)實現。亦即將裸晶與元件在同一步驟中，擺置於超薄多層基板上(尚未接合的狀態)，經由一次回焊製程，能使裸晶與元件同時與超薄多層基板接合，使封裝方法簡化且提昇封裝效率。
並且，在前述所有實施例之各種封裝步驟中，固定超薄多層基板之方法亦可採用前述如第3A圖至第3D圖中進行測試時所採用之夾持系統300-302。於封裝各步驟中，固定超薄多層基板的要求可不若進行測試時有解除電阻及所受張力等諸多嚴格之要求，僅要能固定超薄多層基板，以利進行封裝即可。
總言之，本發明之特色即在於製作超薄多層基板後，將超薄多層基板與暫時性載板(晶圓)分離，即實現先行測試多層基板的可能，再者，藉由本發明，不僅具備完善良率的技術特徵，更由於測試、封裝等步驟的可彈性排程及有別於習知技術晶圓級封裝受限於晶圓上進行封裝製程的各種缺點，因而採用本發明封裝及測試方法的電路設計亦能更為靈活。是以，本發明超薄多層基板之封裝及測試方法更提供了軟性超薄多層基板封裝製程的全方位解決方案，不僅適用於現今複雜度、整合密度要求日趨嚴密之封裝製程，不僅能提升晶圓級封裝製程的整體良率，更能有效低進一步減少無謂的製作材料成本。
雖然本發明已就較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之變更和潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．暫時性載具(晶圓)
102．．．金屬層
104．．．介電層
106．．．金屬層
108．．．焊墊層
110．．．導孔金屬
112．．．凸塊
114．．．植球
150．．．晶片(裸晶)
152．．．模封
20．．．超薄多層基板
200．．．暫時性載板
202．．．金屬層
204．．．介電層
206．．．金屬層
208．．．導孔金屬
210．．．焊墊層
300．．．夾持系統
301．．．夾持系統
302．．．夾持系統
310．．．外周部
311．．．下挾持板
312．．．上挾持板
313．．．吸附孔
314．．．下挾持板
315．．．上挾持板
320．．．挾持部
330．．．調整彈簧
340．．．緊固螺絲
341．．．緊固螺絲
400．．．探針卡
410．．．測試針
S101-S110．．．封裝方法第一實施例之步驟
S201-S211．．．封裝方法第二實施例之步驟
S301-S311．．．封裝方法第三實施例之步驟
S3011-S3081．．．封裝方法第四實施例之步驟
S401-S411．．．封裝方法第五實施例之步驟
第1A圖至第1F圖係表示習知晶圓級封裝的簡單示意圖。
第2A圖至第2D圖係表示本發明超薄多層基板之封裝方法前四個步驟之簡單示意圖。
第3A圖至第3D圖係本發明超薄多層基板在進行封裝前以測探針卡進行基板測試之簡單示意圖。
第4圖係表示本發明超薄多層基板之封裝方法第一實施例之流程圖。
第5圖係表示本發明超薄多層基板之封裝方法第二實施例之流程圖。
第6圖係表示本發明超薄多層基板之封裝方法第三實施例之流程圖。
第7圖係表示本發明超薄多層基板之封裝方法第四實施例之流程圖。
第8圖係表示本發明超薄多層基板之封裝方法第五實施例之流程圖。

Claims (14)

  1. 一種超薄多層基板之封裝方法，包括：提供一暫時性載板；交替形成複數個金屬層及複數個介電層，用以製作該超薄多層基板，該超薄多層基板具有複數個封裝單元，用以各別封裝複數個晶片；於該超薄多層基板表面形成複數個焊墊層；將該超薄多層基板與該暫時性載板分離；對該超薄多層基板未被覆蓋之一上表面及一下表面進行測試，用以汰選具有缺陷的該些封裝單元；以該些封裝單元為單位，切割該超薄多層基板，用以篩選出不具有缺陷的該些封裝單元；以模封板之尺寸為單位，重組不具有缺陷的該些封裝單元後，各別以覆晶接合方式與該些晶片接合；以及對該模封板上已覆晶接合之該些晶片進行模封。
  2. 如申請專利範圍第1項所述超薄多層基板之封裝方法，對該超薄多層基板進行測試之步驟中，更進一步包括以一夾持系統夾持該超薄多層基板，同時至少露出該超薄多層基板之上下表面的該些焊墊層之步驟，以進行測試。
  3. 如申請專利範圍第2項所述超薄多層基板之封裝方法，於夾持該超薄多層基板之步驟中，更進一步包括控制該超薄多層基板所受張力及該超薄多層基板的接觸電阻為一預定值之步驟。
  4. 如申請專利範圍第1項所述超薄多層基板之封裝方法，其中該些封裝單元係透過該些焊墊層，以覆晶接合方式與該些晶片接合。
  5. 如申請專利範圍第1項所述超薄多層基板之封裝方法，其中該模封係採用移轉模封。
  6. 如申請專利範圍第1項所述超薄多層基板之封裝方法，於進行該模封之步驟後，更包括一對該些封裝單元各別與複數個錫球接合形成一球閘陣列之步驟。
  7. 如申請專利範圍第6項所述超薄多層基板之封裝方法，於形成該球閘陣列之步驟後，更包括一以該些封裝單元為單位，切割該模封板之步驟。
  8. 如申請專利範圍第7項所述超薄多層基板之封裝方法，於切割該模封板之步驟後，更包括一各別對該些已模封之晶片進行測試之步驟。
  9. 如申請專利範圍第1項所述超薄多層基板之封裝方法，於進行該模封之步驟前，更包括一對該些封裝單元各別與一球閘陣列封裝元件接合之步驟，該步驟係在該些封裝單元以覆晶接合方式與該些晶片接合之同一表面進行。
  10. 如申請專利範圍第9項所述超薄多層基板之封裝方法，於進行與該球閘陣列封裝元件接合之步驟前，更進一步包括對該些封裝單元進行助焊劑或錫膏印刷之步驟。
  11. 如申請專利範圍第1項所述超薄多層基板之封裝方法，各別以覆晶接合方式與該些晶片接合之步驟前，更包括一對該些封裝單元各別與一球閘陣列封裝元件接合之步驟。
  12. 如申請專利範圍第11項所述超薄多層基板之封裝方法，其中與該球閘陣列封裝元件接合之步驟係在該些封裝單元，各別以覆晶接合方式與該些晶片接合之同一表面進行。
  13. 如申請專利範圍第1項所述超薄多層基板之封裝方法，其中各別以覆晶接合方式與該些晶片接合之步驟中，更同 時包括對該些封裝單元各別與一球閘陣列封裝元件接合之步驟，該球閘陣列封裝元件係在該些封裝單元，各別以覆晶接合方式與該些晶片接合之同一表面進行接合。
  14. 如申請專利範圍第1項所述超薄多層基板之封裝方法，以模封板之尺寸為單位，重組不具有缺陷的該些封裝單元後，各別以覆晶接合方式與該些晶片接合之步驟中，該覆晶接合方式係以金凸塊進行接合。
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