CN101197360A - 多芯片封装及其方法 - Google Patents

多芯片封装及其方法 Download PDF

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CN101197360A
CN101197360A CNA2007101969953A CN200710196995A CN101197360A CN 101197360 A CN101197360 A CN 101197360A CN A2007101969953 A CNA2007101969953 A CN A2007101969953A CN 200710196995 A CN200710196995 A CN 200710196995A CN 101197360 A CN101197360 A CN 101197360A
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crystal grain
dielectric layer
substrate
layer
heavy distribution
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杨文焜
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Abstract

一种多芯片封装结构，包含具有于其上表面内的晶粒接收凹处以及穿过其中的第一穿孔结构的基板，而具有端点垫的电路则形成于第一穿孔结构之下。第一晶粒位于晶粒接收凹处内，第一介电层则形成于第一晶粒以及基板上。第一重分布层形成于第一介电层上，并经由第一穿孔结构耦合至第一晶粒与该端点垫，第二介电层具有形成于第一重分布层上的开口，第二晶粒则附着于第二介电层上。围绕第二晶粒的围绕材料具有对准此开口的第二穿孔结构，第三介电层形成于第二晶粒以及围绕材料上。第二重分布层形成于第三介电层上，并经由第二穿孔结构耦合至第二晶粒的结合垫以及端点垫，保护层则形成于第二重分布层上。

Description

多芯片封装及其方法
技术领域
本发明是关于一种系统级封装(system in package；SIP)的结构，特别是关于具有SIP面板等级封装(panel scale package；PSP)。
背景技术
于半导体组件领域中，组件的密度持续增加而组件的尺寸却不断缩小。为配合上述情况，如此高密度组件中封装或互连技术的需求亦日益增加。传统上，覆晶封装(flip-chip)附着方法中焊锡凸块阵列是形成于晶粒表面，此焊锡凸块的形成可利用焊锡复合材料通过防焊层(solder mask)而予以施行，以用于产生期望的焊锡凸块形态。芯片封装的功能包含功率分配、信号分配、散热、保护及支撑等，当半导体变为更加复杂，传统封装技术例如导线架封装、软性封装、刚性封装技术等已无法满足欲产生具较高密度组件的较小芯片的需求。
公知技术中，通常将多芯片模块以及混合电路(hybrid circuits)附着于基板上，且组件亦密封于外壳中。一般而言是采用多层基板，其包含介于多个介电材料层之间的多个导电层，并由层叠技术制造此多层基板，其中金属导体乃形成于个别介电层上，接着堆叠这些介电层并使其结合在一起。
高密度与高效能的需求加速了系统芯片(System On Chip；SOC)以及系统级封装的发展，多芯片模块(Multi-Chip Module；MCM)并已广泛地利用于整合具有不同功能的芯片，而多芯片封装或者多芯片模块技术是指将多个未封装集成电路(裸晶；bare die)安装于基础材料上的程序，多个晶粒将被封装在完整的密封材料或者其它聚合物的中。MCM提供了高密度封装，所以于电脑中主机板上仅占去较少的空间，且MCM亦有利于整合功能测试。
再者，由于传统封装技术必须切割圆片上的晶粒，并个别封装这些晶粒，因而此种工艺相当耗费时间。因为芯片封装技术受到集成电路发展影响甚大，所以封装技术要求的尺寸等同于电子组件一般。基于上述理由，今日封装技术的发展便偏向于球闸阵列封装(BGA)、覆晶球闸阵列封装(FC-BGA)、芯片级封装(CSP)以及圆片级封装(WLP)。圆片级封装的意义为于圆片上进行完整封装以及所有连接，并于切割为芯片前进行其它处理程序。一般而言，在所有组合程序或封装程序完成后，将自具有数个半导体晶粒的圆片分出个别的半导体封装。此种圆片级封装具有极小的尺寸以及非常好的电性。
WLP为一种先进的封装技术，其中晶粒的制造与测试均于圆片上进行，且接着由切割而单一化以用于在表面黏着生产线中组装。由于圆片级封装技术将整个圆片作为单一个体来运用，而非着眼于单一的芯片与晶粒，所以在进行切割程序前，封装与测试均已完成，并且WLP为相当高阶的技术，因此线接合、晶粒黏着及底部填充的程序可予以忽略。利用圆片级封装技术，可减少成本及制造时间且圆片级封装的结果结构可相当于晶粒，故此技术可满足电子装置的微型化需求。
虽圆片级封装技术具有上述优点，然而仍存在一些影响圆片级封装技术的接受度的问题。例如，虽然利用WLP技术可降低IC与互相连接的基板间CTE的不相配，然随着组件尺寸的缩减，WLP的基板材质间CTE的不同将成为结构机械稳定度的另一个关键因素。再者，在圆片级的芯片级封装中，乃利用涉及重分布层的传统重分布程序，将形成在半导体晶粒上的数个结合垫重新分布在区域阵列类型中的数个金属垫中。锡球将直接熔接在此金属垫上，此金属垫乃由重分布程序而形成为区域阵列类型。
一般而言，所有的堆叠重分布层均形成在晶粒上的组合层上，因此增加了封装的厚度，此有违缩减芯片尺寸的需求。
发明内容
本发明的目的在于提供一种多芯片封装及其方法。
为实现上述目的，本发明提供的多芯片封装结构，其包含：
一基板，具有于其上表面内的晶粒接收凹处以及穿过其中的第一穿孔结构，而具有端点垫的电路则形成于该第一穿孔结构之下；
一第一晶粒，位于该晶粒接收凹处内；
一第一介电层，形成于该第一晶粒以及该基板上；
一第一重分布层，形成于该第一介电层上，并经由该第一穿孔结构耦合至该第一晶粒与该端点垫；
一第二介电层，具有形成于该第一重分布层上的开口；
一第二晶粒，附着于该第二介电层上；
一围绕材料，围绕该第二晶粒，并具有对准该开口的第二穿孔结构；
一第三介电层，形成于该第二晶粒以及该围绕材料上；
一第二重分布层，形成于该第三介电层上，并经由该第二穿孔结构耦合至该第二晶粒以及该端点垫；以及
一保护层，形成于该第二重分布层上。
所述的多芯片封装结构，其中，该介电层包含弹性介电层。
所述的多芯片封装结构，其中，该第一与第二重分布层是自该第一与第二晶粒扇出。
所述的多芯片封装结构，其中，该第一与第二重分布层通过该第一与第二穿孔结构向下与该端点垫进行通讯。
本发明提供的多芯片封装结构，还包含：
一基板，具有于其上表面内以接收至少两个晶粒的至少两个晶粒接收凹处以及穿过其中的穿孔结构，而具有端点垫的电路则形成于该穿孔结构下；
一第一晶粒以及一第二晶粒，个别位于该至少两个晶粒接收凹处内；
一第一介电层，形成于该第一晶粒、该第二晶粒以及该基板上；
一重分布层，形成于该第一介电层上，耦合至该第一晶粒、该第二晶粒以及该端点垫；以及
一第二介电层，形成于该重分布层上。
所述的多芯片封装结构，其中，该介电层包含弹性介电层。
所述的多芯片封装结构，其中，该重分布层是自该第一与第二晶粒扇出。
所述的多芯片封装结构，其中，该重分布层通过该穿孔结构向下与该端点垫进行通讯。
本发明提供的形成半导体组件封装的方法，其中，该方法的步骤包含：
提供基板，该基板具有晶粒接收凹处形成于其上表面内以及形成穿过其中的穿孔结构，而具有端点垫的电路则形成于该穿孔结构下；
利用取放精密校准系统将第一晶粒以预期之间距重新分布于工具上；
将黏着物附着于该第一晶粒背侧；
使该基板与该晶粒背侧结合，并分开该工具；
将第一介电层涂布于该第一晶粒与该基板上；
于该第一介电层上形成第一重分布层；
于该第一重分布层上形成该第二介电层；
将第二晶粒附着于该第二介电层上；
形成介电材料以填入该第二晶粒周围区域；
于该第二晶粒上形成第三介电层；
于该第三介电层上形成第二重分布层；以及
形成第四介电层以保护该第一与第二重分布层。
所述的方法，其中，该第一与第二重分布层是由包含钛/铜/金合金或钛/铜/镍/金合金的合金所构成，并且该基板的材质包含环氧树脂、双马来酰亚胺三嗪树脂、印刷电路板、合金、玻璃、硅树脂、陶瓷或金属。
附图说明
图1呈现根据本发明较佳实施例的堆叠扇出SIP结构的截面图。
图2呈现根据本发明实施例的堆叠扇出SIP结构的截面图。
图3呈现根据本发明实施例的平行扇出SIP结构的截面图。
图4呈现根据本发明实施例的堆叠扇出SIP结构的截面图。
具体实施方式
本发明提供的具有高度可靠性以及低成本优势的SIP，本发明的多芯片封装结构包含具有于其上表面内的晶粒接收凹处(die receiving cavity)以及穿过其中的第一穿孔结构(first through hole structure)的基板(structure)，而具有端点垫(terminal pad)的电路则形成于第一穿孔结构之下。第一晶粒(die)位于晶粒接收凹处内，第一介电层(dielectric layer)则形成于第一晶粒以及基板上。第一重分布层形成于第一介电层上，并经由第一穿孔结构耦合至第一晶粒与该端点垫，第二介电层具有形成于第一重分布层上的开口，第二晶粒则附着于第二介电层上。围绕第二晶粒的围绕材料具有对准此开口的第二穿孔结构，第三介电层形成于第二晶粒以及围绕材料上。第二重分布层形成于第三介电层上，并经由第二穿孔结构耦合至第二晶粒的结合垫以及端点垫，保护层则形成于第二重分布层上。第一与第二重分布层是自第一与第二晶粒扇出，并通过第一与第二穿孔结构向下与端电点进行通讯。
另外，本发明所提供的另一多芯片封装结构包含基板，此基板具有于其上表面内以接收至少两个晶粒的至少两个晶粒接收凹处，以及穿过其中的穿孔结构，而具有端点垫的电路则形成于穿孔结构下。第一晶粒以及一第二晶粒个别位于至少两个晶粒接收凹处内，第一介电层形成于第一晶粒、第二晶粒以及基板上。重分布层形成于第一介电层上，并耦合至第一晶粒、第二晶粒以及端点垫，而第二介电层则形成于重分布层上，以作为保护层。
第一介电层包含弹性材料，或者此第一介电层可包含硅树脂介电基材(silicone dielectric based material)、苯环丁烯(Benzocyclobutene；BCB)或聚酰亚胺(Polyimide；PI)，其中硅氧烷基材包含硅氧烷聚合物(siloxanepolymers；SINR)、道康宁(Dow Coming)WL5000系列或者两者的组合。第一介电层亦可包含感光(可曝光成像)层。
基板的材质可包含环氧树脂类型的FR5、FR4、双马来酰亚胺三嗪树脂(Bismaleimide triazine；BT)、印刷电路板(PCB)、合金、玻璃、硅树脂、陶瓷或金属。或者，基板的材质可包含Alloy42(42％的镍、58％的铁)或Kovar(29％的镍、17％的钴、54％的铁)。
以下将由较佳实施例配合附图详细地说明本发明，然应可理解者为这些较佳实施例仅为例示之用，除了文中提及的实施例外，本发明还可广泛地以其它方式实施，并且除了依各项权利要求所界定外，本发明的范围不受其它内容所限制。
本发明揭露的WLP结构，是利用具有预设电路的基板，并且此基板具有形成于其上的穿孔(through holes)以及基板内的凹处(cavity)。感光物质则涂布于晶粒以及预先成型的基板上，此感光物质最好由弹性材料构成。
图1呈现根据本发明较佳实施例用于SIP的面板级封装的截面图，其中SIP的结构包含基板2，具有形成于其上的晶粒接收凹处(die receivingcavity)4，以接受晶粒18。并有数个穿孔6自基板2的上表面贯穿至其下表面，而导电物将被填入穿孔6以提供电子流通。端点垫8则位于基板的下表面，并以导电物连接至穿孔6，传导电路线(conductive circuit trace)10形成于基板2的下表面上，而例如防焊环氧树脂(solder mask epoxy)的保护层12则形成于传导电路线10上以保护。
晶粒18是置于基板2上晶粒接收凹处4内，并以黏着(晶粒附着)物14固定，而接触垫(焊垫)20则形成于晶粒18上，感光层或介电层22覆盖晶粒18，并且填入晶粒18与凹处4边墙间的空隙。数个开口通过微影工艺或曝光显影程序而形成于介电层22内，此数个开口个别通过穿孔6以及接触或I/O垫20与接点对齐排列。重分布层(RDL)24，或称为导线24，则由将形成于于介电层22上的选定部分移除以形成于介电层22上，RDL24将通过I/O垫20与晶粒18保持电性连接。RDL的一部分将填入介电层22中的开口，因而形成通过穿孔6上的金属以及焊垫20上的垫金属的连接。介电层26覆盖RDL 24，并形成于晶粒18以及基板2之上，并填入晶粒18周围的空间。数个开口形成于介电层26内，并与RDL 24对齐排列以暴露RD 24的部分。
第二芯片30具有第二接触垫36，并通过黏着物28附着于介电层26之上，并于第二芯片20周围涂布介电材料32。第二穿孔34是形成于介电材料32内，介电层50具有形成于第二芯片(晶粒)30上的开口，此开口是以公知的方式形成，且与第二芯片30的接触垫以及第二穿孔34对齐，并将导电物填入第二穿孔34以及介电层26的开口中。第二RDL 38形成于介电层50上，并填入介电层的开口，保护层40则形成于第二芯片30以及第二RDL 38之上，且遮盖物42乃选择地形成于保护层40之上。遮盖物42的材料可为环氧树脂、橡胶、树脂、金属、塑胶、陶瓷等(最好为金属材质，以提供电屏蔽、散热以及较佳的印字品质)。导电凸块16耦合至端点垫8，具有导电凸块16的结构称为BGA类型SIP或者SIP-BGA。若略去导电凸块，则为LGA类型SIP或者SIP-LGA，请参照图2，由于相关部分与图1相似，因此将省略相同参照编号部分的说明。
应留意者为，第一芯片18可通过第一穿孔6、第二穿孔34、第一RDL24、第二RDL 38而与第二芯片30进行通讯，此为选择性的配置，并且可发现到第一芯片18形成于凹处4内，降低了SIP的高度。两RDL结构均为扇出型(Fan-Out)而增加了球间距(ball pitch)，遂增强了可靠度与散热能力。
基板2的材质最好为有机基板，例如环氧树脂类型的FR5、双马来酰亚胺三嗪树脂(Bismaleimide triazine；BT)、具有已定义凹处的PCB或者具有预先蚀刻电路的Alloy 42。有机基板中具有较高的转移温度(transitiontemperature；Tg)者为环氧树脂类型的FR5或者BT类型的基板，Alloy 42是由42％的镍(Ni)以及58％的铁(Fe)组成，且亦可采用Kovar，其由29％的镍、17％的钴(Co)以及54％的铁组成，此外亦可采用玻璃、陶瓷、硅，因为其热膨胀系数(CTE)较低。
在本发明的某一实施例中，介电层22最好为弹性介电材质，其由包含有硅氧烷聚合物(siloxane polymers；SINR)、道康宁(Dow Coming)WL5000系列、以及两者的组合的硅树脂介电基材所制成。在另一实施例中，介电层由包含聚亚酰胺(PI)或硅树脂的材料所组成。其最好为感光层以简化工艺。
在本发明的某一实施例中，弹性介电层22为一种具有大于100(ppm/℃)的热膨胀系数、约40％的伸长率(最好30％至50％)以及介于塑胶及橡胶之间的硬度的材料，弹性介电层18的厚度则取决于在温度循环测试期间累积于重分布层/介电层界面中的应力。
在本发明的一实施例中，RDL 24的材料包含钛/铜/金合金或钛/铜/镍/金合金，其厚度是于2微米至15微米间。钛/铜合金由溅镀技术形成作为种子金属层(seed metal layers)，且铜/金或铜/镍/金合金由电镀技术形成。利用电镀程序形成重分布层可使重分布层具有足够的厚度以抵抗温度循环期间的热膨胀系数不匹配。金属垫20可为铝或铜或其结合。若扩散型圆片级封装(FO-WLP)结构利用硅氧烷聚合物(SINR)作为弹性介电层且利用铜作为重分布层的金属，累积于重分布层/介电层界面内的应力将会降低。
基板2可为圆形，例如圆片型，其半径可为200毫米、300毫米或以上。基板亦可为矩形，例如面板型。图3呈现预先成型的基板2的截面，由附图可知，基板2形成有凹处4以及内建电路10，且穿孔结构6中填有金属。在图3上部，第一芯片与第二芯片并未配置为堆叠结构，第二芯片30位于第一芯片18旁，且两芯片乃通过垂直通讯线24a互相通讯，而非通过穿孔结构。如图所示，此结构包含两个凹处以个别接收第一与第二芯片，其中并个别呈现BGA与LGA两种类型。
另外，图4中的实施例结合了图1与图3，至少有四个芯片配置于SIP中，上层的芯片可通过RDL 36进行通讯，而下层的芯片则可通过RDL 24a耦合，并且上层的芯片至少可通过穿孔结构34、34a互相通讯。
如图1至图4所示，RDL 24、38自晶粒扇出，并向下与封装穿孔结构下的端点垫8进行通讯，与公知的MCM技术不同者为其堆叠结构是于晶粒上，因而增加了封装的厚度，违反了降低晶粒封装厚度的原则。与其相反地，本发明的端点垫是位于基板上与晶粒垫相对之侧，通讯线路经由穿孔穿过基板2，并将讯号引导至端点垫8。据此，将显着地降低晶粒封装厚度，使本发明的封装较公知技术薄。再者，基板于封装前便已预先备妥，凹处4以及线路10亦已预先设置，所以可增加产量。本发明在此揭露于RDL上没有堆叠组合层的扇出WLP。
在处理完圆片并背面研磨至期望的厚度后，便将圆片切分为晶粒。基板上预先形成有内建的电路以及至少一个凹处，基板的材质最好为转化温度(Tg)较高的FR5/BT印刷电路板。基板可具有不同大小的凹处以接收不同的芯片，并且凹处的深度较晶粒的厚度多20至30微米以容纳晶粒附着材料。本发明的程序包含提供校准工具(薄板)，其具有形成其上的校准图型。接着，将图样黏着剂印刷于工具上(用以黏附晶粒的表面)，然后利用具有覆晶功能的取放精密校准系统以基已知为完好的晶粒以期望之间具重新分布于工具上，图样黏着剂将芯片黏着于工具上。随后，将晶粒附着材料印刷于晶粒背侧，并利用板结合器(panel bonder)将基板固定于晶粒背侧，基板的上表面除了凹处外亦黏贴于图样黏着剂上，接着施行真空处理(vacuum curing)，接着将工具自面板级圆片分离。
另外，可利用具有精密校准能力的晶粒结合器，且晶粒附着材料可配置于基板的凹处上，将晶粒放至于基板的凹处上，并将晶粒附着材料加热以确保晶粒固着于基板上。
一旦将晶粒重新分布于基板上，便施行洁净程序，以湿式清洗及/或干式清洗来清洁晶粒表面。其后的步骤为将介电材料涂布于面板的表面上，并接着施行光微影蚀刻程序以开启接触以及铝接合垫。之后，执行等离子清洗(plasma clean)步骤以清洗通孔及铝接合垫的表面，并溅镀钛/铜作为种子金属层，且接着涂布光阻(PR)于介电层及种子金属层上，以用于形成重分布金属层(RDL)的图形。接着进行电镀程序以形成铜/金或铜/镍/金作为重分布层金属，然后去除光阻(PR)并进行金属湿蚀刻以形成重分布层金属导线。随后为涂布或印刷顶部介电层，并且/或者开启接触接触垫，以完成第一层面板程序。
接着并以后续的程序完成第二层晶粒，且较薄的晶粒(大约50微米)最好能够获得较佳的程序效能与可靠度。此程序包含将晶粒附着材料28印刷于第二层晶粒30的背侧上，第一个处理过的面板将与第二层晶粒与工具结合，然后于处理后将工具与面板分离，接着清洁第二层晶粒的表面，并涂布或印刷介电材料，以填满晶粒周边以及上方没有晶粒的区域。使介电层50覆盖晶粒30，并由微影工艺开启接触垫。随后处理介电层并清洁第二层晶粒30的I/O垫以及穿孔。执行溅镀钛/铜步骤以形成种子金属层，并涂布光阻(PR)以形成RDL图样，且使用电路步骤来形成铜/金于RDL图样内，然后除去光阻并进行金属湿蚀刻以形成重分布层金属导线38，形成上方介电层40以保护此RDL导线38，并形成覆盖层42以供上方印字用。
于设置球或印刷焊锡糊剂后，施行热回融程序以回焊基板侧(用于BGA类型)。接着执行测试，由利用垂直式探针卡(vertical probe card)施行面板圆片级最终测试。测试完毕后，切割基板将封装分成具有多芯片的个别SIP单元，接着拣选个别封装并将封装置于托盘或卷带及卷轴上。
本发明的优点为：
基板预先备妥预形成凹处；凹处的大小与晶粒大小每侧加50至100微米相当；由填充弹性介电材料可用作为应力缓冲释放区域，以吸收硅晶粒与基板(FR5/BT)间热膨胀系数不同所造成的热应力。由于应用简化的积层于晶粒表面上方，故封装生产率将会增加(制造周期减少)。端点垫系形成于晶粒主动面的相反侧(预先形成)。
晶粒放置程序与现行程序相同，惟本发明无须填充核心黏胶(树脂、环氧树脂混合物、硅氧烷橡胶等)。于焊锡与主机板PCB结合时没有CTE不匹配的问题，且晶粒与基板FR4之间的深度仅为大约20至30微米之间(用于容纳晶粒附着材料的厚度)，当晶粒附着于基板的凹处上后，晶粒与基板的表面高低可趋于一致。仅将硅树脂介电材料(silicone dielectricmaterial；最好为SINR)涂布于晶粒主动面及基板(最好为FR4、FR5或BT)表面上。由于介电层(SINR)为感光层，故只利用光屏蔽程序即得以开启接触通孔结构。于SINR涂布时利用真空工艺可消除气泡的问题。在基板与晶粒(芯片)结合之前，晶粒附着材料系印刷于晶粒背侧。封装与面板级的可靠性均较以往提升，特别是面板级温度循环测试，盖因基板的CTE与PCB主机板相同，因此没有热机械应力施加于锡球或锡凸块上。
本发明使成本降低并且简化工艺，而使复合封装(多晶粒封装)变得更为容易。
虽然本发明的较佳实施例以详述于上，但本发明所属领域中具有通常知识者应可理解本发明并非仅局限于上述实施例，毋宁更应包含所有未悖离各请求项所定义的发明的精神与范围的所有调整与更替。

Claims (10)

1.一种多芯片封装结构，其特征为包含：
一基板，具有于其上表面内的晶粒接收凹处以及穿过其中的第一穿孔结构，而具有端点垫的电路则形成于该第一穿孔结构之下；
一第一晶粒，位于该晶粒接收凹处内；
一第一介电层，形成于该第一晶粒以及该基板上；
一第一重分布层，形成于该第一介电层上，并经由该第一穿孔结构耦合至该第一晶粒与该端点垫；
一第二介电层，具有形成于该第一重分布层上的开口；
一第二晶粒，附着于该第二介电层上；
一围绕材料，围绕该第二晶粒，并具有对准该开口的第二穿孔结构；
一第三介电层，形成于该第二晶粒以及该围绕材料上；
一第二重分布层，形成于该第三介电层上，并经由该第二穿孔结构耦合至该第二晶粒以及该端点垫；以及
一保护层，形成于该第二重分布层上。
2.如权利要求1所述的多芯片封装结构，其特征为，该介电层包含弹性介电层。
3.如权利要求1所述的多芯片封装结构，其特征为，该第一与第二重分布层是自该第一与第二晶粒扇出。
4.如权利要求1所述的多芯片封装结构，其特征为，该第一与第二重分布层通过该第一与第二穿孔结构向下与该端点垫进行通讯。
5.一种多芯片封装结构，其特征为，包含：
一基板，具有于其上表面内以接收至少两个晶粒的至少两个晶粒接收凹处以及穿过其中的穿孔结构，而具有端点垫的电路则形成于该穿孔结构下；
一第一晶粒以及一第二晶粒，个别位于该至少两个晶粒接收凹处内；
一第一介电层，形成于该第一晶粒、该第二晶粒以及该基板上；
一重分布层，形成于该第一介电层上，耦合至该第一晶粒、该第二晶粒以及该端点垫；以及
一第二介电层，形成于该重分布层上。
6.如权利要求5所述的多芯片封装结构，其特征为，该介电层包含弹性介电层。
7.如权利要求5所述的多芯片封装结构，其特征为，该重分布层是自该第一与第二晶粒扇出。
8.如权利要求5所述的多芯片封装结构，其特征为，该重分布层通过该穿孔结构向下与该端点垫进行通讯。
9.一种形成半导体组件封装的方法，其特征为，该方法的步骤包含：
提供基板，该基板具有晶粒接收凹处形成于其上表面内以及形成穿过其中的穿孔结构，而具有端点垫的电路则形成于该穿孔结构下；
利用取放精密校准系统将第一晶粒以预期之间距重新分布于工具上；
将黏着物附着于该第一晶粒背侧；
使该基板与该晶粒背侧结合，并分开该工具；
将第一介电层涂布于该第一晶粒与该基板上；
于该第一介电层上形成第一重分布层；
于该第一重分布层上形成该第二介电层；
将第二晶粒附着于该第二介电层上；
形成介电材料以填入该第二晶粒周围区域；
于该第二晶粒上形成第三介电层；
于该第三介电层上形成第二重分布层；以及
形成第四介电层以保护该第一与第二重分布层。
10.如权利要求9所述的方法，其特征为，该第一与第二重分布层是由包含钛/铜/金合金或钛/铜/镍/金合金的合金所构成，并且该基板的材质包含环氧树脂、双马来酰亚胺三嗪树脂、印刷电路板、合金、玻璃、硅树脂、陶瓷或金属。
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