CN101335265A - 具有晶粒功能之半导体封装结构 - Google Patents

具有晶粒功能之半导体封装结构 Download PDF

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Publication number
CN101335265A
CN101335265A CNA2008101275307A CN200810127530A CN101335265A CN 101335265 A CN101335265 A CN 101335265A CN A2008101275307 A CNA2008101275307 A CN A2008101275307A CN 200810127530 A CN200810127530 A CN 200810127530A CN 101335265 A CN101335265 A CN 101335265A
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Prior art keywords
crystal grain
substrate
connection gasket
perforation
semiconductor device
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CNA2008101275307A
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杨文焜
张瑞贤
李基城
杨文彬
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Publication of CN101335265A publication Critical patent/CN101335265A/zh
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Abstract

本发明提供一种具有伪晶粒之半导体封装结构，包含第一基底具有晶粒置入穿孔形成于其上；第一晶粒具有第一连接垫及第二晶粒具有第二连接垫，且分别配置于晶粒置入穿孔之内；黏着层形成于第一晶粒与第二晶粒间之间隙及第一基底之晶粒置入穿孔之侧壁；重布线形成以将第一基底上之第一接触垫分别耦合至第一连接垫与第二连接垫；以及保护层形成于重布线、第一晶粒、第二晶粒及第一基底之上。

Description

具有晶粒功能之半导体封装结构
【技术领域】
本发明系有关一种半导体装置封装之结构，特别是关于一种具有伪晶粒功能之半导体封装之结构，因此得以缩减封装尺寸及增进良率与可靠度。
【背景技术】
近年来，高科技电子制造产业日益趋向更精致(feature-packed)与人性化(humanized)之电子产品。快速发展之半导体技术更将半导体封装导向缩减之尺寸，因而采用多重接脚(multi-pin)、良好间距(fine pitch)、小型化(minimization)之电子组件(electric components)及其相似物。
由于一般封装技术必须先将晶圆上之晶粒分割为个别晶粒，再将晶粒分别封装，因此上述技术之制程十分费时。由于晶粒封装技术与集成电路之发展有密切关联，因此封装技术对于电子组件之尺寸要求越来越高。基于上述之理由，现今之封装技术已逐渐趋向采用球门阵列封装(ball grid array，BGA)、覆晶球门阵列封装(flip chip ball grid array，FC-BGA)、芯片尺寸封装(chip sizepackage，CSP)、晶圆级封装(Wafer Level Package，WLP)之技术。应可理解「晶圆级封装(WLP)」系指晶圆上所有封装及交互连接结构，如同其它制程步骤，系于切割(singulation)为个别晶粒之前进行。利用上述晶圆级封装(WLP)技术，可产生具有极小尺寸及良好电性之晶粒。根据上述晶圆级封装(WLP)技术之优点，仍存在一些可能影响晶圆级封装(WLP)技术接受度(acceptance)之问题。一般而言，由于需要具有多重晶粒之封装结构，因此封装结构之尺寸便随多重晶粒之总高度而增加，而使得制程越驱复杂化。
图1系为具有堆栈晶粒(stacked dice)之习知封装。封装结构100包含第一晶粒120具有第一连接垫(first bonding pads)116形成于其上，及第二晶粒122具有第二连接垫118形成于其上，第一晶粒120与第二晶粒122系形成于第一基底104之上，且具有第一连接垫114形成于其上。封装100更包含第三晶粒124具有第三连接垫112，且形成于第一基底104之下，及配置于具有第二接触垫(second contact pads)110之第二基底102之上。黏着层(attached material)106与107分别形成于第三晶粒124与第一基底104之下方，而黏着层108形成于第一晶粒120与第二晶粒122之下方。再者，第三连接垫112系利用连接线(bonding wires)126连接至第二接触垫110，第一接触电114系利用连接线128连接至第二接触垫110，并且第一连接线116与第二连接线118系分别藉由连接线130与132而分别连接至第一接触垫114。接着，保护层(protection layer)145系形成以覆盖第一晶粒120、第二晶粒122、第三晶粒124，以及焊锡凸块(solder bumps)150系形成于第二基底102之下层。因此，封装100之尺寸系为累积(accumulated)之尺寸，且约略等于每一材料层尺寸之总和，然而上述封装结构会随着晶粒数目增加，而使制程越趋复杂且提高成本。
有鉴于上述，本发明提供一种具有伪晶粒功能(pseudo chipsfunction)之新颖结构，以克服上述习知技术之缺点。
【发明内容】
本发明系为美国专利申请第11/648,688号之部份连续申请案(continue-in-part(CIP)application)之对应台湾申请案，上述美国专利申请案之名称为「Wafer Level Package with Die ReceivingThrough-Hole and Method of the Same」，且申请日为2007年1月3日，在此一并作为参考。
在此，本发明将详细地叙述一些实施例。然而，值得注意的是除了这些明确之叙述外，本发明可以实施在其它广泛范围之实施例中，并且本发明之范围不受限于上述实施例，其当视后述之专利申请范围而定。
本发明之一目的系在于揭露一种半导体封装结构，可提供具有伪晶粒功能之新颖结构。
本发明之另一目的系在于揭露一种半导体封装结构，可提供半导体封装之小型化结构(small foot print)与薄型(thinner)之结构。
本发明之又一目的系在于揭露一种半导体封装结构，可得到较佳之可靠度(reliability)。
本发明之再一目的系在于揭露一种半导体封装结构，可降低成本及提高良率(yield)。
本发明提供一种半导体装置封装之结构，包含第一基底具有晶粒置入穿孔；第一晶粒具有第一连接垫及第二晶粒具有第二连接垫，且分别配置于晶粒置入穿孔之内；黏着层形成于第一晶粒与第二晶粒间之间隙及第一基底之晶粒置入穿孔之侧边；以及重布线形成以将第一基底上之第一连接垫分别耦合至第一连接垫与第二连接垫。
本发明提供一种半导体装置封装之结构，包含第一基底具有第一晶粒置入穿孔；第一晶粒具有第一连接垫及第二晶粒具有第二连接垫，且分别配置于第一晶粒置入穿孔之内；第一黏着层形成于第一与第二晶粒间之间隙及第一基底之第一晶粒置入穿孔之侧壁；重布线形成以将第一基底上之接触垫分别耦合至第一连接垫与第二连接垫；保护层形成于重布线、第一晶粒、第二晶粒及第一基底之上；第二基底具有第二晶粒置入穿孔与第二接触垫，且形成于第二黏着层之上及第一基底之下；以及第三晶粒具有第三连接垫配置于第二晶粒置入穿孔之内。
本发明提供一种半导体装置封装之结构，包含第一基底具有晶粒置入穿孔形成于其中；第一晶粒具有第一连接垫及第二晶粒具有第二连接垫，且分别配置于晶粒置入穿孔之内；第一黏着层形成于第一与第二晶粒间之间隙及第一基底之第一晶粒置入穿孔之侧壁；重布线形成以将第一基底上之第一接触垫分别耦合至第一连接垫与第二连接垫；保护层形成于重布线、第一晶粒、第二晶粒及第一基底之上；第三晶粒具有第三连接垫配置于第一基底之下；以及第二基底具有第二接触垫及电路线形成于其中及第三晶粒之下。
【附图说明】
藉由参考下列详细叙述，将可以更快地了解上述观点以及本发明之优点，并且藉由下面的描述以及附加图式，可以更容易了解本发明之精神。其中：
图1系为根据习知技术之半导体装置封装结构之剖面示意图。
图2系为根据本发明之一实施例之半导体装置封装结构之上视示意图。
图3系为根据本发明之一实施例之半导体装置封装结构之剖面示意图。
图4系为根据本发明之另一实施例之半导体装置封装结构之剖面示意图。
图5系为根据本发明之另一实施例之半导体装置封装结构之剖面示意图。
图6系为根据本发明之另一实施例之半导体装置封装结构之剖面示意图。
图7系为根据本发明之另一实施例之半导体装置封装结构之剖面示意图。
图中：
100    封装结构                       202    第一基底
102    第二基底                       203    第一晶粒置入穿孔
104    第一基底                       204    第二基底
106、107、108  黏着层                 206    金属或导电层
110    第二接触垫                     208    黏着层
112    第三连接垫                     210    第一接触垫
114    第一接触垫                     216    第一连接垫
116    第一连接垫                     218    第二连接垫
118    第二连接垫                     220    第一晶粒
120    第一晶粒                       222    第二晶粒
122    第二晶粒                       226    重布线
124    第三晶粒                       230    介电层
126、128、130、132  连接线            232    保护层
145    保护层                         240    黏着层
150    焊锡凸块                       300    封装结构
200    封装结构                       302    基底
303    第一晶粒置入穿孔       503    第二晶粒置入穿孔
308    黏着层                 504    第三晶粒
310    接触垫                 505    第三接触垫
316    第一连接垫             506    金属或导电层
318    第二连接垫             508    黏着层
320    第一晶粒               509    第二基底
322    第二晶粒               510    第二接触垫
326    连接线                 512、514    连接线
400    封装结构               545    保护层
402    第二基底               550    焊锡层
404    第二接触垫             600    封装结构
406    连接线                 602    第二基底
445    保护层                 604    第二接触垫
450    焊锡层                 612、614    连接线
500    封装结构               645    保护层
502    黏着层                 650    焊锡层
【具体实施方式】
在下列叙述中，各式特定细节系用以提供本发明实施例之通盘了解。本发明将配合其较佳实施例与后附之图式详述于下，应理解者为本发明中所有之较佳实施例仅为例示之用，并非用以限制本发明。熟知该项技术者亦应理解，本发明之实施不须一或多特定细节，或其它特定方法、组件或材料等。
根据本发明之一观点，本发明提供一种半导体装置之水平(side-by-side)结构，如第二、三、四图所示。
图2系为根据本发明之一实施例之半导体装置封装200之结构之上视示意图。封装200包含第一基底202具有第一晶粒220包含第一连接垫216，及第二晶粒222包含第二连接垫218。黏着层208系分别形成以环绕于第一晶粒220与第二晶粒222之边缘。重布线(RDL)226系分别形成以电性连接于第一接触垫210与第一连接垫216之间、第一接触垫210与第二连接垫218之间以及第一连接垫216与第二连接垫218之间。
参考图3，系为根据本发明之一实施例之半导体装置封装200结构之剖面示意图。在图3中，第一基底202具有第一晶粒置入穿孔(first die receiving through hole)203形成于其中，用以容纳第一晶粒220与第二晶粒222。穿孔203形成于第一基底202由上表面穿透至下表面。第一晶粒置入穿孔203，穿孔203系预先形成于第一基底202之内。黏着层208系形成于第一与第二晶粒220与222边缘间及穿孔203侧壁之间隙间。第一接触垫210(有机基底)系形成于第一基底202之上表面。
再者，介电层230形成于第一晶粒220、第二晶粒222及第一基底202之上，以暴露第一连接垫216、第二连接垫218与第一接触垫210之表面。重布线(RDL)226系形成于第一连接垫216与第二连接垫218之间、第一接触垫210与第一连接垫216之间以及第一接触垫210与第二连接垫218之间，以彼此互相电性连接(第一接触垫210与重布线(RDL)226可同时形成)。保护层232系形成于第一与第二晶粒220与222、介电层230及重布层(RDL)226，以暴露第一接触垫210之表面。值得注意的是，在形成最终黏着层后，重布层(RDL)226系隐藏于其后。
金属或导电层206系选择性涂布于第一晶粒置入穿孔203侧壁上，换言之，金属层206系形成于第一与第二晶粒220与222之间，且被黏着层208与第一基底202所环绕。因此，本发明可利用特殊黏着材料，特别是橡胶型黏着材料，以增进晶粒边缘与第一基底202之晶粒置入穿孔203侧壁间之黏着强度及应力吸收能力。
第一晶粒220与第二晶粒222系分别配置于第一基底202之第一晶粒置入穿孔203。如熟知该项技术者所熟知，第一连接垫216系形成于第一晶粒220之上表面，及第二连接垫218系形成于第二晶粒222之上表面。
保护层232系用以于进阶封装制程期间避免封装受到外力伤害，因此于最终封装制程后由最终黏着材料所覆盖，以作为保护层232。
在一实施例中，第一基底202之材料包含环氧树脂型FR5、FR4或BT(Bismaleimide triazine epoxy)。第一基底202之材料亦包含金属、合金、玻璃、陶瓷或印刷电路板(PCB)。上述合金更包含Alloy 42(42％镍-58％铁)或Kovar(29％镍-17％钴-54％铁)。再者，合金金属较佳的系由Alloy 42所构成，为一镍铁合金，其热膨胀系数适用于小型化之电子电路，且其包含镍42％与铁58％。上述合金金属亦由Kovar所构成，且其包含29％镍、17％钴及54％铁。
较佳的，第一基底202之材料系为有机基底，例如具有已定义置入穿孔之环氧树脂型FR5、BT、印刷电路板(PCB)或具有预蚀刻电路之铜合金金属，并且由于第一基底202之热膨胀系数(CTE)系与印刷电路板(PCB)(母板)之热膨胀系数(CTE)相符(matching)，因此本发明可提供较佳可靠度结构。较佳的，具有玻璃转换温度点(Glass transition temperature，Tg)之有机基底系为环氧树脂型FR5或B T型基底。亦可使用铜合金金属(CTE约为16)。上述基底也包含玻璃、陶瓷、硅。黏着层208系由硅橡胶弹性材料所构成。
在一实施例中，黏着层208之材料包含硅氧烷聚合物(Siloxane polymer，SINR)、WL5000、橡胶(rubber)、环氧树脂(epoxyresin)、液态化合物(liquid compound)及聚亚酰胺(polyimide，PI)。黏着层208之材料亦包含金属材料。
在另一实施例中，图3所显示之重布层(RDL)226系为连接线(bonding wires)326以利电性连接，如图4所示。
在图4中，封装结构300包含基底302具有第一晶粒320及第二晶粒322形成于预形成之第一晶粒置入穿孔303之内。黏着层308系形成于基底302与第一及第二晶粒320及322间之间隙。金属或导电层306系选择性形成以填充基底302与黏着层308间之间隙。接触垫310系分别利用连接线326耦合至第一连接垫316与第二连接垫318。连接线326系分别耦合至金属或导电层306及第一连接垫316与第二连接垫318。接下来，保护层332系形成于第一晶粒320、第二晶粒322及连接线326之上，且暴露接触垫310之表面以利于电性连接。
图5系为根据本发明之另一实施例显示一半导体装置封装结构400之剖面示意图。值得注意的是，在此省略相似组件之说明与叙述，以避免模糊本发明。
在图5中，封装结构400包含封装结构200，如图3所示，形成于具有第二接触垫404及形成于其中之电路线的第二基底402之上。封装结构200系形成于黏着层240之上，且形成于第二基底402之上。封装400更包含连接线406耦合至第二接触垫404与第一接触垫210，以利电性连接。换言之，第一接触垫210形成且环绕于第一基底202之边缘区域可电性耦合至形成于第二基底402内之第二接触垫404。本发明更包含形成最后之保护层445以覆盖上述封装，及最后之焊锡层450系形成于第二基底402下表面之末端金属垫。
根据本发明之一观点，本发明更提供一种半导体装置之堆栈(stacking)结构，如第六与七图所示。下述之实施例更包含伪晶粒(pseudo chips)形成于第二基底上之结构内。伪晶粒用以作为本发明中之单一晶粒，由于晶粒堆栈封装结构中之晶粒尺寸差异，因而可避免连接线过长或过短之问题，伪晶粒不仅可减少封装体之厚度与foot print，亦可简化连接线制程以增加封装之良率与质量。
参考图6，系根据本发明另一实施例之半导体装置之封装结构500之剖面示意图。封装结构500包含封装结构200，如图3所示，形成于第二基底509之上且具有第二接触垫510形成于其中。再者，第二基底509具有预形成之第二晶粒置入穿孔503，用以容纳第三晶粒504且具有复数第三接触垫505形成于其中。黏着层502系形成于第三晶粒504与第二基底509之下，及黏着层508系填充于第三晶粒504与第二基底509间之间隙。金属或导电层506系形成于第二基底402与黏着层508间之间隙，作为交互连接穿孔(inter-connecting through hole)以耦合第二基底509上表面至第二基底509下表面之讯号。
在图6中，封装结构500更包含复数连接线512以耦合至第二接触垫510与第一接触垫210，及复数连接线514以耦合至第二接触垫510与第三接触垫505。最终之保护层545系形成以覆盖上述封装，并且最终之焊锡层550系形成于第二基底509下表面之末端金属垫上。值得注意的是，在此省略相似组件之说明与叙述，以避免模糊本发明。
参考图7，系为根据本发明另一实施例之半导体装置之封装结构600之剖面示意图。封装结构600包含封装结构200，如图3所示，形成于具有第三接触垫505之第三晶粒504。第三晶粒504系形成于黏着层502之上，并且第三晶粒504系形成于具有复数第二接触垫604及电路线形成于其中之第二基底602上。在图7中，封装结构600更包含复数连接线612耦合至第二接触垫604与第一接触垫210，及复数连接线614耦合至第二接触垫604与第三接触垫505。形成最后之保护层645以覆盖上述封装，及最后之焊锡层650系形成于第二基底602下表面之末端金属垫。
金属膜(或层)(未显示)可选择性溅镀(sputtered)或涂布(plated)于第一、第二与第三晶粒220、222与504，以利于解决热管理需求。
在说明书中，应可理解在此省略相似组件之说明与叙述，以避免混淆本发明。值得注意的是，上述结构之材料与排列方式并非用以限定本发明。上述结构之材料与排列方式亦可根据不同情况与要求而作变动。
根据本发明之一观点，本发明提供一种具有伪晶粒之半导体装置结构，且提供薄型(thin)封装结构。上述封装(伪晶粒)尺寸可根据多重晶粒之尺寸而作调整。再者，本发明提供一种简易封装结构，可增进可靠度与产率。并且，本发明更提供一种具有伪晶粒之新颖结构，用以作为晶粒功能且省略习知技术中之基底层，因而可缩减晶粒尺寸封装(chip scale package)结构之尺寸，以及因使用低成本材料亦可降低成本。因此，本发明所揭露之薄型晶粒尺寸封装结构可提供习知技术所无法预期之功效，并且解决习知技术之问题。上述结构可应用至晶圆或面板产业，亦可应用与润饰至其它相关产业之应用。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张之专利权利范围。其专利保护范围当视后附之申请专利范围及其等同领域而定。凡熟悉此领域之技艺者，在不脱离本专利精神或范围内，所作之更动或润饰，均属于本发明所揭示精神下所完成之等效改变或设计，且应包含在下述之申请专利范围内。

Claims (10)

1.一种半导体装置封装之结构，其特征在于：包含：
第一基底具有晶粒置入穿孔；
第一晶粒具有第一连接垫及第二晶粒具有第二连接垫，且分别配置于该晶粒置入穿孔之内；
黏着层形成于该第一晶粒与该第二晶粒间之间隙及该第一基底之该晶粒置入穿孔之侧边；以及
重布线形成以将该第一基底上之该第一连接垫分别耦合至该第一连接垫与该第二连接垫。
2.根据权利要求1所述之半导体装置封装之结构，其特征在于：更包含伪晶粒形成于该第一基底之上。
3.根据权利要求1所述之半导体装置封装之结构，其特征在于：更包含介电层形成于该重布线之上。
4.根据权利要求1所述之半导体装置封装之结构，其特征在于：更包含保护层形成于该重布线、该第一晶粒、该第二晶粒及第一基底之上，且暴露该第一连接垫之表面。
5.根据权利要求1所述之半导体装置封装之结构，其特征在于：更包含一金属或导电层形成于该第一基底之该晶粒置入穿孔中之侧壁。
6.根据权利要求1所述之半导体装置封装之结构，其特征在于：更包含第二基底具有第二接触垫与电路线形成于其中。
7.根据权利要求6所述之半导体装置封装之结构，其特征在于：其中该第二接触垫系利用复数连接线而耦合至该第一接触垫。
8.根据权利要求6所述之半导体装置封装之结构，其特征在于：更包含黏着层形成且环绕该第一基底与该第二基底。
9.一种半导体装置封装之结构，其特征在于：包含：第一基底具有第一晶粒置入穿孔；
第一晶粒具有第一连接垫及一第二晶粒具有第二连接垫，且分别配置于该第一晶粒置入穿孔之内；第一黏着层形成于该第一与第二晶粒间之间隙及该第一基底之该第一晶粒置入穿孔之侧壁；
重布线形成以将该第一基底上之接触垫分别耦合至该第一连接垫与该第二连接垫；
保护层形成于该重布线、该第一晶粒、该第二晶粒及该第一基底之上；
第二基底具有第二晶粒置入穿孔与第二接触垫，且形成于一第二黏着层之上及该第一基底之下；以及
第三晶粒具有第三连接垫配置于该第二晶粒置入穿孔之内。
10.一种半导体装置封装之结构，其特征在于：包含：
第一基底具有晶粒置入穿孔；
一第一晶粒具有第一连接垫及一第二晶粒具有第二连接垫，且分别配置于该晶粒置入穿孔之内；
第一黏着层形成于该第一与第二晶粒间之间隙及该第一基底之该第一晶粒置入穿孔之侧壁；
重布线形成以将该第一基底上之第一接触垫分别耦合至该第一连接垫与该第二连接垫；
保护层形成于该重布线、该第一晶粒、该第二晶粒及该第一基底之上；
第三晶粒具有第三连接垫配置于该第一基底之下；以及
第二基底具有第二接触垫及电路线形成于其中及该第三晶粒之下。
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