TW200832666A - Multi-chips package and method of forming the same - Google Patents

Multi-chips package and method of forming the same Download PDF

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Publication number
TW200832666A
TW200832666A TW096146338A TW96146338A TW200832666A TW 200832666 A TW200832666 A TW 200832666A TW 096146338 A TW096146338 A TW 096146338A TW 96146338 A TW96146338 A TW 96146338A TW 200832666 A TW200832666 A TW 200832666A
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TW
Taiwan
Prior art keywords
die
dielectric layer
substrate
layer
chip package
Prior art date
Application number
TW096146338A
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English (en)
Inventor
Wen-Kun Yang
Original Assignee
Advanced Chip Eng Tech Inc
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Filing date
Publication date
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW200832666A publication Critical patent/TW200832666A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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Description

200832666 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種系統級封裝（system in package;
Sip)的結構’特別是關於具有SIP之面板等級封裝（panel scale package ； PSP) 〇 【先前技術】 於半導體70件之領域中，元件之密度持續增加而元件 之尺寸卻不斷細小。為配合上述情況，如此高密度元件中 封裝或互連技術之需求亦日益增加。傳統上，覆晶封裝 (flip-chip)附著方法中焊錫凸塊陣列係形成於晶粒之表: 面’此焊錫&塊之形成可利用焊錫複合材料透過防焊層 (S〇ldei*刪k)而予以施行，以用於產生期望之焊錫凸塊 形恕。晶片封裝之功能包含功率分配、信號分配、散埶、 :呆=撐等，當半導體變為更力•傳統封編例 ===性封裝、剛性封褒技術等已無法滿足欲 產生，、較尚益度元件之較小晶片之需求。 習知技術中’通常將多晶片模組以及混合電路 附著於基板上’且元件亦密封於外殼之 声之門二夕層基板’其包含介於多個介電材料 層之間的多㈣電層，域由層疊技 其中金屬導體乃形成於個別介 b屬基板 層並使其結合在-起。^層上’接㈣疊這些介電 高：度:高效能的需求加逮了系統晶片 lp )以及系統級封裳的發展，多晶片模組 6 200832666 (Multi_Chip Module ; MCM )並已廣泛地利用於整合具有 不同功能的晶片，而多晶片封裝或者多晶片模組技術係指 將多個未封裝積體電路（裸晶；baredie)安裝於基礎材料 上的程序’多個晶粒將被封裝在完整的密封材料或者其他 ♦合物之中。MCM提供了高密度封裝，所以於電腦中主 機板上僅佔去較少的空間，且MCM亦有利於整合功能測 試。 再者’由於傳統封裝技術必須切割晶圓上的晶粒，並 個別封裝這些晶粒，因而此種製程相當耗費時間。因為晶 片封裝技術受到積體電路發展影響甚大，所以封裝技術要 f的尺寸係等同於電子元件一般。基於上述理由，今日封 衣技術的發展便偏向於球閘陣列封裝（BGA)、覆晶球閘 ^列封裝（FC-BGA)、晶片級封裝（csp)以及晶圓級封 袭（WLP)。晶圓級封裝的意義為於晶圓上進行完整封裝 以及所有連接，並於切割為晶片前進行其他處理程序。一 鲁般而:在所有組合程序或封裝程序完成之後，將自具有 數個半導體晶粒的晶圓分出個別的半導體封裝。此種晶圓 級封裝具有極小的尺寸以及非常好的電性。 二、LP為種先進之封裝技術，其中晶粒之製造與測 式^於曰曰圓上進行，且接著藉切割而單一化以用於在表面 '著生產線中組裝。由於晶圓級封裝技術將整個晶圓 ^個體來運用，而非著眼於單一的晶片與晶粒，所以在 進行切割程序前，封裝與測試均已完成，並且 當高階之技術，因此線接合'晶粒料及底料充之^ 7 200832666 =以忽略。仙用晶圓級封裝技術，可減少成本及製造 :曰且日日圓級封裝之結果結構可相當於晶粒，故此 滿足電子裝置之微型化需求。
雖晶圓級封裝技術具有上述優點，然而仍存在一些 影響晶圓級封裝技術之接受度之問題。例如，雖然㈣ 技術可降低IC與互相連接之基板間cte的不相配， 然隨著元件尺寸的縮減，WLP之基板材質間cte的不同 將成為結構機械穩定度的另一個關鍵因素。再者，在晶圓 級的晶片級封裝中，乃利用涉及重分佈層的傳統重分佈程 序，將形成在半導體晶粒上的數個結合墊重新分佈在區域 陣歹]類型中的數個金屬墊中。錫球將直接溶接在此金屬墊 上’此金屬墊乃藉由重分佈程序而形成為區域陣列類型。 一般而言，所有的堆疊重分佈層均形成在晶粒上的組 合層上，因此增加了封裝的厚度，此有違縮減晶片尺寸之 需求。 據此，本發明乃提供WLP之多晶片封裝。 【發明内容】 本發明之目的在於提供具有高度可靠性以及低成本優 勢的SIP，本發明之多晶片封裝結構包含具有於其上表面 内的晶粒接收凹處（die receiving cavity )以及穿過其中的 第一穿孔結構（first through hole structure )的基板 (structure)，而具有端點墊（terminal pad)的電路則形 成於第一穿孔結構之下。第一晶粒（die )位於晶粒接收凹 處内，第一介電層（dielectric layer )則形成於第一晶粒以 200832666 及基板上。第一重分佈層形成於 八 -穿孔結構耦合至第—晶粒與該上’並經由第 形成於第一重分佈層上的開口 ：,’弟二介電層具有 雷层I· on ^ 弟—日日粒則附著於第-八 穿二槿 二晶粒之圍繞材料具有對準此開口之 Γ;!佈=電層形成於第二晶粒以及圍繞材料 弟二重：佈層形成於第三介電層上，並經由第二穿孔 二重分佈層上。第一與第二：墊：護層則形成於第 •扇出’並透過第一盘第_穿:佈广：自弟-與第二晶粒 訊。 、弟一牙孔結構向下與端電點進行通 另外，本發明所提供之另一多晶片封裝結構包含基 此基板具有於其上表面内以接收至少兩個晶粒的至少 兩個晶粒接收凹處，以及穿過其中的穿孔結構，而具 點墊的電路則形成於穿孔結構下。第一晶粒以及一第二曰 第二晶粒以及基板上。重分佈層形成於第一介 _位於至少兩個晶粒接收凹處内，第一介電層形成Ζ -弟一晶粒 Μ - 、 電層上，並耦合至第一晶粒、第二晶粒以及端點塾，而第 二介電層則形成於重分佈層上，以作為保護層。 第一介電層包含彈性材料，或者此第一介電層可包含 夕祕月日 η 電基材（silic〇ne dieiectric base(j materiai)、苯 裱 丁烯（Benzocyci〇butene ; BCB )或聚醯亞胺 (Polyimide，Pi )，其中矽氧烷基材包含矽氧烷聚合物 (sil〇xane polymers; SINR)、道康寧（D〇w c〇rning) WL5000系列或者兩者之組合。第一介電層亦可包含感光 9 200832666 (可曝光成像）層。 基板之材質可包含環氧樹脂類型的FR5、FR4、雙馬 來酰亞胺二嗓樹脂（Bismaleimide triazine ; BT )、印刷電 路板（PCB )、合金、玻璃、矽樹脂、陶瓷或金屬。或者， 基板之材質可包含Alloy42( 42%的鎳、58%的鐵）或Kovar (29%的鎳、17%的钻、54%的鐵）。 【實施方式】 以下將藉由較佳實施例配合圖式詳細地說明本發明， ⑩然應可理解者為這些較佳實施例僅為例示之用，除了文中 提及之實施例外，本發明更可廣泛地以其他方式實施，並 且除了依各請求項所界定者外，本發明之範圍不受其他内 容所限制。 本發明揭露之WLP結構，係利用具有預設電路之基 板，並且此基板具有形成於其上的穿孔（thr〇ugh h〇les) 以及基板内的凹處（Cavity )。感光物質則塗布於晶粒以 0及預先成型的基板上，此感光物質最好由彈性材料構成。 第一圖呈現根據本發明較佳實施例用於Slp之面板級 封裝的截面圖，其中SIP之結構包含基板2，具有形成於 其上的晶粒接收凹處（die receiving cavity ) 4，以接受晶 粒18並有數個穿孔6自基板2的上表面貫穿至其下表 面，而導電物將被填入穿孔6以提供電子流通。端點墊8 則位於基板的下表面，並以導電物連接至穿孔6，傳導電 路線（conductive circuit trace) 10形成於基板2的下表面 上而例如防焊環氧樹脂（solder mask epoxy )的保護層 10 200832666 12則形成於傳導電路線丨〇上以保蠖之。 晶粒18係置於基板2上晶 著（晶粒附著）物14固定，而接館執處4之内’並以黏 於晶粒18上1光Η介% f觸墊（料）2G則形成 这尤層或；I電層22覆蓋晶粒18， 日日粒18與凹處4邊牆間的空隙。數 / 、 曝光顯影程序而形成於介電_ 幵過微影製程或 禍〜a "电潛22内，此數個開口個別透 i的、=為導線24,則藉由將形成於於介電層22 的二疋朽移除以形成於介電層22上，仙⑶將透過 塾20與晶粒18保持電性連接只 介雷犀79 ^0曰 于电注運接。RDL的一部分將填入 =22中的開口，因而形成透過穿孔6上的金屬以及焊 的塾金屬之連接。介電層％覆蓋rdl24，並形成 ::粒18以及基板2之上，並填入晶粒18周圍的空間。 t開口形成於介電層26内’並與舰24對齊排列以暴 路RD 24之部分。 第—θ曰片3〇具有第二接觸墊36，並透過黏著物28附 著於^電f %之上，並於第二晶片2〇周圍塗布介電材料 2第一牙孔34係形成於介電材料32之内，介電層％ 具有形成於第二晶片（晶粒）3〇上的開口，此開口係以習 知之方式形成，且與第u3G的接觸塾以及第二穿孔 34對齊，亚將導電物填入第二穿孔μ以及介電層％之開 中第—RDL 38形成於介電層5〇上，並填入介電層之 開 保羞層40則形成於第二晶片30以及第二RDL 38 之上，且遮蓋物42乃選擇地形成於保護層4〇之上。遮蓋 11 200832666 I:等=可為環氧樹脂、橡膠、樹脂、金屬、塑膠、 的印字品質)子為二質，以提供電屏蔽、散熱以及較佳 擒1 6沾处m…屯凸塊16耦合至端點墊8，具有導電凸 φ 、、、、°冓稱為BGA類型SIP或者SIP_BGA。若略去 :凸塊’則為…類型SIP或者，請 號部=1::部分與第一圖相似’因此將省略相同參照編 · ' 者為’第—晶片18可透過第-穿孔6、第二穿 1、弟一 RDL 24、第二RDL 38而與第二晶片30進行 U，此為選擇性之配置，並且可發現到第一晶片Η係 ^成於凹處4内’降低了 SIp之高度。兩rdl結構均為扇 型（Fan_〇Ut)而增加了球間距（ballpitch)，遂增強了 可靠度與散熱能力。 土板2之材貝最好為有機基板，例如環氧樹脂類型的 肥、雙馬來酰亞胺三嗪樹脂（別酿丨—⑷; 修BT)、具有已定義凹處# pCB或者具有預先㈣電路的 Alloy 42。有機基板中具有較高的轉移溫度（的旧出⑽ temperature ; Tg )者為環氧樹脂類型的FR5或者Βτ類型 的基板·，Alloy 42係由42%的鎳（Ni)以及58%的鐵（Fe) 組成，且亦可採用Kovar，其係由29%的鎳、17〇/〇的鈷 (Co)以及54%的鐵組成，此外亦可採用玻璃、陶瓷、 矽，因為其熱膨脹係數（CTE )較低。 在本發明的某一實施例中，介電層22最好為彈性介 電材質，其係由包含有矽氧烷聚合物（Siloxanepolymers; 12 200832666 SINR )、道康寧（Dow Corning ) WL5000系列、以及兩者 之組合的石夕樹脂介電基材所製成。在另一實施例中，介電 層係由包含聚亞酸胺（PI )或石夕樹脂之材料所組成。其最 好為感光層以簡化製程。 在本發明之某一實施例中，彈性介電層22為一種具 有大於100 (ppm/°c )之熱膨脹係數、約40%之伸長率（最 好30%至50%)以及介於塑膠及橡膠之間之硬度的材料， 彈性介電層18之厚度則取決於在溫度循環測試期間累積 _於重分佈層/介電層介面中的應力。 、 在本發明之一實施例中，RDL 24之材料包含鈦/銅/金 合金或鈦/銅/鎳/金合金，其厚度係於2微米至15微米間。 鈦/銅合金係藉由濺鍍技術形成作為種子金屬層（化以 metal layers)，且銅/金或銅/鎳/金合金係藉由電鍍技術形 成。利用電鍍程序形成重分佈層可使重分佈層具有足夠之 厚度以抵抗溫度循環期間之熱膨脹係數不匹配。金屬墊 # 20可為鋁或銅或其結合。若擴散型晶圓級封裝 結構利用石夕氧燒聚合物（SINR)作為彈性介電層且利用銅 作為重分佈層之金屬，累積於重分佈層/介電層介面内之 應力將會降低。 “基板2可為圓形，例如晶圓型，其半徑可為2〇〇毫 ，、300耄米或以上。基板亦可為矩形，例如面板型。第 三圖呈現預先成型之基板2的截面，由圖式可知，基板2 係形成有凹處4以及内建電路1〇，且穿孔結構6中填有金 屬。在第三圖上部，第一晶片與第二晶片並未配置為堆疊 13 200832666 結構，第二晶片3〇係位於第一晶片18旁，且兩晶片乃透 過垂直通訊線24a互相通訊，而非透過穿孔結構。如圖所 不，此結構包含兩個凹處以個別接收第一與第二晶片，其 中並個別呈現BGA與LGA兩種類型。 另外，第四圖中的實施例結合了第一圖與第三圖，至 少有四個晶片配置於SIP中，上層的晶片可透過皿％ 進行通訊，而下層的晶片則可透過RDL24a耦合，並且上 層的晶片至少可透過穿孔結構34、3如互相通訊。 如第-圖至第四圖所示’ RDL24、38自晶粒扇出， 並向下與封裝穿孔結構下的端點塾8進行通訊，盘習知之 MCM技術不同者為其堆疊結構係於晶粒上，因而增加了 封裝的厚度，違反了降低晶粒封I厚度的原則。Μ相反 地，本發明之端點墊係位於基板上與晶粒墊相對之側，通 =路經由穿孔穿過基板2’並將訊號引導至端點塾8。 ，此1顯著地降低晶粒封裝厚度，使本發明之封裝較習 者薄。再者，基板於封裝前便已預先備妥，凹處4 U:R:亦已預先設置，所以可增加產量。本發明在 島路於RDL上沒有堆疊組合層的扇出WLp。 切八ίΐΓ完ΐ圓並背面研磨至期望的厚度後，便將晶圓 凹;為;曰立。基板上預先形成有内建之電路以及至少一個 凹處，基板之材質最好為轉化严
印刷電路板。基板可具二二匕)較…R5/BT 片，並且凹處之深度較晶粒 处以接收不同的晶 曰輪糾丄 ；度夕20至30微米以容納 B曰粒附者材料。本發明之程序包含提供校準工具(薄板)， 200832666 其具有形成其上之校準圖型。接著，將圖樣黏著劑印刷於 工具上（用以黏附晶粒之表面），然後利用具有覆晶功能 之取放精您校準系統以基已知為完好的晶粒以期望之間具 重新分佈於工具上，圖樣黏著劑將晶片黏著於工具上。隨 後，將晶粒附著材料印刷於晶粒背側，並利用板結合器 (panel bonder)將基板固定於晶粒背侧，基板的上表面除 了凹處外亦黏貼於圖樣黏著劑上，接著施行真空處理 (vacuum curing)，接著將工具自面板級晶圓分離。 另外，可利用具有精密校準能力的晶粒結合器，且晶 粒附著材料可配置於基板的凹處上，將晶粒放至於基板的 凹處上，並將晶粒附著材料加熱以確保晶粒固著於基板 上0
、一皆曰曰粒重新分佈於基板上，便施行潔淨程序，以 /”、、式α洗及/或乾式清洗來清潔晶粒表面。其後之步驟為 將介電材料塗佈於面板之表面上，並接著施行光微影钱刻 程序以開啟接觸以及ls接合墊。之後，執行㈣子清洗 (Plasma elean)步驟以清洗通孔及㈣合塾之表面，並賤 鑛欽/銅作為種子金屬層，且接著塗佈光阻（PR)於介電 層及種子金屬層上，以用於形成重分佈金屬層（心广之 圖形。接著進行電鍍程序以形成銅/金或銅/鎳/全 佈層金屬’然後去除光阻（PR)並進行金屬 :1 重分佈層金料線。隨後為塗佈或印刷頂部介 /或者開啟接觸接觸墊，以完成第一層面板程序。 接著並以後續的程序完成第二層晶粒，且較薄的晶粒 15 200832666 (大約50微米）最好能夠獲得較佳的程序效能與可靠产。 此程序包含將晶粒附著材料28印刷於第二層晶粒3〇=背 側上，第一個處理過的面板將與第二層晶粒與工具結合， 然後於處理後將工具與面板分離，接著清潔第二層晶粒的 表面，並塗佈或印刷介電材料，以填滿晶粒週邊以及上方 沒有晶粒的區域。使介電層50覆蓋晶粒3〇，並藉由微影 製程開啟接觸墊。隨後處理介電層並清潔第二層晶粒= 的I/O墊以及牙孔。執行濺鍍鈦/銅步驟以形成種子金屬 層，並塗佈光阻（PR)以形成RDL圖樣，且使用電路步 驟來形成銅/金於RDL圖樣内，然後除去光阻並進行金屬 濕蝕刻以形成重分佈層金屬導線38，形成上方介電層仞 以保護此RDL導線38，並形成覆蓋層42以供上方印字之 用。 於設置球或印刷焊錫糊劑後，施行熱迴融程序以迴焊 基板側（用於BGA類型）。接著執行測試，藉由利用垂 鲁直式探針卡（vertical probe card)施行面板晶圓級最終測 試。測試完畢之後，切割基板將封裝分成具有多晶片的個 別SIP單元，接著揀選個別封裝並將封襄置於托盤或捲帶 及捲轴上。 本發明之優點為：基板係預先備妥預形成凹處；凹處 之大小與晶粒大小每侧加50至1〇〇微米相當；藉由填充彈 性介電材料可用作為應力緩衝釋放區域，以吸收石夕晶粒與 基板（FR5/BT)間熱膨脹係數不同所造成之熱應力。由於 應用簡化之積層於晶粒表面上方，故封震生產率將會增加 16 200832666 (製造周期減少）。端點墊係形成於晶粒主動面之相反側 (預先形成）。
晶粒放置程序與現行程序相同，惟本發明無須填充核 心黏膠（樹脂、環氧樹脂混合物、矽氧烷橡膠等）。於銲 錫與主機板PCB結合時沒有CTE不匹配的問題，且晶粒 與基板FR4之間的深度僅為大約2〇至3〇微米之間（用於 容納晶粒附著材料的厚度），當晶粒附著於基板的凹處上 後，μ粒與基板的表面高低可趨於一致。僅將石夕樹脂介電 材料（silicone dielectric material ;最好為 SINR)塗佈於 晶粒主動面及基板（最好為FR4、FR5或Βτ)表面上。由 於介電層（SINR)為感光層，故只利用光遮罩程序即得以 開啟接觸通孔結構。於SINR塗佈時利用真空製程可消除 氣泡的問題。在基板與晶粒（晶片"吉合之前，晶粒附著 =料係印刷於晶粒背侧。封裝與面板級的可靠性均較以往 提昇，特別是面板級溫度循環測試，蓋因基板之cte與 PCB主機板相同，因此沒有熱機械應力施加於錫球或錫凸 塊上。本發明使成本降低並且簡化製程，而使複合封裝 (多晶粒封裝）變得更為容易。 口 衣 雖然本發明之較佳實施例以詳述於上，但本發明 二域中具有通常知識者應可理解本發明並非僅偈限於上述 的科更應包含所有未_各請求項戟義 的精神與範圍之所有調整與更替。 乃 【圖式簡單說明】 第-圖呈現根據本發明較佳實施例之堆疊扇出⑽結 17 200832666 構的截面圖。 第二圖呈現根據本發明實施例之堆疊扇出SIP結構的 截面圖。 第三圖呈現根據本發明實施例之平行扇出SIP結構的 截面圖。 第四圖呈現根據本發明實施例之堆疊扇出SIP結構的 截面圖。 【主要元件符號說明】 • 2基板 4 晶粒接收凹處（die receiving cavity ) 6 穿孑L ( through hole ) 8 端點墊（terminal pad ) 10 傳導電路線(conductive circuit trace) 12保護層 14 黏著物（adhesion material ) • 16 導電凸塊（conductive bump ) 18 晶粒（die) 20 接觸墊（contact pad ) 22 介電層（dielectric layer) 24 重分佈層（re-distribution layer) 26介電層 28黏著物 30晶片 32介電材料 18 200832666 34穿孔 36接觸墊 38重分布層 40保護層 42遮蓋物（cover ) 5 0介電層

Claims (1)

  1. 200832666 十、申請專利範圍： 1 · 一種多晶片封裝結構，包含： 一基板（structure)，具有於其上表面内的晶粒接收凹 處（die receiving cavity)以及穿過其中的第—穿孔結 構（first through hole structure )，而具有端點塾 (terminaipad)的電路則形成於該第一穿孔結構之下； 一第一晶粒（die )，位於該晶粒接收凹處内； 一第一介電層（dielectric layer)，形成於該第一晶粒 以及該基板上； 第重分佈層，形成於該第一介電層上，並經由該 第牙孔結構麵合至該第一晶粒與該端點墊； 一第二介電層，具有形成於該第一重分佈層上的開 α ; 一第二晶粒，附著於該第二介電層上； 一圍繞材料，圍繞該第二晶粒，並具有對準該開口之 第二穿孔結構； 一第三介電層，形成於該第二晶粒以及該圍繞材料 上； 二第=重分佈層，形成於該第三介電層上，並經由該 =二，孔結構耦合至該第二晶粒以及該端點墊；以及 保屢層’形成於該第二重分佈層上。 2.如^求㊆i所述之多晶片封裝結構，其更包含搞合至 該端點墊的導電凸塊（conductive bump )。 20 200832666 3. 如請求項1所述之多晶片封裝結構，其中該介電層包 含彈性介電層。 4. 如請求項1所述之多晶片封裝結構，其中該介電層包 含碎樹脂介電基材（silicone dielectric based material )、 苯環丁烯（Benzocyclobutene ; BCB )或聚醯亞胺 (Polyimide ; PI)，其中該矽氧烷基材包含矽氧烷聚合 物（siloxane polymers ; SINR)、道康寧（Dow Corning) WLSOOO系歹*J或者兩者之組合。 5. 如請求項1所述之多晶片封裝結構，其中該第一介電 層包含感光（可曝光成像層。 6. 如請求項1所述之多晶片封裝結構，其中該第一或第 二重分佈層係由包含鈦/銅/金合金或鈦/銅/鎳/金合金之 合金所構成。 7. 如請求項1所述之多晶片封裝結構，其中該第一與第 二重分佈層係自該第一與第二晶粒扇出（fanout)。 8·如請求項1所述之多晶片封裝結構，其中該第一與第 二重分佈層透過該第一與第二穿孔結構向下與該端點 墊進行通訊。 21 200832666 9·如請求項1所述之多晶片封裝結構，其中該基板之材 質包含環氧樹脂類型的FR5、FR4、雙馬來酰亞胺三嗪 樹脂（Bismaleimide triazine ; ΒΤ )、印刷電路板 (PCB )、合金、玻璃、石夕樹脂、陶曼或金屬。 1 〇·如請求項1所述之多晶片封裝結構，其中該基板之材 質包含 Alloy42 ( 42%的鎳、58%的鐵）或 Kovar ( 29% 的鎳、17%的鈷、54%的鐵）。 U·—種多晶片封裝結構，包含： 一基板，具有於其上表面内以接收至少兩個晶粒的至 少兩個晶粒接收凹處，以及穿過其中的穿孔結構，而 具有端點墊的電路則形成於該穿孔結構下； 一第一晶粒以及一第二晶粒，個別位於該至少兩個 粒接收凹處内； 一第一介電層，形成於該第一晶粒、該第二晶粒以及 該基板上； 一重分佈層，形成於該第一介電層上，耦合至該第一 日日粒、忒第二晶粒以及該端點墊·，以及 一第二介電層，形成於該重分佈層上。 其更包含耦合至 12·如請求項11所述之多晶片封裝結構 該端點墊的導電凸塊。 22 200832666 13 t:求項1所述之多晶片封裝結構， 含彈性介電 其中該介電層包 層 a::項二所述之多晶片封裳結構，其中該介電層包 氣r其1 電基材、苯環丁 _或聚醯亞胺，其中該石夕 去材包含石夕氧燒聚合物、道康寧wl5000系列或 I兩者之組合。 芦=項11所述之多晶片封I結構，其中該第一介電 曰匕3感光（可曝光成像）層。 # it項U所述之多晶片封I結構，其中該重分佈層 成i 3鈦/銅/金合金或鈦/鋼/鎳/金合金之合金所構 :求項11所述之多晶片封裝重分 係自該第-與第二晶粒扇出（fanout)。 23 1 所述之多晶片封裝結構，其中該重分佈層 牙孔結構向下與該端點墊進行通訊。 項11所述之多晶片封I結構，其中該基板之 貝包含環氧樹脂類型的阳、FR4、雙馬㈣亞胺三。秦 200832666 树脂、印刷電路板、合金、玻璃、矽樹脂、陶瓷戈金 屬。 、’ 20·=請求項11所述之多晶片封裝結構，其中該基板之材 質包含 All〇y42 ( 42%的鎳、58%的鐵）或 K〇var (29% 的鎳、17%的銘、54%的鐵）。 ❿21 ·種形成半導體元件封裝的方法，其步驟包含·· 提供基板，該基板具有晶粒接收凹處形成於其上表面 内以及形成穿過其中的穿孔結構，而具有端點塾的電 路則形成於該穿孔結構下； 利用取放精密校準系統將第一晶粒以預期之間距重新 分佈於工具上； 將黏著物附著於該第一晶粒背側； 使該基板與該晶粒背侧結合，並分開該工具； 鲁將第-介電層塗布於該第一晶粒與該基板上； 於該第一介電層上形成第一重分佈層； 於該第一重分佈層上形成該第二介電層； 將第二晶粒附著於該第二介電層上； 形成’I電材料以填入該第二晶粒周圍區域； 於該第二晶粒上形成第三介電層； 於該第三介電層上形成第二重分佈層；以及 形成第四介電層以保護該第一與第二重分佈層。 24 200832666 22·如請求項？〗 α : 斤述之形成半導體元件封裝的方$ 各該介電層包切樹脂材;方法，其中 胺’其中該彻基材包含砍 ？':或聚醯亞 WL5_系列或者兩者之組合^物、道康寧 23·如請求項21 %、+、> / 該第-介電===半導體元件封裝的方法，其中 曰感光（可曝光成像）層。 _ 2 4 ·如請求項21张、w ^ η — >成半導體元件封裝的方法，其中 鎳/金合金之合包含鈦/銅/金合金或鈦/銅/ 25=f項21所述之形成半導體元件封裝的方法，其中 土反之材貝包含環氧樹脂類型的fr5、、雙馬來 酰亞胺三嗪樹脂、印刷電路板、合金、玻璃、矽樹 脂、陶瓷或金屬。 26·如请求項21所述之形成半導體元件封裝的方法，其中 λ基板之材貝包含A11〇y42 ( 42%的鎳、％%的鐵）或 Kovar (29〇/〇的！臬、17%的鉛、54%的鐵）。 25
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8445995B2 (en) 2010-12-06 2013-05-21 Industrial Technology Research Institute Semiconductor structure with conductive plug in an oxide layer
TWI501365B (zh) * 2010-10-13 2015-09-21 Ind Tech Res Inst 封裝單元及其堆疊結構與製造方法
TWI501359B (zh) * 2009-03-13 2015-09-21 Xintec Inc 電子元件封裝體及其形成方法
TWI611523B (zh) * 2014-09-05 2018-01-11 矽品精密工業股份有限公司 半導體封裝件之製法
TWI771647B (zh) * 2014-11-05 2022-07-21 美商艾馬克科技公司 晶圓級堆疊晶片封裝及製造其之方法

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812434B2 (en) * 2007-01-03 2010-10-12 Advanced Chip Engineering Technology Inc Wafer level package with die receiving through-hole and method of the same
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
TWI460844B (zh) * 2009-04-06 2014-11-11 King Dragon Internat Inc 具有內嵌式晶片及矽導通孔晶粒之堆疊封裝結構及其製造方法
US8612809B2 (en) 2009-12-31 2013-12-17 Intel Corporation Systems, methods, and apparatuses for stacked memory
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
CN102194706B (zh) * 2010-03-02 2013-08-21 日月光半导体制造股份有限公司 封装工艺
TW201131705A (en) * 2010-03-03 2011-09-16 Advanced Chip Eng Tech Inc Conductor package structure and method of the same
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US9337116B2 (en) * 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US9543269B2 (en) * 2011-03-22 2017-01-10 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
WO2012126377A1 (en) 2011-03-22 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
US8546900B2 (en) * 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices
KR101918261B1 (ko) * 2011-11-28 2018-11-14 삼성전자주식회사 모바일 장치용 반도체 패키지
US8648473B2 (en) * 2012-03-27 2014-02-11 Infineon Technologies Ag Chip arrangement and a method for forming a chip arrangement
US9136213B2 (en) * 2012-08-02 2015-09-15 Infineon Technologies Ag Integrated system and method of making the integrated system
US9941229B2 (en) * 2013-10-31 2018-04-10 Infineon Technologies Ag Device including semiconductor chips and method for producing such device
US9527723B2 (en) 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
KR20150144416A (ko) * 2014-06-16 2015-12-28 한국전자통신연구원 적층 모듈 패키지 및 그 제조 방법
TWI566348B (zh) * 2014-09-03 2017-01-11 矽品精密工業股份有限公司 封裝結構及其製法
CN104282657A (zh) * 2014-10-28 2015-01-14 华进半导体封装先导技术研发中心有限公司 超薄多层封装体及其制作方法
CN104409424B (zh) * 2014-12-24 2017-05-24 华进半导体封装先导技术研发中心有限公司 一种基于玻璃转接板的叠层封装体及其制备方法
US9627224B2 (en) * 2015-03-30 2017-04-18 Stmicroelectronics, Inc. Semiconductor device with sloped sidewall and related methods
TWI634629B (zh) * 2015-08-20 2018-09-01 矽品精密工業股份有限公司 電子封裝件及其製法
US9831147B2 (en) 2015-11-30 2017-11-28 Infineon Technologies Austria Ag Packaged semiconductor device with internal electrical connections to outer contacts
EP3267484B1 (en) * 2016-07-04 2021-09-01 ams International AG Sensor chip stack and method of producing a sensor chip stack
US9679878B1 (en) * 2016-07-27 2017-06-13 Semiconductor Components Industries, Llc Embedded stacked die packages and related methods
KR102549402B1 (ko) 2016-08-04 2023-06-28 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR102059403B1 (ko) * 2016-10-04 2019-12-26 삼성전자주식회사 팬-아웃 반도체 패키지
US9966361B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10312194B2 (en) 2016-11-04 2019-06-04 General Electric Company Stacked electronics package and method of manufacturing thereof
US10700035B2 (en) * 2016-11-04 2020-06-30 General Electric Company Stacked electronics package and method of manufacturing thereof
US9966371B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10529671B2 (en) 2016-12-13 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10763242B2 (en) 2017-06-23 2020-09-01 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US11158595B2 (en) * 2017-07-07 2021-10-26 Texas Instruments Incorporated Embedded die package multichip module
US10497648B2 (en) * 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same
CN108364913A (zh) * 2018-04-25 2018-08-03 哈尔滨奥瑞德光电技术有限公司 一种用于碳化硅功率器件的无引线封装结构和制备方法
CN109599389A (zh) * 2018-12-19 2019-04-09 成都瑞迪威科技有限公司 一种一体化集成电路封装结构
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
US11088100B2 (en) 2019-02-21 2021-08-10 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
CN113728383B (zh) 2019-02-22 2023-05-30 美光科技公司 存储器装置接口及方法
US11798865B2 (en) 2019-03-04 2023-10-24 Intel Corporation Nested architectures for enhanced heterogeneous integration
CN110035625B (zh) * 2019-03-07 2021-07-06 武汉迈斯卡德微电子科技有限公司 一种讯号量测介质软板的制作方法
KR102586890B1 (ko) * 2019-04-03 2023-10-06 삼성전기주식회사 반도체 패키지
US10903169B2 (en) * 2019-04-30 2021-01-26 Advanced Semiconductor Engineering, Inc. Conductive structure and wiring structure including the same
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
WO2021138329A1 (en) 2019-12-30 2021-07-08 Micron Technology, Inc. Memory device interface and method
KR20220114027A (ko) 2019-12-31 2022-08-17 마이크론 테크놀로지, 인크. 메모리 모듈 다중 포트 버퍼 기술
CN113125007B (zh) * 2019-12-31 2023-04-07 科大国盾量子技术股份有限公司 一种正弦门控探测器雪崩信号处理系统及处理方法
US11101840B1 (en) 2020-02-05 2021-08-24 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module
US11183765B2 (en) 2020-02-05 2021-11-23 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module
CN111312697B (zh) * 2020-02-28 2022-02-22 西安微电子技术研究所 一种三维堆叠集成结构及其多芯片集成结构和制备方法
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11605571B2 (en) * 2020-05-29 2023-03-14 Qualcomm Incorporated Package comprising a substrate, an integrated device, and an encapsulation layer with undercut
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
CN112349693B (zh) * 2020-09-28 2022-06-28 中国电子科技集团公司第二十九研究所 一种采用bga接口的宽带射频系统级封装结构
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
CN112968012B (zh) * 2021-02-01 2022-09-09 长江存储科技有限责任公司 扇出型芯片堆叠封装结构及其制造方法
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
CN113707630A (zh) * 2021-08-26 2021-11-26 矽磐微电子(重庆)有限公司 Mcm封装结构及其制作方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI501359B (zh) * 2009-03-13 2015-09-21 Xintec Inc 電子元件封裝體及其形成方法
TWI501365B (zh) * 2010-10-13 2015-09-21 Ind Tech Res Inst 封裝單元及其堆疊結構與製造方法
US8445995B2 (en) 2010-12-06 2013-05-21 Industrial Technology Research Institute Semiconductor structure with conductive plug in an oxide layer
TWI611523B (zh) * 2014-09-05 2018-01-11 矽品精密工業股份有限公司 半導體封裝件之製法
TWI771647B (zh) * 2014-11-05 2022-07-21 美商艾馬克科技公司 晶圓級堆疊晶片封裝及製造其之方法

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US20080136002A1 (en) 2008-06-12

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