201011877 九、發明說明： 【發明所屬之技術領域】 本發明係關於晶圓級封裝（WLP，wafer level package)，更特別地係有關於在晶圓級封裝中形成金屬線 (metal line)及球底金屬（UBM，under ball metal)之方法以改 善焊錫球（solder ball)之勢力（shear force)與減少製造周期 之時間。 【先前技術】 ® 在現今半導體元件的領域中，其元件的密度持續地增 加而體積卻又不斷縮減。因此，業界對於如此高密度元件 的封裝或互連（interconnecting)技術要求亦相對增加’以因 應上述之情勢。在傳統的覆晶接合法（flip-chip attachment) 中，封裝用之焊錫凸塊（solder bumps)陣列係形成於晶粒 (die)之表面上。焊錫凸塊之形成可經由使用一焊錫複合材 料透過一焊鍚罩幕（solder mask)以製造出期望之焊錫凸塊 ❹圖案。晶片封裝之功能包括電力分配、信號分配、熱發散、 保護及支撐等功能。當半導體元件曰趨複雜時’傳統封裝 技術，例如導線架封裝（lead frame package)、軟質基板封 裝（flex package)、硬質基板封裝（rigid package)技術，已無 法滿足含有高密度元件的小型晶片（chip)之製造需求。 此外，由於傳統封裝技術須先將晶圓分成個別的晶 粒，再分別封裝每一晶粒，因此採用上述技術之製造程序 相當耗時。由於積體電路之發展影響晶片封裝技術甚鉅， 因此當電子產品之尺寸要求變高時，封裝技術亦然。基於 201011877 上述理由，現今封裝技術之趨勢係朝向球閘陣列（BGA，ball grid array)、覆晶式球閘陣列（FC-BGA，flip-chip ball grid array)、晶片尺寸封裝（CSP，chip scale package)、以及晶 圓級封裝（WLP，wafer level package)邁進。「晶圓級封裝」 係代表整體的封裝及晶圓上所有互連結構 (interconnections)之形成以及其他製程步驛皆於晶片（晶粒） 切割（singulation)前完成。一般而言，完成所有組裝程序或 封裝程序之後，其個別的半導體封裝會自一具有複數個半 ® 導體晶粒的晶圓分離下來。故此，晶圓級封裝具有極小的 尺寸並伴隨極佳的電性性質。 晶圓級封裝（WLP)技術係為一種先進之封裝科技，藉 由此技術，其晶粒係直接在晶圓上進行製造與測試，然後 晶圓會再經過切割（dicing)使之分離以組裝在表面黏著線 (surface-mount line)上。由於WLP技術係利用整體晶圓作 為一物件，而非單一的晶片或晶粒，因此在進行劃線切割 φ (scribing)步驟前，封裝及測試皆已完成；此外，因為WLP 係為如此先進之技術以致於打線（wire bonding)、黏晶（die mount)、及底部填膠（under-fill)等步驟皆可省略。藉由使 用WLP技術，製造所需之成本及時間皆可縮減，且所得 之WLP結構可與晶粒相同；因此，此技術可滿足電子裝 置微型化之需求。 雖然晶圓級封裝（WLP)技術具備上述優點，但仍存在 一些問題影響WLP技術之接受度。舉例而言，WLP結構 之材料與母板（PCB，printed circuit board，印刷電路板）材 201011877 料間熱膨脹係數（CTE，coefficient of thermal expansion)之 差異為影響此結構機械不穩定性之另一關鍵因素。美國專 利第6,271,469號中所揭露之封裝即為其中一種會遭遇熱 膨脹係數不合問題之設計，這是因為一般的先前技術是使 用模封材料（molding compound)來封住石夕晶粒。誠如所知 者，矽材料之熱膨脹係數為2.3，但模封材料之熱膨脹係 數則約為40-80。此種配置會造成晶片在製程中移位，此 位移係導因於模封材料及介電層材料之固化溫度較高，且 m 互連接塾（inter-connecting pads)產生位移會進而導致量率 及效能之問題。由於環氧類樹脂（epoxy resin)之特性，若 其固化溫度接近或超過玻璃轉換溫度（Tg，glass transition temperature)，在製程溫度的循環（temperature cycling)下晶 片亦不易返回其原本之位置。由此可知先前之結構封裝係 無法進行大尺寸之處理，且花費較高之製造成本。 此外，先前之技術須歷經複雜之製程才得以形成金屬 _ 線。此製程需要兩次濺鍍（sputtering)製程及相對應之微影 (lithography)製程與蝕刻（etching)製程以形成晶種金屬層 (seed metal layer)。成本及周期時間係因而增加。因此，本 發明係提供一方法以形成具備良好焊錫球剪力之晶圓級封 裝及減少製造周期時間以克服前述之問題，亦具有較佳的 基板級（board level)溫度循環可靠度測試。 【發明内容】 本發明之目的係為提供一方法以於晶圓級封裝中形成 具有卓越焊錫球剪力之金屬線及球底金屬（UBM，under 201011877 ball metal)。 本發明之另一目的係在於提供負光阻（negative photoresist)作為電鍍罩幕（plating mask)以解決光阻解析度 之問題’並省去一次濺鍍（sputtering)、去光阻（stripping) 及蝕刻步驟。 此外’本發明之另一目的係為提供一方法以於晶圓級 封裝中形成金屬線及球底金屬以改善可靠度及減少製造周 期時間。 本發明係揭露一種製程用以於晶圓級封裝中形成金屬 線及球底金屬，其中包含在一晶粒之主動表面上形成一第 介電層，進行一濺鍍製程以在該第一介電層上形成晶種 金屬層；在該晶種金屬層上形成一第一負光阻圖案；進行 第一電錄製程在該晶種金屬層上形成重布層 (ydistHbution layer);在該第一介電層及該重布層上形成 第二負光阻並露出該重布層部位；進行第二電錄製程於該 ❹重布層上形成一接觸窗（contact via);在該第一介電層、該 重布層、及該接觸窗上形成第二介電層圖案並露出該接觸 窗部位；以及在該接觸窗上形成導電球。 第-與第二介電層之材料包括彈性介電層、感光層、 矽酮類（silicone based)介電層、矽氧烷（sii〇xane)聚合物 層、聚醢亞胺(PI’ polyimides)層、或矽氧樹脂層(仙_ resin layer) ° 【實施方式】 本發明更深入 之詳述將透過以下本發明中較佳 之實施 201011877 例與圖示進行描述。然而，應理解者為本發明 佳實施例僅為例示之用，並非用以限制 ‘ ::=__外，本發明亦可廣泛=: 其他實把例中，且本發明之範料顯係非受限，但以 請專利範圍」中所述為準。 申 本發明揭露了-種製程，其係利用—次魏 電鑛步驟於晶圓級封裝中形成金屬線及球底金屬。因二銅 產能可大幅提升。-基板，具有預設終端之金屬接塾於其 上形成。-晶粒係配置於此基板上並於其間填人核心材質 (core paste)，例如，以彈性核心材質填入晶粒間之空隙。 一介電材料形成於晶粒及核心材質區域上。重布層，亦稱 為導電線路（conductive trace)或金屬，線，係形成於介電層 上。接觸（contact)部位，例如球底金屬（UBM) ’係形成於 導電線路上。複數個導電球係形成於此接觸部位之上表面、。 Ο 圖一至圖七係為本發明一實施例中形成晶圓級封裝之 剖面圖。如圖一所示，第一介電層1〇1係形成於晶粒_ 之主動表面上。本發明之一實施例中，第一介電層ι〇ι以 矽酮類介電材料為主製作之彈性介電材料為佳，其中包含 了石夕氧烧聚合物（SWR ’ siloxane polymers)、道康寧（d〇w C〇rning)WL5000系列、及其間之組成。之後，利用濺鍍製 程於第一介電層101上形成一薄晶種金屬層1〇〇a，如圖一 所示。滅鍍材料可選擇銅、鋁等。接著，第一光阻層則形 成於已滅鑛之晶種金屬層l〇〇a上。在一實施例中，第一光 阻層係由一負光阻所製成。其後，第一負光阻層係定義為 201011877 第一預設光阻圖案（區域）103並藉由光微影 (photo-lUhography)製程使晶種金屬層100a露出，如圖二 所示。第一預設光阻圖案103係於顯影之後形成，其區域 係於光照後顯開。而未曝露於光照之光阻區域1〇4則於顯 影後移除。第一電鍍製程係形成一厚金屬層以作為重布層 104且覆蓋於晶種金屬層i〇〇a之上，此重布層亦稱為導電 線路（conductive trace)或金屬線，位於第一介電層1〇1上， ❹如圖三所示。第一負光阻圖案103可移除或保留至下一製 程。重布層104透過晶粒墊與晶粒保持電性連接。 然後，第二光阻層係形成於第一介電層1〇1與重布層 102之上。在一實施例中，第二光阻層係由一負光阻製成。 同樣地，第二負光阻層係定義為第二預設光阻圖案（區 域）105以藉由光微影製程曝出重布層1〇2，如圖四所示。 由於下層負光阻圖案103之故，其未曝光之光阻區域 的均勻性較已曝光之光阻區域105為佳。在此實施例中， ®由於已曝光之光阻區域1〇5具有較大之階高（step height)， 故亦產生較窄之製程條件（process wind〇w)與較小之焦深 (DOF，depth of f〇cus)。亦因此，發明中最好能採用負光 阻，因為其顯影後並不會有光阻解析度之問題。另者，未 曝光光阻區域106之焦深較已曝光之光阻區域1〇5 佳。因此，使用第二負光阻層作為罩幕（mask)優於正光阻 層且較合適。第二光阻圖案105係形成於顯影之後，此區 域係曝露於光照。未曝光之光阻區域1〇4由於未受光照係 於顯影後移除。其後，利用第二電錢製程於重布層1〇4形 201011877 成接觸窗（contact via)l〇7，如圖五所示。接著，以光阻剝 離劑（photoresist stripper)移除第二負光阻層。在此步驟 中，前述剩餘之第一負光阻圖案及位於第一負光阻下方之 部分晶種金屬層100a亦於此期間移除。 第二介電層係形成於第一介電層1〇1之上。其後，第 二介電層圖案108係形成於第一介電層1〇1、重布層1〇4 與接觸窗107上並透過光微影製程及蝕刻製程使接觸窗 ❹1〇7露出，如圖六所示。根據光微影製程，光阻層上穿孔 圖案之臨界尺寸（CD，critical dimensi〇n)係於顯影後得 到。第二介電層圖案108之開放區域109係於蝕刻後得到。 在一例中，全部或部分之第二介電層1〇8係蓋住接觸窗 1〇7。本發明之一實施例中，第二介電層1〇8以矽酮類介電 材料為主製作之彈性介電材料為佳，其中包含了矽氧烷聚 合物（SINR，sii〇xane p〇lymers)、道康寧⑴⑽ C〇niing)WL5_纟列、及其間之組成。第二彈性介電層 ❿刚之厚度端視重布層/介電層介面於溫度循環測試期間所 累積之應力決定。之後’導電球110係形成於接觸窗 上以提供電性接連，如圖七所示。 如圖七所示，部分的第二介電層應會覆蓋在接觸窗 107上’亦因此焊錫球11G之底部係連接至第二介電 108。本發明與先前技術不同之處在於其巾所有導電球110 係連接至金屬相此料球可輕易舉I本發明之封 先前技術具有較佳之焊錫球剪力或應力。本發明係揭露一 具備良好焊錫球剪力應力及熱膨脹係數相合度佳之晶圓級 201011877 封裝。 圖八為根據本發明之晶圓級封裝構造剖面圖。上述圖 七所說明之構造係形成於基板丨13上’且核心材質丨12圍 繞著晶粒100，該晶粒1〇〇上有晶粒墊u丨形成，例如一 彈性核心材質填入晶粒100間之空隙。晶圓級封裝之構造 係包括一具備終端接觸傳導墊之基板U3。核心材質U2 係以真空印刷方式或塗布於晶粒100下表面之下，從而將 ❹晶粒10〇密封。一黏著材料（adhesive material)係塗布於基 板113上以增進晶粒1 〇〇與基板丨丨3之間的黏著力。本發 明之一實施例中，彈性介電層係為一種熱膨脹係數大於 100(百萬分之一 /每攝氏溫度，ppm/ )之材料，伸長率 (elongation rate)約為40%(以30-50%為佳），且此種材料之 硬度係介於塑膠與橡膠之間。核心材質112係作為一緩衝 區域以於溫度循環時吸收晶粒1〇〇與基板113間之熱機械 應力，此應力係由介電層1〇8之彈性性質所造成。此前述 ❹之構造係構成球閘陣列（BGA)式封裝。 基板113之材質以有機基板為佳，如環氧類樹脂類的 環氧樹脂玻璃（FR5)、雙馬來醯亞胺_三氮雜苯樹脂（BT， Bismaleimide triazine)、或具有已定義穿孔之印刷電路板 (PCB，printed circuit board)、或是有預蝕刻電路 (pre-etching)之銅金屬。其熱膨脹係數與其母板（pCB)相同 為較佳。具有而玻璃轉換溫度之有機基板以環氧類樹脂 FR5或BT基板為較佳。銅金屬（熱膨脹係數約為16)亦可 使用。玻璃、陶瓷、矽皆可用作基板之材料。彈性核心材 12 201011877 質係由矽酮橡膠（silicone rubber)與彈性樹脂材料所構成。 其基板可為圓形，如晶圓型態，其直徑可為2〇〇公厘 (mm)、300公厘或更長。此基板亦可呈長矩形，如面板形 式（panel) ° 本發明之一實施例中，介電層1〇4係以矽嗣類介電材 料為主製作之彈性介電材料為佳，其中包含了矽氧烷聚合 物（SINR，siloxanep〇lymers)、道康寧（d〇w C〇rning)WL5000系列、及其間之組成。另一實施例中介 電層係由包含聚醯亞胺（pj，p〇lyimides)或矽氧樹脂 (silicone resin)之材料所製成。此材料以感光層為佳以簡化 製程。 本發明之-實施例中，彈性介電層係為一種熱膨服係 數大於1〇〇(百萬分之一/每攝氏溫度，ppmrc)之材料，伸 長率（elongation rate)約為4〇%(以3〇·5〇%為較佳），且此種 材料之硬度係介於塑膠與橡膠之間。 晶粒（熱膨脹係數約為2.3)係包於封裝内。環氧樹脂 玻璃（FR5)或雙馬來酿亞胺_三氮雜苯樹脂（Βτ)為有機環氧 類樹脂（熱膨脹係數約為16)，此等材料係用以作為基板， 其熱膨脹係數與印刷電路板或母板相同。此外，介電層108 ^ 3彈材料以吸收晶粒塾與基板或印刷電路板間之應 力。 本發月之一實施例中，重布層之材料包含鈦/銅/金合 金或欽/銅/錄/金合金；重布層之厚度係介於2至15 L ⑷之間°鈦銅合金與晶種金屬層皆以_技術形成，而銅 13 201011877 金合金或銅/鎳/金合金則以電鍍（electr〇piating)技術形 成’利用電鑛製程以形成重布層可使其具備足夠厚度與較 好之機械性質以耐受溫度循環期間熱膨脹係數不合的現 象金屬墊之材質可為鋁或銅或兩者之組合。如果晶圓級 封裝結構分別採用矽氧烷聚合物（SINR)與銅作為其彈性介 電層與重布f，則根據應力分析（未表示），’累積於重布層/ 介電層介面之應力將會減少。 ❹ 因此，本發明之步驟包括提供一晶粒重布（對準）工 具，其上有對準圖案（alignment pattern)形成然後已具 有圖案之黏膠係印刷於此工具上（用以與晶粒面與基板面 黏合）’接著，利用具備覆晶（flip chip)功能之取置精細對 準系統（pick and place fine alignment system)以所欲之節距 將目標晶粒在此工具上進行重布。圖案黏膠係將晶片（主動 表面侧）黏合於此工具之上。隨後，基板會黏結於此工具（以 圖案黏膠黏合）上，之後再將彈性核心材質印刷在晶粒間的 ❹二間（空隙）中。最好能使核心材質之表面與基板保持在同 水平南度。接著，固化步驟被施行來固化核心材質並透 過黏著材料黏結載體（玻璃或銅箔積層板CCL)0面板接合 機（panel bonder)係用以將底座接合至基板上及晶粒後 側。待真空接合後，再將上述工具與面板晶圓分離。 當晶粒於基板（面板底座）上完成重布後，即進行一淨 化程序’其係藉由濕洗及/或乾洗方法清理晶粒表面。下一 步驟係將第一介電層塗布於晶粒表面。其後，濺鍍鈦/銅合 金以作為晶種金屬層，接著負光阻劑係塗布於介電層與晶 14 201011877 種金屬層上以形成重布金屬層之圖案。之後，施以電鍍形 成銅金合金或銅/鎳/金合金以作為重布層金屬，隨後於重 布層上形成接觸窗（contact via)，接著去除光阻。下—步驟 係塗布或印上頂端介電層並選擇性吃開接觸窗區域或吃開 切割線（scribe line)。 其後，於接觸窗上印出焊錫球之配置或焊錫膏 paste)’並在焊錫球側進行熱迴銲（heat refi〇w)步驟（球閘 ⑩車列式封裝），最後執行測試。面板晶圓級之最後測試係利 用垂直或環氧類樹脂探測卡（pr〇be card)以接觸其接觸金 屬窗（contact metal via)來實現。測試後，將面板固定在藍 膠（blue tape)框架上，該基板會自其下表面位置進行切割 而分離成個別單位。 本發明之優點包含： 上述形成面板式晶圓之製程簡單且易於控制面板表面 之粗糙度。其面板厚度易於控制且可排除製程中晶粒位移 ❿ 門靖射出成型工具（injection mold tool)係可省略且亦 無需化學機械拋光步驟（CMP，Chemical Mechanical olishing)。晶圓級封裝製程易於處理面板型晶圓。 、封裝產能可藉由採用此一次濺鍍與兩道金屬電鍍製程 而曰加（製造周期時間減少）。負光阻的採用可解決因前一 二p層之光阻形狀配置（t〇p〇1〇gy)所帶來之光阻解析度問 ，並可省去一道濺鍍步驟、一道去光阻步驟、以及一道 】V驟。本發明之封裝結構係優於先前技術而具有較佳 焊錫球剪力或應力以加強封裝之強度。 15 201011877 在本發明中，其封裝級與基板級之可靠度亦較以往為 佳，特別是對於基板級溫度循環測試，這是因為基板與印 刷電路母板（PCB)之熱膨脹係數（CTE)相同所致，因此製程 中焊錫凸塊（s〇lder bumps)/焊錫球上不會受到任何熱機械 應力，先前於溫度循環期間進行之失效模式基板測試（即焊 錫球碎裂）已不明顯。其成本低廉且製程簡易。 對熟悉此領域技藝者，本發明雖以較佳實施例闡明如 ❹上然其並非用以限定本發明之精神。在不脫離本發明之 精神與範圍内所作之修改與類似的配置，均應包含在下述 之申請專利範圍内，此範圍應覆蓋所有類似修改與類似結 構，且應做最寬廣的詮釋。 【圖式簡單說明】 圖一至圖七係以剖面圖說明一程序以根據本發 晶圓級封裝。 v 圖八係根據本發明以剖面圖來說明一晶圓級封襞之結 ❹構。 、”。 【主要元件符號說明】 1 〇 0晶粒 100a晶種金屬層 101第一介電層 102重布層 103第—負光阻圖案 104重布層 105第二光阻圖案 0 0201011877 106未曝光之光阻區域 107接觸窗 108第二介電層圖案 109開放區域 110導電球 111晶粒塾 112核心材質 113基板201011877 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer level package (WLP), and more particularly to forming a metal line and a ball in a wafer level package. The method of underlying metal (UBM) improves the shear force of the solder ball and reduces the manufacturing cycle time. [Prior Art] ® In the field of semiconductor components today, the density of components continues to increase while the volume is shrinking. Therefore, the industry's requirements for packaging or interconnection technology for such high-density components are relatively increased' in response to the above situation. In a conventional flip-chip attachment, a solder bumps array for packaging is formed on the surface of a die. Solder bumps can be formed by using a solder composite material through a solder mask to create a desired solder bump pattern. The functions of the chip package include functions such as power distribution, signal distribution, heat dissipation, protection and support. When semiconductor components are becoming more complex, 'conventional packaging technologies, such as lead frame packages, flexible package packages, and rigid package technologies, have been unable to meet small wafers containing high-density components ( Chip) manufacturing needs. In addition, the manufacturing process using the above technique is quite time consuming because conventional packaging techniques involve first dividing the wafer into individual crystal grains and then packaging each of the crystal grains separately. Since the development of the integrated circuit affects the chip packaging technology, when the size requirement of the electronic product becomes high, the packaging technology is also the same. Based on the above reasons for 201011877, the trend of today's packaging technology is toward ball grid array (BGA), flip-chip ball grid array (FC-BGA), chip size package (CSP, chip scale). Package), and wafer level package (WLP). "Wafer-level packaging" means that the overall package and the formation of all interconnects on the wafer and other process steps are completed prior to wafer (die) singulation. In general, after completing all assembly or packaging procedures, individual semiconductor packages are separated from a wafer having a plurality of half-conductor dies. Therefore, the wafer level package has a very small size and is accompanied by excellent electrical properties. Wafer-level packaging (WLP) technology is an advanced packaging technology in which the die is fabricated and tested directly on the wafer, and the wafer is then diced to separate it for assembly. On the surface-mount line. Since WLP technology uses an integral wafer as an object rather than a single wafer or die, packaging and testing are completed before the scribing step φ (scribing); in addition, because the WLP is so advanced Techniques such as wire bonding, die mount, and under-fill can be omitted. By using WLP technology, the cost and time required for manufacturing can be reduced, and the resulting WLP structure can be the same as the die; therefore, this technology can meet the demand for miniaturization of electronic devices. Although wafer level packaging (WLP) technology has these advantages, there are still some issues that affect the acceptance of WLP technology. For example, the difference between the material of the WLP structure and the coefficient of thermal expansion (CTE) of the PCB (printed circuit board) 201011877 is another key factor affecting the mechanical instability of the structure. factor. The package disclosed in U.S. Patent No. 6,271,469 is one of the designs which suffers from a problem of thermal expansion coefficient mismatch, since the conventional prior art uses a molding compound to seal the stone. As is known, the thermal expansion coefficient of the tantalum material is 2.3, but the thermal expansion coefficient of the molding material is about 40-80. This configuration causes the wafer to be displaced during the process. This displacement is caused by the higher curing temperature of the molding material and the dielectric layer material, and the displacement of the inter-connecting pads causes a dose rate. And performance issues. Due to the characteristics of epoxy resin, if the curing temperature approaches or exceeds the glass transition temperature (Tg), the wafer is not easily returned to its original position under temperature cycling. It can be seen from the prior art that the structural package is incapable of processing in a large size and costs a high manufacturing cost. In addition, the prior art required a complex process to form a metal wire. This process requires two sputtering processes and corresponding lithography processes and etching processes to form a seed metal layer. The cost and cycle time are thus increased. Accordingly, the present invention provides a method for forming a wafer level package with good solder ball shear and reducing manufacturing cycle time to overcome the aforementioned problems, as well as a better board level temperature cycle reliability test. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wire and a ball metal (UBM, under 201011877 ball metal) having excellent solder ball shear force in a wafer level package. Another object of the present invention is to provide a negative photoresist as a plating mask to solve the problem of photoresist resolution and to eliminate a sputtering, stripping, and Etching step. Further, another object of the present invention is to provide a method for forming metal lines and ball-bottom metal in a wafer level package to improve reliability and reduce manufacturing cycle time. The present invention discloses a process for forming a metal line and a ball-bottom metal in a wafer-level package, wherein a dielectric layer is formed on an active surface of a die, and a sputtering process is performed to perform a sputtering process. Forming a seed metal layer on the electric layer; forming a first negative photoresist pattern on the seed metal layer; forming a ydistHbution layer on the seed metal layer by performing a first electrical recording; Forming a second negative photoresist on the dielectric layer and the redistribution layer and exposing the portion of the redistribution layer; performing a second electrical recording process to form a contact via on the buffer layer; Forming a second dielectric layer pattern on the dielectric layer, the redistribution layer, and the contact window to expose the contact window portion; and forming a conductive ball on the contact window. The materials of the first and second dielectric layers include an elastic dielectric layer, a photosensitive layer, a silicone based dielectric layer, a sii〇xane polymer layer, and a polyimide polyimide (PI' polyimides). Layer or Oxygen Resin Layer [Embodiment] Further details of the present invention will be described by way of the following preferred embodiment of the present invention 201011877 and the drawings. However, it should be understood that the preferred embodiment of the present invention is for illustrative purposes only, and is not intended to limit ' ::= __, the present invention may also be broadly defined. Not limited, but as described in the scope of the patent. The present invention discloses a process for forming metal lines and ball-bottom metal in a wafer level package using a sub-electrode process. As the capacity of the two copper can be greatly increased. a substrate on which a metal terminal having a predetermined terminal is formed. The die is disposed on the substrate and filled with a core paste therebetween, for example, a space between the crystal grains is filled with an elastic core material. A dielectric material is formed over the die and core material regions. A redistribution layer, also known as a conductive trace or metal, is formed on the dielectric layer. A contact portion, such as a ball-bottom metal (UBM), is formed on the conductive line. A plurality of conductive balls are formed on the upper surface of the contact portion. 1 to 7 are cross-sectional views showing a wafer level package in an embodiment of the present invention. As shown in FIG. 1, the first dielectric layer 1〇1 is formed on the active surface of the die. In one embodiment of the present invention, the first dielectric layer ι〇ι is preferably an elastic dielectric material mainly composed of an anthrone-based dielectric material, and includes SWR ' siloxane polymers, Dow Corning (d〇w C〇rning) WL5000 series, and its composition. Thereafter, a thin seed metal layer 1a is formed on the first dielectric layer 101 by a sputtering process, as shown in FIG. The material to be plated can be selected from copper or aluminum. Next, the first photoresist layer is formed on the seed metal layer 10a which has been destroyed. In one embodiment, the first photoresist layer is made of a negative photoresist. Thereafter, the first negative photoresist layer is defined as 201011877 first predetermined photoresist pattern (region) 103 and the seed metal layer 100a is exposed by a photo-lUhography process, as shown in FIG. The first predetermined photoresist pattern 103 is formed after development, and its area is developed after illumination. The photoresist region 1未4 that is not exposed to light is removed after development. The first electroplating process forms a thick metal layer as the redistribution layer 104 and overlies the seed metal layer i〇〇a. The redistribution layer is also called a conductive trace or a metal line. On the dielectric layer 1〇1, ❹ is shown in Figure 3. The first negative photoresist pattern 103 can be removed or retained to the next process. The redistribution layer 104 is electrically connected to the die through the die pad. Then, a second photoresist layer is formed over the first dielectric layer 1〇1 and the redistribution layer 102. In an embodiment, the second photoresist layer is made of a negative photoresist. Similarly, the second negative photoresist layer is defined as a second predetermined photoresist pattern (region) 105 to expose the redistribution layer 1 〇 2 by photolithography, as shown in FIG. Due to the lower negative photoresist pattern 103, the uniformity of the unexposed photoresist region is better than the exposed photoresist region 105. In this embodiment, ® has a relatively narrow process height (process wind〇w) and a small depth of focus (DOF) because the exposed photoresist region 1〇5 has a large step height. , depth of f〇cus). Therefore, it is preferable to use a negative photoresist in the invention because it does not have a problem of resolution of the photoresist after development. In addition, the depth of focus of the unexposed photoresist region 106 is better than that of the exposed photoresist region. Therefore, the use of the second negative photoresist layer as a mask is superior to the positive photoresist layer and is suitable. The second photoresist pattern 105 is formed after development, and this area is exposed to light. The unexposed photoresist region 1〇4 is removed after being undeveloped by illumination. Thereafter, a second electric money process is used to form a contact via l11 in the redistribution layer 1〇4 shape 201011877, as shown in FIG. Next, the second negative photoresist layer is removed with a photoresist stripper. In this step, the remaining first negative photoresist pattern and a portion of the seed metal layer 100a under the first negative photoresist are also removed during this period. The second dielectric layer is formed over the first dielectric layer 1〇1. Thereafter, the second dielectric layer pattern 108 is formed on the first dielectric layer 1〇1, the redistribution layer 1〇4 and the contact window 107, and is exposed through the photolithography process and the etching process to expose the contact window 1❹7. As shown in Figure 6. According to the photolithography process, the critical dimension (CD, critical dimensi〇n) of the perforation pattern on the photoresist layer is obtained after development. The open region 109 of the second dielectric layer pattern 108 is obtained after etching. In one example, all or part of the second dielectric layer 1〇8 covers the contact window 1〇7. In one embodiment of the present invention, the second dielectric layer 1〇8 is preferably an elastic dielectric material mainly composed of an anthrone-based dielectric material, and includes a siloxane polymer (SINR, sii〇xane p〇). Lymers), Dow Corning (1) (10) C〇niing) WL5_ 纟 column, and the composition between them. The thickness of the second elastic dielectric layer is determined by the stress accumulated during the temperature cycling test of the redistribution layer/dielectric layer interface. Thereafter, conductive balls 110 are formed on the contact windows to provide electrical continuity, as shown in FIG. As shown in Figure 7, a portion of the second dielectric layer should be overlying the contact window 107. Thus, the bottom of the solder ball 11G is connected to the second dielectric 108. The present invention differs from the prior art in that all of the conductive balls 110 of the towel are attached to the metal phase. The ball can be easily cured. The prior art has better solder ball shear or stress. The present invention discloses a wafer level 201011877 package with good solder ball shear stress and good thermal expansion coefficient. Figure 8 is a cross-sectional view of a wafer level package structure in accordance with the present invention. The structure illustrated in FIG. 7 above is formed on the substrate '13 and the core material 丨12 surrounds the die 100, and the die 1 is formed with a die pad, for example, an elastic core material is filled into the die. 100 spaces. The wafer level package structure includes a substrate U3 having a terminal contact conductive pad. The core material U2 is vacuum printed or coated under the lower surface of the die 100 to seal the germanium die 10〇. An adhesive material is applied to the substrate 113 to promote adhesion between the die 1 and the substrate 3. In one embodiment of the invention, the elastic dielectric layer is a material having a coefficient of thermal expansion greater than 100 (parts per million per gram per degree Celsius, ppm/), and an elongation rate of about 40% (by 30- 50% is better, and the hardness of this material is between plastic and rubber. The core material 112 serves as a buffer region for absorbing thermomechanical stress between the die 1 and the substrate 113 during temperature cycling, which is caused by the elastic properties of the dielectric layer 1〇8. The aforementioned structure of the ❹ constitutes a ball gate array (BGA) package. The material of the substrate 113 is preferably an organic substrate such as an epoxy resin-based epoxy resin glass (FR5), a bismaleimide triazine (BT), or a defined perforation. Printed circuit board (PCB), or copper metal with pre-etching. The coefficient of thermal expansion is preferably the same as that of its mother board (pCB). The organic substrate having the glass transition temperature is preferably an epoxy resin FR5 or BT substrate. Copper metal (a coefficient of thermal expansion of approximately 16) can also be used. Glass, ceramics, and tantalum can be used as the material of the substrate. Elastic core material 12 201011877 The system consists of silicone rubber and elastic resin material. The substrate may be circular, such as a wafer type, and may have a diameter of 2 mm (mm), 300 mm or more. The substrate may also have a long rectangular shape, such as a panel. In one embodiment of the present invention, the dielectric layer 1〇4 is preferably an elastic dielectric material mainly made of a terpene-based dielectric material, and includes A mixture of a naphthenic polymer (SINR, siloxanep〇lymers), a dow Corning (WL) series, and a composition thereof. Another embodiment of the dielectric layer is made of a material comprising polypimide (pj, p〇lyimides) or a silicone resin. This material is preferably a photosensitive layer to simplify the process. In an embodiment of the invention, the elastic dielectric layer is a material having a thermal expansion coefficient greater than 1 〇〇 (parts per million per sen's temperature, ppmrc), and an elongation rate of about 4%. (3〇·5〇% is preferred), and the hardness of this material is between plastic and rubber. The grains (having a thermal expansion coefficient of about 2.3) are packaged in the package. Epoxy glass (FR5) or bismaleimide _triazabenzene resin (Βτ) is an organic epoxy resin (coefficient of thermal expansion is about 16). These materials are used as substrates, and their thermal expansion coefficients are The printed circuit board or motherboard is the same. In addition, the dielectric layer 108 embosses the material to absorb the stress between the die and the substrate or printed circuit board. In one embodiment of the present month, the material of the redistribution layer comprises titanium/copper/gold alloy or chin/copper/record/gold alloy; the thickness of the redistribution layer is between 2 and 15 L (4). Titanium-copper alloy Both the seed metal layer and the seed metal layer are formed by _ technology, and the copper 13 201011877 gold alloy or copper/nickel/gold alloy is formed by electroplating (electr〇piating) technology to form a redistribution layer to have a sufficient thickness. The material of the metal pad is better than the mechanical properties to withstand the thermal expansion coefficient during the temperature cycle. The material of the metal pad may be aluminum or copper or a combination of the two. If the wafer-level package structure uses sodium oxymethane polymer (SINR) and copper as its elastic dielectric layer and redistribution f, respectively, according to stress analysis (not shown), 'accumulated to the redistribution layer/dielectric layer interface The stress will be reduced. ❹ Therefore, the steps of the present invention include providing a die re-alignment (alignment) tool having an alignment pattern formed thereon and then having a patterned adhesive printed on the tool (for use with the die The surface is bonded to the substrate surface.] Next, the target die is re-distributed on the tool at a desired pitch by using a pick and place fine alignment system with a flip chip function. . The pattern adhesive adheres the wafer (active surface side) to the tool. Subsequently, the substrate is bonded to the tool (bonded with a pattern of adhesive), and then the elastic core material is printed between the two spaces (voids) between the grains. It is best to keep the surface of the core material at the same level as the substrate. Next, a curing step is performed to cure the core material and bond the carrier (glass or copper laminate CCL) through a bonding material. A panel bonder is used to bond the substrate to the substrate and to the back side of the die. After the vacuum bonding, the tool is separated from the panel wafer. After the die is finished on the substrate (panel base), a cleaning process is performed, which cleans the surface of the die by wet cleaning and/or dry cleaning. The next step is to apply a first dielectric layer to the surface of the die. Thereafter, a titanium/copper alloy is sputtered as a seed metal layer, and then a negative photoresist is applied to the dielectric layer and the metal layer of the layer 11 201011877 to form a pattern of the redistributed metal layer. Thereafter, a copper-gold alloy or a copper/nickel/gold alloy is formed by electroplating as a redistribution metal, and then a contact via is formed on the redistribution layer, followed by removal of the photoresist. Next—Steps coat or print the top dielectric layer and selectively open the contact window area or eat the scribe line. Thereafter, a solder ball arrangement or a solder paste paste was printed on the contact window and a heat reheating step (ball gate 10-column package) was performed on the solder ball side, and finally the test was performed. The final test of the panel wafer level is achieved by using a vertical or epoxy resin pr〇be card to contact its contact metal via. After the test, the panel was attached to a blue tape frame which was cut from the lower surface to separate into individual units. Advantages of the present invention include: The above-described process for forming a panel wafer is simple and easy to control the roughness of the panel surface. The thickness of the panel is easily controlled and the grain displacement in the process can be eliminated. The injection mold tool can be omitted and the chemical mechanical polishing (CMP) is not required. The wafer level packaging process is easy to handle with panel wafers. The package throughput can be increased by using this single-sputter and two-metal plating process (reduction in manufacturing cycle time). The use of negative photoresist can solve the problem of the resolution of the photoresist caused by the shape configuration of the photoresist layer of the first two p layers, and can save a sputtering step and a photoresist. Steps, and a v. The package structure of the present invention is superior to the prior art and has better solder ball shear or stress to enhance the strength of the package. 15 201011877 In the present invention, the reliability of the package level and the substrate level is also better than before, especially for the substrate level temperature cycle test, because the substrate has the same thermal expansion coefficient (CTE) as the printed circuit mother board (PCB). As a result, solder bumps/solder balls are not subjected to any thermo-mechanical stress during the process, and the failure mode substrate test (ie, solder ball chipping) previously performed during the temperature cycle is not obvious. The cost is low and the process is simple. It will be apparent to those skilled in the art that the present invention is not limited by the scope of the invention. Modifications and similar configurations made within the spirit and scope of the invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 7 illustrate a procedure in a cross-sectional view for wafer level packaging in accordance with the present invention. Figure 8 is a cross-sectional view of a wafer level sealing structure in accordance with the present invention. "" Main component symbol description] 1 〇 0 die 100a seed metal layer 101 first dielectric layer 102 redistribution layer 103 - negative photoresist pattern 104 redistribution layer 105 second photoresist pattern 0 0201011877 106 not Exposure photoresist region 107 contact window 108 second dielectric layer pattern 109 open region 110 conductive ball 111 die 塾 112 core material 113 substrate
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