200939448 六、發明說明： 【發明所屬之技術領域】 係有關於半導體元件料結構，料而言係有 關於八“晶粒之半導體元件封裝結構及其方法，本結構 可減小封裝尺寸及改善產量及可靠性。 【先前技術】200939448 VI. Description of the Invention: [Technical Fields of the Invention] There is a semiconductor component material structure, which relates to an eight-die semiconductor package structure and method thereof, which can reduce package size and yield. And reliability. [Prior technology]
近年來，高科技電子製造業推出更具特徵且更為人性 化之電子產ασ。半導體科技之快速成長已促使半導體封裝 尺寸縮小、適用多接腳、細間距、電子元件縮小等之快速 進展。晶圓級封裝之目的及優點包含減少生產成本以及藉 由利用較短導線路徑、獲得較佳雜訊比（即訊號對雜訊之比） 而減夕寄生電谷及寄生電感所造成之影響。 因傳統封裝技術必須將晶圓上之晶粒分割成各別之晶 粒且接著各別封裝該H故此類技術對於製造程序而言 係為耗時。因晶片封裝技術係大為受到積體電路發展之影 響故虽電子裝置之尺寸變為高要求時，封裝技術亦係如 此。由於上述之理由，封裝技術之趨勢係朝向現今之錫球 陣列（BGA)、覆晶封裝（覆晶錫球陣列（fc_bga))、晶片尺 寸封裝（csp)、晶圓級封裝（WLP)。「晶圓級封裝」（wLp) 係被瞭解為晶圓上整體封裝、所有互連及其他程序步驟係 於分割成晶粒之前施行。一般而言，於完成所有組裝程序 或封裝程序之後，獨立之半導體封裝係從具數個半導體晶 粒之晶圓分割出。該晶圓級封裝具有極小之尺寸並結合極 佳之電子特性。 口 200939448 於製造方法中，晶圓級晶片尺寸封裝（WLCSP)技術係 為高級封裝技術’藉其晶粒係於晶圓上予以製造及測試， 且接著藉切割而分割出，以用於在表面黏著生產線中組 展因曰曰圓級封裝技術利用整個晶圓作為目標，而非利用 單一晶片或晶粒，因此於進行分割程序之前，封裝及測試 皆已完成。此外，晶圓級封裝（WLp)係如此之高級技術， 因此打線接合、晶粒黏著及底部填充之程序可予以忽略。 藉利用晶圓級封裝技術，可減少成本及製造時間且晶圓級 ©封裝之最終結構尺寸可相當於晶粒大小，故此技術可滿足 電子裝置之微型化需求。再者，晶圓級晶片尺寸封裝 (WLCSP)具有能藉由利用晶粒之週邊區域作為接合點而直 接於晶粒上印刷重分佈電路之優點。其係由重分佈晶粒表 面上之區域陣列而達成，可完全利用晶粒之整塊區域。接 合點係藉由形成覆晶凸塊而位於重分佈電路上，故晶粒之 ❹ 底側係直接連接i具有微型 > 隔接合點 < 印 (PCB) 〇 雖晶圓級晶片尺寸封裝（饥⑽河大為減少訊號路徑 距離’然而當晶粒及内部元件之整合度更高時，於晶粒表 面上容納所有接合點仍然非常困難。當整合度更高時，晶 :上之接腳數增加，故區域陣列中接腳之重分佈也就難以 達到。即使接腳重分佈成功，接腳之間之距離將太小而益 法符合印刷電路板（PCB)之間距。亦即，由於巨大之封裝、 尺寸，此樣先前技術之程序及結構係受困於良率及可靠产 之問題。先前技術之方法之另一缺點係為較高成本及製： 5 200939448 耗時。 級封裝技術具有上述優點，然㈣存在一 二曰曰圓級封裝技術之接受度之問題。例如，晶圓 ^士 構之材料與印刷電路板（PCB)間之熱膨脹係數差 另。 一造成結狀機械不穩HI鍵因素。美國專利申二第 M7⑽號所揭露之封裝方案則係受困於熱膨脹係：不 匹配之問題。乃因先前技術利用由模製混合物包裹之矽晶 粒。如此領域所熟知，石夕材料之熱膨脹係數料2.3，^ 而模製混合物之熱膨脹係數係約2G i⑽。由於混人^ 介電層材料之ID化溫度較高，故此配置會造成晶粒^置於 製程期間偏移’且互連悍墊亦將偏移，而造成良率及效能 問題。於溫度循環期間要回復到原來位置係為困難(若固化 溫度鄰近或高於玻璃化轉變溫度（Tg)，則係由環氧樹脂特 性所造成）。其意指先前之結構封裝不能以大尺寸來製造， 且會造成較高製造成本。 〇 ’若干技術係牽涉到利用直接形成於基板上表面 上之晶粒。如此領域所熟知，形成於半導體晶粒上之焊墊 係透過牽涉到重分佈層（R D L)之習用重分佈程序予以重分 佈成區域陣列形式中之複數個金屬墊。積層將增加封裝: 尺寸。因此，封裝之厚度會增加。其可能與減少晶片尺寸 之需求相牴觸。 此外，先前技術係受困於需要複雜製程以形成板型封 裝。其需要模製工具以用於模製材料之包裹及注入。由於 混合物熱固化後會變形，故不可能控制晶粒表面與混合物 6 200939448 於同水平，因此需要化學機械研磨（CMP)程序以刨光不 平坦之表面。成本因此提高。 _ 鑑於以上所述，本發明提供一種新穎之具有多晶粒之 結構及其方法以用於板型封裝（Panel scale package; PSP)，以便克服上述問題。 【發明内容】 本發明將以若干較佳實施例加以敘述。然而，此領域 之技藝者應得以領會，除此處之詳細敘述之外，本發明可 ❹廣泛實施於其他實施财。树明之範圍係不受此類實施 例所限制，且應視下述申請專利範圍而定。 、本發明之一目的係提供半導體元件封裝結構及其方 法，其可提供一具有堆疊晶粒之新穎超薄封裝結構。 本發明之另一目的係提供半導體元件封裝結構及其方 法，由於基板及印刷電路板具有相同之熱膨祖係數，故可 提供較佳之可靠度。 本發明之又另—目的係提供半導體树封裝結構及其 、’其可提供-簡易之用以形成半導體元件封裝之製程。 本發明之再另—目的係提供半導體元件封裝結構及其 方法，其可降低成本並提高良率。 ^發^另-目的絲供半㈣元件縣結構及其方 /，八可提供一良好之低腳位數元件解決方案。 盆且：：明係提供一半導體元件封裝結構，其包含基板， 過mi:晶粒接收通孔及一導電連接通孔結構，且透 過上述導電連接通孔結構與上述基板之上表面上之第一接 7 200939448 觸墊及上述基板之下表面上之第二接觸塾相輕合；至少一 第一晶粒’其具有帛一接合塾且係言史置於上述晶粒接收通 -孔内；第一黏著材料，其形成於上述第一晶粒之下；第二 •黏著材料，其填充入上述第一晶粒與上述基板之上述晶粒 接收通孔之側壁間之間隔内；第一導線，其係加以形成以 耦合上述第一接合墊與上述第一接觸墊；至少一第二晶 粒:其具有第二接合墊且係附著於上述第一晶粒上；晶粒 附著材料，其形成於上述第二晶粒之下；第二導線，其係 ❹加以形成以耦合上述第二接合墊與上述第一接觸墊；以及 複數介電層’其形成於上述第一及第二導線、上述第一及 第一晶粒以及上述基板之上。 本發明係提供用以形成半導體元件封裝之方法，其包 含提供具有至少一晶粒接收通孔及導電連接通孔結構之基 板，上述基板透過上述導電連接通孔結構與上述基板之上 表面上之第接觸墊及上述基板之下表面上之第二接觸塾 ❹相搞5，印刷圖樣化黏膠於晶粒重佈工具上丨藉由上述圖 樣化黏膠將上述基板接合於上述晶粒重佈工具上；藉由取 放精密對準系統將具有第一接合塾之至少一第—晶粒重分 佈於上述晶粒重佈工具上，使其具有期望之間距並使第一 晶粒之主動面由上述圖樣化黏膠所緊黏；形成第一黏著材 料於上述第一晶粒之背侧上（其可於切割之前以晶圓形式 實施）’將第二黏著材料填充入上述第一晶粒之邊緣與上述 基板之上述晶粒接收通孔間之間隔内；藉由分離上述圖樣 化黏膠將封裝結構（或板晶圓，意指具有内嵌晶粒及黏著材 8 200939448 料之基板）從上述晶粒重佈工具分開；形成第一導線以將上 述第一接合塾連接至上述第一接觸墊；藉由晶粒附著材料 將t有第二接合墊之至少一第二晶粒附著並放置於上述第 :=粒上（晶粒附著材料可以黏著膠膜實施於晶圓形式或 於70成形成第一導線之後印刷晶粒附著材料於第一晶粒 上）；形成第二導線以連接上述第二接合墊以及上述第一接 觸墊；藉由導電連接通孔結構（預形成於基板内）將第一接 觸墊連接至第二接觸墊；形成複數介電層於上述導線、上 ©述第-及第二晶粒之主動面以及上述基板之上表面上；以 及將上述封裝結構（板型）黏著於膠膜上並予以切割使其形 成獨立晶粒。其可於分割晶粒之前以板晶圓形式實施最終 測試及/或預燒程序。 本發明係提供用以形成半導體元件封裝之方法，其包 含提供具有至少一晶粒接收通孔及導電連接通孔結構之基 板，上述基板透過上述導電連接通孔結構與上述基板之上 ❹表面上之第接觸墊及上述基板之下表面上之第二接觸墊 相耦合；印刷圖樣化黏膠於晶粒重佈工具上；藉由上述圖 樣化黏膠將上述基板接合於上述晶粒重佈工具上；藉由取 放精捃對準系統將具有第一接合墊之至少一第一晶粒重分 佈於上述晶粒重佈工具上，使上述第一晶粒之背側由上述 圖樣化黏膠緊黏並使其具有期望之間距且於上述晶粒接收 通孔内；形成第一導線以將上述第一接合墊連接至上述第 一接觸墊；將具有第二接合墊之至少一第二晶粒放置/附著 於上述第一晶粒上（於第二晶粒之背侧上附有黏著膠膜/材 9 200939448 料）’形成第二導線以耦合上述第二接合墊以及上述第一接 觸墊；形成介電層於上述第一及第二晶粒之主動面以及上 -述基板之上表面上且填充入上述第一晶粒邊緣與上述基板 •之上述晶粒接收通孔之側壁間之間隔内；藉由分離上述圖 樣化黏膠將封裝結構（或板型結構，意指具有晶粒及黏著材 料卩此處之介電層之基板）從上述晶粒重佈工具分開·以及 將上述封裝結構（板型）黏著於膠膜上並予以切割使其形成 獨立晶粒（半導體元件）。 Φ 【實施方式】 ^、下敘述中，將提供若干特定細節以徹底瞭解本發 施例％此類敘述係解釋本發明之結構及程序，只 =以，明本發明之較佳實施例，而非用以限制本發明。缺 = Γ者將得以領會，本發明可無需-或多;； 、參昭:或可以其他方法、元件、材料實施。 施例㈡體IS::其係為—^ ❹__構1〇。包含基㈣2、第=二圖 通孔⑼、第一黏著材料106 一 m、曰曰拉接收 合塾108、金屬或導電層11〇、第材料107、第一接 113、導電連接114 s線112、第一接觸墊 ⑵、第二接合塾12 弟一接觸塾出、第二晶粒 介電層118以及複數導雷料124、第二導線128、 介電層118a、118b及n 土 U〇。第一 b圖係顯示多個 成。 8C ’其係利用積層結構及方法形 200939448 、於第一 3圖及第一 b圖中，基板102具有一晶粒接收 通孔105形成於其中，以接收第一晶粒104。晶粒接收通 -孔ι〇5係從基板丨〇2之上表面形成並貫穿基板102至基板 • 102 ,下表面。晶粒接收通孔1〇5係預先形成於基板 中。第一黏著材料1〇6係塗佈（黏著）於第一晶粒1〇4之下 表面之下，其可於切割分離之前以矽晶圓形式實施，藉此 密封第-晶粒104。第二黏著材料1〇7亦重填於第一晶粒 104之邊緣與晶粒接收通孔1〇5之側壁間之間隔内。第一 ©黏著材才斗106及第二黏著材料1〇7均可利用相同之材料。 基板102還包含導電連接通孔結構114形成於其中。 第一接觸墊113及第二接觸塾115(用於有機基 ，成於導電連接通孔結構114之上表面及下表面上以^ 礼之基板102之上表面及下表面上。導電材料係重填入 導電連接通孔結構114内，以用於電性連接。其為製造美 板102時之預先形成程序。 ❹)金屬或導電層U0係選擇性塗佈（藉由濺鍍或無電極 電鍍法（electro-less Plating))於晶粒接收通孔1〇5 :側壁 上’亦即金屬或導電層110係形成於由第二黏著材料⑽ 所環繞之第一晶粒1〇4與基板102之間。藉由利用若干特 別之黏著材料尤其係橡膠型態黏著材料，可改善晶粒邊緣 與基板102之晶粒接收通孔105之側壁之間之黏著強声、、。 第-晶粒’係設置於基板1G2中之晶粒接收ς孔 W5内。如此領域之技藝者所熟知，第一接合墊 成於第-晶粒ΗΜ之上表面内。第一導線112係加以形: 11 200939448 。第一導線112 1以用於電性連 以耦合第—接合墊108及第一接觸墊113 可以打線接合方式或堆疊重分佈方式實施 接。 "月還产含第二晶纟122,其形成於晶粒附著材料 124上，且接著放置/附著於第一晶粒ι〇4之主動面上（或當 利用積層結構時放置/附著於介電層上）。換言之，第二2 粒m係放置/附著於第一晶粒1〇4之上方，:暴露第; 合墊⑽’以用於電性連接（若利用打線接合方式第二晶 粒122具有複數第二接合墊126,其形成於第二晶粒U2 之上气面_L帛一導線！ 28係加以形成以耦合第二接合墊 126及第接觸塾113(其可為接合線或積層結構）。接著， 介電層118係加以形成以覆蓋第一導線ιΐ2、帛二導線 m、第-曰曰“立104及第二晶纟122之上表面以及基板 H)2。當利用積層結構及方法時，介電層可為多個介電層結 構118a、118b、118c，如第一 b圖所示。 積層(重刀佈層(RDL))結構及其程序可選擇性實施於 包覆有晶片之基板之下侧上，以將第二接觸墊耦合至終端 墊。終端墊結構可為錫球陣列（BGA)或平面㈣陣列（lga) 形式。 之後複數導電凸塊12〇係藉由於表面上印刷錫膏 ⑽derpasteX或設置焊錫球）而形成並輕合至終端墊上。隨 後，實施迴焊程序以迴焊錫薈卜 w T (solder paste)。因此，第一 晶粒104及第一"晶粒122可读说道命、± & j還過導電連接通孔結構114、 第一導線112及第二導線f & 守 咏28而與導電凸塊120相電性連 12 200939448 接0 保護基底119係加以利用以防 ^ ^ ^ 防止封裝爻到可能會傷害 .=之外力。其包含黏膠層119&以黏著介電層ιΐ8及保護 基底119。頂部之介電層U8c若 ’、 m 11Q 黏陡夠強亦可用作為黏膠 性，°由於第：黏著材料W具有彈性（伸長）特 &诚甘或導電層11G及第二黏著材料1G7係作為緩衝 G域，其吸收於溫度循環期間第—晶粒1〇4及基板ι〇2之 間之熱機械應力。上述結構係構成平面間格陣列（l ©裝（周圍型）。 於一實施例中，基板1〇2之材料包含環氧型耐高溫玻 璃纖維板（FR5)、玻璃纖維板（FR4)、聚亞醯胺（ρι)或内部具 有破璃纖維之雙馬來醯亞胺三氮雜苯樹脂（BT)。基板ι〇2 之材料亦可為金屬、合金、玻璃、矽、陶瓷或印刷電路板 (PCB)。合金還包含鎳鐵合金（Alloy42)(42%鎳-58%鐵）或柯 弗合金（K〇ver)(29%鎳-17%鈷-54%鐵）。再者，合金較佳係 ❾由鎳鐵合金（Alloy42)所組成，其係為一種鎳鐵合金，其膨 脹係數使其適於加入微型電子電路中之矽晶片，且其係由 42%之鎳以及58%之鐵所組成。合金亦可由柯弗合金 (Kover)所組成，其係由29〇/〇之鎳、17%之鈷以及54〇/〇之鐵 所組成。 基板102之材料較佳為有機基板，例如具已定義通孔 之環氧型耐高溫玻璃纖維板（FR5)、聚亞醯胺（PI)、雙馬來 酿亞胺三氮雜苯樹脂（BT)或印刷電路板（PCB)’或具預蝕刻 電路之銅金屬層。熱膨脹係數（CTE)較佳係與印刷電路板 13 200939448 (PCB)相同。由於基板1G2之熱膨脹係數（cte)係與印刷電 路板（PCB)或主機板（m〇ther b〇ard)之熱膨服係數（Cte)相 .匹配，故本發明可提供具有較佳可靠度之結構。具高玻璃 •化轉變溫度（T g)之有機基板較佳為環氧型耐高溫玻璃纖維 板（FR5)或雙馬來醢亞胺三氮雜苯樹脂（Βτ)型基板。銅金屬 (熱膨脹係數約16)亦可予以利用。玻璃、陶究、石夕亦可予 以利用作為基板。第二黏著材料1〇7較佳係以石夕膠彈性材 料形成，亦可利用環氧樹脂。 © 於—實施例中，第—黏著材料106及第二黏著材料1〇7 之材料包含紫外光(UV)固化型及熱固化型材料、環氧樹脂 或橡膠型材料。第-黏著材料1〇6之材料亦可包含金 料。再者，當使用打線接合時，介電層118之材料包含液 態膠（liquid⑽p_d)、樹脂、石夕膠，而當使用積層結構 時，介電層118之材料則包含苯環丁稀（BCB)、石夕氧烧聚 合物（SINR)或聚亞醯胺（p〇。 ❹〜力-實施例中，保護基底119之材料包含但不限於耐 局溫玻璃纖維板（FR5)、玻璃纖維板（FR4)、聚亞酿胺㈣ 或内部具有玻璃纖維之雙馬來醯亞胺三氮雜苯樹脂（BT)或 金屬。保護基底119可附著於介電層118之頂部上以保護 封裝，且保護基底119亦可藉由雷射程序於其頂部加以標 記。 於一實施例中，晶粒附著材料124之材料包含但不限 於彈性材料。晶粒附著材料124，例如附著膠帶，之内部 係具有間隔球（space balls)，其作為緩衝區域以吸收於溫度 14 200939448 循％期間及熱固化期間第一晶粒1〇4及第二晶粒122間之 熱機械應力。 參照第二a圖，其係根據本發明之另一實施例之半導 體元件封裝結構200之橫切面示意圖。基板2〇2包含導電 連接通孔結構214，其形成於基板 202之四側上，亦即導 電連接通孔結構214係各別形成於基板2〇2之兩側邊（可為 ❹In recent years, the high-tech electronics manufacturing industry has introduced a more characteristic and more humane electronic product ασ. The rapid growth of semiconductor technology has led to rapid advances in semiconductor package size, multi-pin, fine pitch, and shrinking of electronic components. The purpose and advantages of wafer level packaging include reduced production costs and the impact of reduced parasitic valleys and parasitic inductances by using shorter wire paths to achieve better noise ratios (ie, signal to noise ratio). Such techniques are time consuming for manufacturing processes because conventional packaging techniques must divide the dies on the wafer into individual granules and then package the H separately. Since the chip packaging technology is greatly affected by the development of integrated circuits, packaging technology is also the case when the size of electronic devices becomes high. For the above reasons, the trend in packaging technology is toward today's solder ball array (BGA), flip chip package (flip chip) (fc_bga), wafer size package (csp), wafer level package (WLP). Wafer-level packaging (wLp) is understood to be performed on the entire package on the wafer, all interconnects, and other program steps before being split into dies. In general, after completing all assembly procedures or packaging procedures, a separate semiconductor package is separated from a wafer having a plurality of semiconductor crystal grains. This wafer level package is extremely small and combines excellent electronic characteristics. Port 200939448 In the manufacturing method, Wafer Level Wafer Size Package (WLCSP) technology is manufactured and tested for advanced packaging technology by using its die attach to the wafer, and then segmented by cutting for use on the surface. In the adhesive line, the group exhibition uses the entire wafer as the target instead of a single wafer or die, so the package and test are completed before the segmentation process. In addition, wafer level packaging (WLp) is such an advanced technology that the procedures for wire bonding, die attach and underfill can be ignored. By using wafer-level packaging technology, cost and manufacturing time can be reduced and the final structure size of the wafer level © package can be equivalent to the die size, so this technology can meet the miniaturization requirements of electronic devices. Furthermore, Wafer Level Wafer Size Package (WLCSP) has the advantage of being able to print a redistribution circuit directly on the die by utilizing the peripheral region of the die as a junction. This is achieved by redistributing the array of regions on the surface of the die, making it possible to fully utilize the monolithic regions of the die. The junction is located on the redistribution circuit by forming a flip-chip bump, so the bottom side of the die is directly connected to i with a micro-> splicing junction <print (PCB) 晶圆 wafer-level wafer size package ( The hunger (10) river greatly reduces the signal path distance. However, when the integration of the die and the internal components is higher, it is still very difficult to accommodate all the joints on the surface of the die. When the degree of integration is higher, the pin on the crystal: The number is increased, so the weight distribution of the pins in the area array is difficult to achieve. Even if the pin redistribution is successful, the distance between the pins will be too small and the method should conform to the distance between printed circuit boards (PCBs). Huge package and size, such prior art procedures and structures suffer from yield and reliable production. Another disadvantage of prior art methods is higher cost and system: 5 200939448 Time-consuming. With the above advantages, (4) there is a problem of acceptance of one or two round-level packaging technology. For example, the coefficient of thermal expansion between the material of the wafer and the printed circuit board (PCB) is different. Steady HI The packaging scheme disclosed in U.S. Patent Application No. M7(10) suffers from the problem of thermal expansion: mismatch. The prior art utilizes the ruthenium grains wrapped by the molding mixture. As is well known in the art, Shi Xi material The thermal expansion coefficient of the material is 2.3, and the thermal expansion coefficient of the molded mixture is about 2G i(10). Since the ID of the mixed dielectric material is higher, the configuration causes the grain to be shifted during the process. Even the mat will shift, causing yield and performance problems. It is difficult to return to the original position during the temperature cycle (if the curing temperature is near or above the glass transition temperature (Tg), it is made of epoxy resin. The characteristic means that the previous structural package cannot be manufactured in a large size and causes a high manufacturing cost. 若干 'Several technologies involve the use of crystal grains directly formed on the upper surface of the substrate. The pads formed on the semiconductor die are redistributed into a plurality of metal pads in the form of a region array by a conventional redistribution process involving a redistribution layer (RDL). The layer will increase the package size: therefore, the thickness of the package will increase. It may be inconsistent with the need to reduce the size of the wafer. Furthermore, the prior art has been plagued by the need for complex processes to form a plate type package. It requires a molding tool to It is used for the wrapping and injection of molding materials. Since the mixture will be deformed after heat curing, it is impossible to control the grain surface to be at the same level as the mixture 6 200939448, so a chemical mechanical polishing (CMP) procedure is required to plan the uneven surface. The cost is thus increased. In view of the above, the present invention provides a novel multi-die structure and method thereof for use in a panel scale package (PSP) to overcome the above problems. This will be described in terms of several preferred embodiments. However, those skilled in the art will appreciate that the present invention can be widely practiced in other implementations in addition to the detailed description herein. The scope of the tree is not limited by such embodiments and should be determined by the scope of the patent application below. SUMMARY OF THE INVENTION One object of the present invention is to provide a semiconductor device package structure and method thereof that can provide a novel ultra-thin package structure having stacked dies. Another object of the present invention is to provide a semiconductor device package structure and a method thereof, which provide better reliability since the substrate and the printed circuit board have the same thermal expansion coefficient. Still another object of the present invention is to provide a semiconductor tree package structure and its process for providing a semiconductor device package. Still another object of the present invention is to provide a semiconductor device package structure and method thereof which can reduce cost and improve yield. ^ Hair ^ another - the purpose of the wire for the half (four) component county structure and its / / eight can provide a good low-foot digit component solution. The pottery:: Ming system provides a semiconductor component package structure including a substrate, a mi: die receiving via hole and a conductive connection via structure, and the through-hole structure through the conductive connection and the upper surface of the substrate a contact pad 200939448 and a second contact 上 on the lower surface of the substrate are lightly coupled; at least one first die ′ having a first bond and a history of being placed in the die receiving via-hole; a first adhesive material formed under the first die; a second adhesive material filled in a space between the first die and a sidewall of the die receiving via of the substrate; the first wire Forming to couple the first bonding pad and the first contact pad; at least one second die having a second bonding pad and attached to the first die; a die attach material forming Under the second die; a second wire formed to couple the second bonding pad and the first contact pad; and a plurality of dielectric layers formed on the first and second wires, First and first And said particles on the substrate. The present invention provides a method for forming a semiconductor device package, comprising: providing a substrate having at least one die receiving via and a conductive connection via structure, wherein the substrate passes through the conductive connection via structure and the upper surface of the substrate The contact pad and the second contact surface on the lower surface of the substrate are printed, and the patterned adhesive is printed on the die re-wiping tool, and the substrate is bonded to the die by the patterned adhesive. Disposing at least one first die having a first bond 于 on the die re-wiring tool by a pick and place precision alignment system to have a desired distance and an active face of the first die Bonded by the patterned adhesive; forming a first adhesive material on the back side of the first die (which can be implemented as a wafer before cutting) 'filling the second adhesive material into the first die The edge is spaced from the die receiving via of the substrate; the package structure is formed by separating the patterned adhesive (or the plate wafer, meaning having the embedded die and the adhesive material 8 200939448 a substrate) separated from the die re-wiring tool; forming a first wire to connect the first bonding pad to the first contact pad; and t-having at least a second crystal of the second bonding pad by a die attach material The granules are attached and placed on the above-mentioned granules (the granule-adhesive material may be applied to the wafer in the form of a film or after 70% of the first wires are formed to be printed on the first crystal grains); a wire for connecting the second bonding pad and the first contact pad; connecting the first contact pad to the second contact pad by a conductive connection via structure (preformed in the substrate); forming a plurality of dielectric layers on the wire, The active surface of the first and second crystal grains and the upper surface of the substrate are attached; and the package structure (plate type) is adhered to the adhesive film and cut to form independent crystal grains. It can perform final testing and/or burn-in procedures in the form of plate wafers prior to dicing the dies. The present invention provides a method for forming a semiconductor device package, comprising: providing a substrate having at least one die receiving via and a conductive connection via structure, wherein the substrate passes through the conductive connection via structure and the upper surface of the substrate The contact pad is coupled to the second contact pad on the lower surface of the substrate; the patterned adhesive is printed on the die re-wiping tool; and the substrate is bonded to the die re-wiping tool by the patterned adhesive Relocating at least one first die having a first bonding pad to the die re-wiring tool by a pick and place alignment system, such that the back side of the first die is formed by the patterned adhesive Tightly bonding and having a desired distance between the die receiving vias; forming a first wire to connect the first bonding pad to the first contact pad; and at least a second crystal having a second bonding pad Placing/attaching the particles on the first die (with an adhesive film/material 9 200939448 on the back side of the second die) forming a second wire to couple the second bonding pad and the first connection a pad; forming a dielectric layer between the active surface of the first and second dies and the upper surface of the substrate and filling the sidewall of the first die and the sidewall of the die receiving via of the substrate By separating the patterned adhesive, the package structure (or the plate-type structure, meaning the substrate having the die and the adhesive material, the dielectric layer here) is separated from the above-mentioned die-removing tool, and The above package structure (plate type) is adhered to the film and cut to form individual crystal grains (semiconductor elements). Φ [Embodiment] In the following description, certain specific details are provided to provide a thorough understanding of the present embodiments. The description of the present invention is to explain the structure and the procedure of the present invention. It is not intended to limit the invention. Lack of = The latter will be able to understand, the present invention may not need - or more;;, reference: or can be implemented by other methods, components, materials. Example (2) Body IS:: The system is -^ ❹__ structured 1〇. The base (4) 2, the second through hole (9), the first adhesive material 106-m, the pull-receiving composite 108, the metal or conductive layer 11A, the first material 107, the first connection 113, and the conductive connection 114 s line 112 The first contact pad (2), the second bonding pad 12, the contact pad, the second die dielectric layer 118, and the plurality of conductive materials 124, the second wires 128, the dielectric layers 118a, 118b, and the n-wells. The first b-picture shows multiple generations. 8C' uses a laminate structure and method shape 200939448. In the first 3 and the first b, the substrate 102 has a die receiving via 105 formed therein to receive the first die 104. The die receiving via-hole 〇5 is formed from the upper surface of the substrate 丨〇2 and penetrates the substrate 102 to the substrate 102, the lower surface. The die receiving via 1 〇 5 is formed in advance in the substrate. The first adhesive material 1〇6 is coated (adhered) under the surface of the first die 1〇4, which can be implemented as a germanium wafer before the dicing separation, thereby sealing the first die 104. The second adhesive material 1〇7 is also refilled in the space between the edge of the first die 104 and the sidewall of the die receiving via 1〇5. The first material of the adhesive material 106 and the second adhesive material 1〇7 can be made of the same material. The substrate 102 also includes a conductive connection via structure 114 formed therein. The first contact pad 113 and the second contact pad 115 (for the organic substrate are formed on the upper surface and the lower surface of the substrate 102 on the upper surface and the lower surface of the conductive connection via structure 114. The conductive material is heavy Filled into the conductive connection via structure 114 for electrical connection. It is a pre-forming procedure for manufacturing the US board 102. ❹) Metal or conductive layer U0 is selectively coated (by sputtering or electrodeless plating) Electro-less Plating is performed on the die receiving via 1〇5: sidewalls, that is, the metal or conductive layer 110 is formed on the first die 1〇4 and the substrate 102 surrounded by the second adhesive material (10). between. By using a plurality of special adhesive materials, particularly rubber-type adhesive materials, the adhesion between the edge of the die and the sidewall of the die receiving via 105 of the substrate 102 can be improved. The first-grain pattern is disposed in the die receiving pupil W5 in the substrate 1G2. As is well known to those skilled in the art, the first bond pad is formed in the upper surface of the first die. The first wire 112 is shaped: 11 200939448. The first wire 112 1 can be electrically connected to couple the first bonding pad 108 and the first contact pad 113 in a wire bonding manner or a stack redistribution manner. "Month also produces a second wafer 122 formed on the die attach material 124 and then placed/attached to the active face of the first die 4 (or placed/attached when utilizing the buildup structure) On the dielectric layer). In other words, the second 2 m is placed/attached over the first die 1〇4, exposing the pad; the pad (10)' is used for electrical connection (if the second die 122 has a plurality of wires by wire bonding) A bonding pad 126 is formed on the second die U2. The 28 is formed to couple the second bonding pad 126 and the first contact pad 113 (which may be a bonding wire or a laminate structure). Next, the dielectric layer 118 is formed to cover the first wire 2, the second wire m, the first surface of the first and second wafers 122, and the substrate H) 2. When the laminated structure and method are utilized The dielectric layer can be a plurality of dielectric layer structures 118a, 118b, 118c, as shown in the first b. The laminate (heavy knife layer (RDL)) structure and its program can be selectively implemented on a wafer covered On the underside of the substrate, the second contact pad is coupled to the termination pad. The termination pad structure can be in the form of a solder ball array (BGA) or a planar (four) array (lga). The plurality of conductive bumps 12 are then printed by surface printing. Solder paste (10) derpasteX or set solder ball) is formed and lightly bonded to the terminal pad. Subsequently, reflow is performed. The procedure is to return the solder paste. Therefore, the first die 104 and the first "die 122 can be read, and the ± & j also passes through the conductive connection via structure 114, the first wire 112. And the second wire f & 咏 28 and electrically connected to the conductive bump 120 12 200939448 0 protection base 119 is used to prevent ^ ^ ^ to prevent the package from being damaged. The adhesive layer 119 & adheres to the dielectric layer ι 8 and protects the substrate 119. The top dielectric layer U8c can be used as a viscose if the viscosity is strong enough, and the adhesive material W has elasticity (elongation). & Chenggan or conductive layer 11G and second adhesive material 1G7 are used as the buffer G domain, which absorbs the thermomechanical stress between the first grain 1〇4 and the substrate ι2 during the temperature cycle. Grid array (1 © (peripheral). In one embodiment, the material of the substrate 1 〇 2 comprises epoxy type high temperature resistant glass fiber board (FR5), glass fiber board (FR4), polytheneamine (ρι) or Bismaleimide triazabenzene resin (BT) with glass fiber inside. The material of the board 亦可2 can also be metal, alloy, glass, tantalum, ceramic or printed circuit board (PCB). The alloy also contains nickel-iron alloy (Alloy 42) (42% nickel - 58% iron) or Coffer alloy (K 〇 Ver) (29% nickel-17% cobalt-54% iron). Further, the alloy is preferably made of nickel-iron alloy (Alloy42), which is a nickel-iron alloy, and its expansion coefficient makes it suitable for adding microelectronics. The silicon wafer in the circuit is composed of 42% nickel and 58% iron. The alloy may also consist of Kover, which consists of 29 〇/〇 of nickel, 17% of cobalt, and 54 〇/〇 of iron. The material of the substrate 102 is preferably an organic substrate, such as an epoxy type high temperature resistant glass fiber board (FR5) having a defined through hole, polyimide (PI), and bismaleimide triazabenzene resin (BT). Or a printed circuit board (PCB)' or a copper metal layer with a pre-etched circuit. The coefficient of thermal expansion (CTE) is preferably the same as printed circuit board 13 200939448 (PCB). Since the thermal expansion coefficient (cte) of the substrate 1G2 is matched with the thermal expansion coefficient (Cte) of the printed circuit board (PCB) or the motherboard (m〇ther b〇ard), the present invention can provide better reliability. The structure. The organic substrate having a high glass transition temperature (T g) is preferably an epoxy type high temperature resistant glass fiber board (FR5) or a bismaleimide triazabenzene resin (Βτ) type substrate. Copper metal (a thermal expansion coefficient of about 16) can also be utilized. Glass, ceramics, and stone eve can also be used as substrates. The second adhesive material 1〇7 is preferably formed of a Shijiao rubber elastic material, and an epoxy resin may also be used. © In the embodiment, the material of the first adhesive material 106 and the second adhesive material 〇7 includes an ultraviolet (UV) curable type and a thermosetting type material, an epoxy resin or a rubber type material. The material of the first-adhesive material 1〇6 may also contain gold. Furthermore, when wire bonding is used, the material of the dielectric layer 118 contains liquid glue (liquid (10) p_d), resin, and shijiao, and when a laminate structure is used, the material of the dielectric layer 118 contains benzene ring butyl (BCB). , Shixi Oxygenated Polymer (SINR) or Polyimide (p〇. ❹~force - In the embodiment, the material of the protective substrate 119 includes, but is not limited to, temperature-resistant glass fiber board (FR5), glass fiber board (FR4) Polyraminate (IV) or double-maleimide arsenazo resin (BT) or metal having glass fibers inside. The protective substrate 119 may be attached on top of the dielectric layer 118 to protect the package, and protect the substrate 119. It can also be marked on the top by a laser program. In one embodiment, the material of the die attach material 124 includes, but is not limited to, an elastic material. The die attach material 124, such as an adhesive tape, has a spacer ball inside. Space balls), which serve as a buffer region to absorb the thermo-mechanical stress between the first die 1〇4 and the second die 122 during the temperature period and during the thermal curing period. Another embodiment of the invention A schematic cross-sectional view of the semiconductor device package structure 200. The substrate 2〇2 includes conductive connection via structures 214 formed on four sides of the substrate 202, that is, the conductive connection via structures 214 are formed on the substrate 2〇2, respectively. Both sides (can be ❹
四端侧邊）上。第一接觸塾213及第二接觸& 215係各別形 成於導電連接通孔結構214之上表面及下表面以及部份之 基板202之上表面及下表面上。_電材料係重填入導電連 接通孔結構214内，以用於電性連接。於完成分割後，每 -獨立封裝係共享一半之導電連接通孔結構。 卞守镀兀件封裝結構200包含第二晶粒222， ，具^複數第二接合塾226形成於第二晶粒222之上表面 。第-晶粒222係形成於晶粒附著材料以上，接著將 放置/附著於第一晶粒2〇4之主動面上(若利 晶粒之第一 形成導線，則第二晶粒222係附著於第-曰粒2〇4 t 上）。換§之，第二晶粒222係放置於第一 利用打線接Μ ί 〇8,以用於電性連接（若 墊咖及二接觸 :板之下側上形成積層(重分佈層: 於第二晶粒222内之第二接合^^塾2G8以及形成 226可糟由導電連接通孔 15 200939448 結構214、第一導線212及第二導線228而與導電凸塊22〇 相電性連接。 金屬或導電層210係選擇性塗佈於晶粒接收通孔2〇5 之侧壁上’亦即金屬或導電層21〇係形成於由第二黏著材 料207所環繞之第一晶粒204與基板202之間。 再者，如第一圖及第二圖所示，半導體元件封裝結構 200中之若干元件係與半導體元件封裝結構1〇〇中之元件 相似，故省略其詳細敘述。 ❹On the side of the four ends). The first contact pads 213 and the second contacts & 215 are respectively formed on the upper surface and the lower surface of the conductive connection via structure 214 and a portion of the upper surface and the lower surface of the substrate 202. The electrical material is refilled into the conductive via structure 214 for electrical connection. After the split is completed, each of the individual packages shares half of the conductive connection via structure. The ruthenium plated package structure 200 includes a second die 222 having a plurality of second bond pads 226 formed on the upper surface of the second die 222. The first die 222 is formed on the die attach material, and then placed/attached to the active surface of the first die 2〇4 (if the first die of the die is formed, the second die 222 is attached) On the first - 曰 grain 2〇4 t). In other words, the second die 222 is placed on the first wire bonding interface 以 〇 8 for electrical connection (if the pad and the two contacts: a layer is formed on the lower side of the plate (redistribution layer: The second bonding 2G8 and the formation 226 in the two dies 222 are electrically connected to the conductive bumps 22 by the conductive connection vias 15 200939448 structure 214, the first wires 212 and the second wires 228. Or the conductive layer 210 is selectively coated on the sidewall of the die receiving via 2', that is, the metal or conductive layer 21 is formed on the first die 204 and the substrate surrounded by the second adhesive 207. Further, as shown in the first and second figures, a plurality of elements in the semiconductor element package structure 200 are similar to those in the semiconductor element package structure 1A, and detailed description thereof will be omitted.
第二b圖係根據本發明之一實施例之半導體元件封裝 結構200之結構之橫切面示意圖。第一接觸墊係形 於導電連接通孔結構214之上。導電連接通孔結構2 位於切割線23〇之區域上。換言之，每—半導體元件封裝 結構於切割後，各具有—半之導電連接通孔結構叫（由^ 右干區域係被切除，故實際上其尺寸係少於-半）。導雷、查 接通孔結構214之内部係填充有導電材料，且/或另外之1 餘區域係以環氧樹脂填塞。其可改善表面黏著程序期間； 焊錫熔接品#，且亦可降低封裝尺寸（foot pdnt)。同樣地 導電連接通孔結構214之結構可形成於晶粒通 壁上（未顯㈣圖中），其可取代金屬或導J 214箱性可稱作連接渠 參照第三a圖及第三6圖，其係根據本發明 半導體元件封裝結構細之橫切面 = 實施例可於第三a圖及第…視得。半導體元件封2 200939448 構200可無需於第二接觸墊215上形成導電凸塊22〇而予 以形成。其他元件係與第_ a圖及第一 b圖相似，故省略 . 其詳細敘述。 從介電層218之表面至基板202之上表面之厚度”交 佳為約118至218微米。從基板202之上表面至其下表面 之厚度a較佳為約60至15〇微米。是故，本發明可提供一 超薄結構，其總厚度小於5〇〇微米，且其封裝尺寸約為晶 粒尺寸每側加上〇.5毫米至1毫米，以藉由使用傳統印刷 ❹電路板（PCB)製程形成晶片尺寸封裝（csp)。 參照第四圖’其係根據本發明之一實施例之半導體元 件封裝結構100之下視圖。半導體元件封裝結構1〇〇之背 側包含基板1〇2(焊錫遮罩層未顯示於圖中）、形成於其中之 第二黏著材料107以及周圍環繞之複數第二接觸墊115。 如圖中虛線以外區域所示，半導體元件封裝結構100選擇 性包含金屬層150’其係以濺鑛或電鑛方式佈於第一晶粒 ❹104之背側上，以取代第一黏著材料1〇6，其可增加埶傳導 率。圖巾之虛、線以内區域係表示第二晶粒122之區^。金 屬層15〇可藉㈣膏與印刷電路板(PCB)相熔接，其可透 過印刷電路板之銅金屬將熱導出（產生自晶粒之熱）。 參照第五圖，其係根據本發明之一實施例之半導體元 件封裝結構UK)之上視圖。半導體元件封裝結構1〇〇之頂 側包含基板102以及形成於第一黏著材料1〇6上之第一晶 粒104。複數第-接觸塾113係形成於基板1〇2邊緣區域 之四周。第-導線112係加以形成以耦合第一接合墊1〇8 17 200939448 與第一接觸t 113。再者，第二晶粒122係形成於第一晶 粒104之上，以暴露第—接合墊1〇8(當使用打線接合時）。 .第二導線128係加以形成以耦合第二接合墊126與第一接 觸墊U3。此領域之技藝者應注意，第一導線112以及第 二導線128於介電層118及保護基底119形成後，即無法 視得。 此外，半導體元件封裝結構1〇〇可應用於更高腳位 數。本實施例係與第五圖相似，故省略其詳細敘述。是故， ❹本周圍型之發明可提供一良好之低腳位數封裝解決方案。 根據本發明之另一觀點，本發明更提供一用於形成半 導體元件封裝結構100之方法，上述半導體元件封裝結構 100具有多晶粒，例如第一晶粒刚及第二晶粒122。參照 第六a圖至第六4圖，其係為用以形成半導體元件封裝結 構100之方法之橫切面示意圖。其實施步驟係如下所述。 如第六a圖所示，首先提供具有晶粒接收通孔1〇5、 ❹導電連接通孔結構114、第一接觸$ 113於其上表面上以 及第二接觸墊115於其下表面上之基板1〇2, #中晶粒接 收通孔105、導電連接通孔結構114、第一接觸墊113以及 第二接觸墊115係預先形成於基板ι〇2内。提供一具有對 f圖型形成於其上之晶粒重佈工具_，且圖樣化黏膠係 P刷於上述工具上（未圖示）。基板1〇2係接合至上述晶粒 重佈工具300。如第六b圖所示，將具有第一接合墊1〇8 第B曰粒104藉由取放精密對準系統重分佈於晶粒重佈 工具300上使其具有期望之間距且放入基板ι〇2之晶粒接 18 200939448 ❹ 收通孔Η)5内，而第—晶粒1〇4係藉由圖樣 晶粒重佈工具300上。亦即，第—晶粒1〇4之主動 由圖樣化黏膠（未圖示）而緊黏於晶粒重佈工具3⑽上。二 將第二黏著材_ 1〇7填入第一晶粒1〇烟壁）與第一立 1〇4背侧上之第一黏著材料1〇6之間之間隔後，第―：著 材料106與第二黏著材料1〇7接著經過固化。於此應用中， 第-黏著材料106與第二黏_ 1〇7可以同一材料製 成。之後，封裝結構（板晶圓形式）遂從晶粒重佈工且 分離。 八 於清潔第一接合墊1〇8以及第一接觸墊ιΐ3 細樣化黏膠可能殘留於第一接…。8以及第一= 塾113之上表面上），如第六c圖所示，形成第一導線112 以將第一接合墊1〇8連接至第一接觸墊u3，其中導線可 藉由打線接合程序或積層程序而形成。積層程序可實施於 基板102之上表面上之介電層上，且用以開啟第一接合 ❾墊例如接著濺鍍種子金屬層，形成光阻以形成導線圖形 並電鍍金屬於上述圖形上，之後剝除光阻，進行金屬濕蝕 】乂形成重分佈層（RDL)導線，塗佈或印刷第二介電層 等隨後，第二晶粒122係形成於晶粒附著材料124之上， 接著將第二晶粒122放置並附著於第一晶粒104之上（若黏 2夠強，則第二介電層可用作為黏著材料）。若實施打線接 _ ‘ν«用則第一晶粒122並未覆蓋住第一接合墊1 〇8，故 而第一接合墊1〇8可暴露出以用於電性連接。第二晶粒122 係具有第二接合墊126形成於其上。接著，第二導線128 200939448 係耦合至第二接合墊126與第一接觸墊113。第二導線之 製程可與第一導線之製程相同。 、 .接著，如第六d圖所示，介電層118係塗佈（模製、印 刷或散佈）並固化於第一晶粒1〇4以及第二晶粒122之主動 面與基板102之上表面上，以保護第一導線112、第一晶 粒104、第二導線128、第二晶粒122以及基板。若應 用積層程序形成導線，則若干介電層係用於積層程序，且 保護基底119係選擇性藉由黏膠層n9a黏附於介電層上， ©以保濩封裝並藉由雷射於頂部表面進行標記。終端接觸塾 係藉由印刷錫膏（或錫球）而形成於第二接觸墊ιΐ5上。積 層程序亦可選擇性應用於包覆有晶粒之基板之下表面上， f將第二接觸墊耦合至終端墊（終端墊可為陣列形式卜接 著’複數導電凸塊12〇係藉由紅外線迴焊（IR灿時)法形 成’並耦合至第二接觸墊115或終端墊。隨後，封構妬 晶圓形式）係黏著於一膠臈302上，以用於晶粒分;^板 板晶圓最終測試或板晶圓預燒(burn_in)程 封裝分割之前實施。 遇擇I·生於 金屬或導電層110係選擇性形成於基板1〇2中 接收通孔105之側壁上，此金屬可其 日曰边 雷托心… U㈣屬可於基板製程期間藉由盔 電木電鍍（electr〇-iess platingR㈣程序再加上 等而預先形成。金屬膜（或層）可濺錢或電鑛於第— 之背側上，以作為第一斑签Λ < 〇4 丨户兩弟黏者材枓106，以得到較伟 理需求。 乂1主之熱處 根據本發明之另一觀點 本發明亦提供另1法用以 20 200939448 形成具有晶粒接收通孔205及導電連接通孔結構214之半 導體7L件封裝結構2〇〇。參照第七a圖至第七h圖，其係 根據本發明之另一實施例之形成半導體元件封裝結構200 之方法之橫切面示意圖。 形成半導體元件封裝結構200之步驟包含提供具有晶 粒接收通孔205、導電連接通孔結構214、第—接觸墊2 = ❹ 1其3面上以及第二接觸塾215於其下表面上之基板 。如第七a圖所示’基板2〇2係接合至上述晶粒重佈工 換言之’基#反2〇2之主動面（用於焊錫炫接）係藉由 I7 1丨圖樣化黏膠（未圖示）而緊黏於晶粒重佈工具上。 b圖所示’第—晶粒204係具有形成於第—晶粒綱 t面之第-接合墊208，且第一黏著材料206(其選擇 可為黏性膠膜）係形成於第一晶粒2〇4之背側上。s 粒204係藉由取放精密對準 曰曰 ιΛη L t 王刀神κ日日粒重佈工具 上，以使第一晶粒204之背側由圖婵/ 曰 矿惻糟由圖樣化黏膠緊黏於 :粒重佈工具300上並使其具有期望之間距。如第七c圖 所不，之後，第一導線212係加以形成將第 連接至第-接觸墊213。 /成以將第一接合塾通 如第七d圖所示，隨德，筮一 ^ 第一日日粒222係形成於晶粒 上，並接著形成於第一晶粒2〇4之上 -接合塾2G8。第二晶粒222係具曰粒 =;::? 226。接著’第-黏著材料= ::材枓224係經過固化。如第七 線228係加以形成以輕合第 第一導 恢。墊226以及第一接觸墊 21 200939448 213 ° 如第七f圖所示，接著，介電層218係形成於第—晶 粒204以及第二晶粒222之主動面與基板202之上表面 上’以完全覆蓋第一導線212及第二導線228，並填充入 晶粒邊緣與晶粒接收通孔205之侧壁間之間隔内，以作為 第二黏著材料207，且之後介電層218係經過固化。如第 七g圖所示，隨後，於藉由分離圖樣化黏膠而將封裝結構 從晶粒重佈工具300分開後，清潔基板202之背側以及第 ❹一黏著材料206(以清除殘留之圖樣化黏膠）。 另則，終端接觸墊係藉由印刷錫膏（或錫球）而形成於 第二接觸墊215之上。複數導電凸塊22〇係選擇性加以形 成且耦合至第二接觸墊215。之後，半導體元件封裝結構 200係黏著於一膠膜302以用於晶粒分割。 金屬或導電層210係選擇性形成於基板2〇2中之晶粒 接收通孔205之侧壁上，其係如上所述預先形成。用以形 ❹成第一黏著材料206之另一製程步驟，包含利用種子金屬 濺鍍、形成圖案、電鍍（銅）、光阻去除、金屬濕蝕刻等牛 驟’以形成金屬層。 乂 如第七h圖所示，於一實施例中，於晶粒分 間係利用傳統之切割刀片232。於分割程序期間切割刀片 232係對準切割線23〇以將晶粒（半導體元件封幻分離 獨立晶粒。 於一實施例中，形成導電凸塊12〇與22〇之步驟 由紅外線迴焊（IRrefl〇w)法實施。 ’、糟 22 200939448 此領域之技藝者應注意，此處所說明之材料盘 ;置係】以敘述本發明’而非用以限制本發明。材；與結 •構之配置可根據不同狀況之需求加以調整。 、 減本發明之—實施例，本發明係提供—種且有 接^孔及導電連接通孔結構之半導體元件封装曰，曰盆 Z提供-超薄之封裝結構，其厚度小於 ς 裝尺寸略大於晶粒尺寸。再者，本發明係提供一良好= ❹ =之案’以用於周圍型應用。本發明係提供 裝;:法且其可改善可靠度及良 構，咖亦可將=寸多晶粒結 =成本之材料及簡易製程而降低成本。是丄= 所益尺寸封裝結構及其方法可提供先前技術 =:=:決=之問題。其方法可實施 關之應用。 、"實施並加以調整成其他相 =此似之㈣讀得以财，上職㈣施例之敛 明本發明而非用以限^本發明。其專利保護範 =藝不脫離本專利精神或範圍内，所= =飾且本發明所揭示精神下所完成之等效改變 發月可藉由說明書中若干較佳實施例及詳細敘述以 23 200939448 及後附圖式得以暸解。然而，此領域之技藝者應得以領 所有本發明之較佳實施例係用以說明而非用以限制本發曰 . 之申請專利範圍，其中： x % • 第一 a圖係根據本發明之一實施例之半導體元件封 結構之橫切面示意圖（打線接合型）。 、 第一 b圖係根據本發明之一實施例之半導體元件封 結構之橫切面示意圖（重分佈層型）。 x ❹ 第二a圖係根據本發明之另一實施例之半導體元 裝結構之橫切面示意圖。 封 第二b圖係根據本發明之另一實施例之半導體元 裝結構之橫切面示意圖。 封 第三a圖係根據本發明之另一實施例之半導體元件 裝結構之橫切面示意圖（打線接合型）。 、 第三b圖係根據本發明之另一實施例之半導體元 裝結構之橫切面示意圖（重分佈層型）。 、 ❹ 第四圖係根據本發明之-實施例之半導體元 構之下視圖。 衣、、 第五圖係根據本發明之一實施例之半導體元 構之上視圖。 教、、，σ 半導圖係根據本發明之一實施例之形成 牛導體兀件封裝結構之方法之橫切面示意圖。 成丰圖至第^圖係根據本發明之另—實施例之形 成+導體it件封裝結構之方法之橫切面示意圖。 【主要元件符號說明】 24 200939448 100半導體元件封裝結構 102基板 104第一晶粒 105晶粒接收通孔 106第一黏著材料 107第二黏著材料 108第一接合墊 110金屬或導電層 ❹112第一導線 113第一接觸墊 114導電連接通孔結構 115第二接觸塾 118介電層 118a介電層 118b介電層 118 c介電層 ® 119保護基底 119a黏膠層 120導電凸塊 122第二晶粒 124晶粒附著材料 126第二接合墊 128第二導線 150金屬層 200半導體元件封裝結構 202基板 204第一晶粒 205晶粒接收通孔 206第一黏著材料 207第二黏著材料 208第一接合塾 210金屬或導電層 212第一導線 213第一接觸墊 214導電連接通孔結構 215第二接觸墊 218介電層 218 a介電層 218b介電層 218c介電層 219保護基底 219a黏膠層 220導電凸塊 222第二晶粒 224晶粒附著材料 226第二接合墊 228第二導線 230切割線 25 200939448 232切割刀片 302膠膜 300晶粒重佈工具Figure 2b is a cross-sectional view showing the structure of a semiconductor device package structure 200 in accordance with an embodiment of the present invention. The first contact pad is formed over the conductive connection via structure 214. The conductive connection via structure 2 is located on the area of the dicing line 23A. In other words, each of the semiconductor device package structures has a semi-conducting connection via structure after being cut (the right stem region is cut off, so the size is actually less than - half). The interior of the lead-through, check-on via structure 214 is filled with a conductive material, and/or the other regions are filled with epoxy. It improves the surface adhesion process; solder welds #, and also reduces the package size (foot pdnt). Similarly, the structure of the conductive connection via structure 214 can be formed on the die via wall (not shown in (4)), which can replace the metal or the J 214 box can be called the connection channel. Referring to the third a diagram and the third 6 The figure is a cross section of a semiconductor device package structure according to the present invention. The embodiment can be viewed in the third a diagram and the .... The semiconductor device package 2 200939448 may be formed without forming conductive bumps 22 on the second contact pads 215. The other components are similar to those of the _a and the first b, and are omitted. The thickness from the surface of the dielectric layer 218 to the upper surface of the substrate 202 is preferably about 118 to 218 μm. The thickness a from the upper surface of the substrate 202 to the lower surface thereof is preferably about 60 to 15 μm. The present invention provides an ultra-thin structure having a total thickness of less than 5 Å and a package size of about 55 mm to 1 mm per side of the grain size for use by using a conventional printed ❹ circuit board ( The PCB process forms a wafer size package (csp). Referring to the fourth figure, it is a bottom view of a semiconductor device package structure 100 according to an embodiment of the present invention. The back side of the semiconductor device package structure 1 includes a substrate 1〇2 (a solder mask layer is not shown in the drawing), a second adhesive material 107 formed therein, and a plurality of second contact pads 115 surrounded by the surrounding. As shown in the area other than the broken line in the figure, the semiconductor device package structure 100 selectively includes a metal. The layer 150' is disposed on the back side of the first die ❹ 104 in a splash or electric ore manner to replace the first adhesive material 〇6, which can increase the yttrium conductivity. The area of the second die 122 is indicated. The metal layer 15 can be fused to the printed circuit board (PCB) by means of a (4) paste, which can be thermally conducted (generated from the heat of the die) through the copper metal of the printed circuit board. Referring to the fifth figure, it is according to the present invention. The top view of the semiconductor device package structure UK) includes a substrate 102 and a first die 104 formed on the first adhesive material 〇6. The plurality of first contacts 塾113 is formed around the edge region of the substrate 1〇2. The first wire 112 is formed to couple the first bonding pad 1〇8 17 200939448 with the first contact t 113. Further, the second die 122 is formed in the first Above a die 104 to expose the first bond pad 1〇8 (when wire bonding is used). The second wire 128 is formed to couple the second bond pad 126 with the first contact pad U3. It should be noted that the first conductive line 112 and the second conductive line 128 are not visible after the formation of the dielectric layer 118 and the protective substrate 119. In addition, the semiconductor device package structure 1 can be applied to higher pin numbers. The example is similar to the fifth figure, so the details are omitted. In summary, the invention of the present invention provides a good low-foot package solution. According to another aspect of the present invention, the present invention further provides a method for forming a semiconductor device package structure 100, the semiconductor The component package structure 100 has a plurality of crystal grains, for example, a first die and a second die 122. Referring to FIGS. 6a to 6-4, a cross-sectional view of a method for forming the semiconductor device package structure 100 is shown. The implementation steps are as follows: As shown in the sixth figure, first, there is provided a die receiving via hole 1〇5, a germanium conductive connection via structure 114, a first contact $113 on the upper surface thereof, and a second The substrate 1〇2, #中 die receiving via 105, the conductive connection via structure 114, the first contact pad 113 and the second contact pad 115 of the contact pad 115 on the lower surface thereof are formed in the substrate ι2 in advance. . A die rewiping tool _ having a pattern of f is formed thereon, and a patterned adhesive P is brushed on the tool (not shown). The substrate 1〇2 is bonded to the above-described crystal grain resurfacing tool 300. As shown in FIG. b, the first bonding pad 1〇8 B particles 104 are redistributed on the die redistribution tool 300 by the pick and place precision alignment system to have a desired distance and placed in the substrate. The die of ι〇2 is connected to the hole 20095, and the first die 1〇4 is reapplied to the tool 300 by the pattern die. That is, the active of the first die 1〇4 is adhered to the die redistribution tool 3 (10) by a patterned adhesive (not shown). After the second adhesive material _ 1〇7 is filled into the gap between the first die 1 〇 壁 与 与 与 与 与 背 背 背 背 背 背 背 背 背 背 背 背 ― ― ― ― ― ― ― ― ― ― ― 106 and the second adhesive material 1〇7 are then cured. In this application, the first adhesive material 106 and the second adhesive material _1〇7 may be made of the same material. Thereafter, the package structure (in the form of a plate wafer) is reworked and separated from the die. 8. Cleaning the first bonding pad 1〇8 and the first contact pad ιΐ3 The fine-formed adhesive may remain in the first connection. 8 and the first = 之上 113 upper surface), as shown in the sixth c, forming the first wire 112 to connect the first bonding pad 1 〇 8 to the first contact pad u3, wherein the wire can be bonded by wire bonding Formed by a program or a layered program. The stacking process can be performed on the dielectric layer on the upper surface of the substrate 102, and is used to open the first bonding pad, for example, to sputter the seed metal layer, form a photoresist to form a wire pattern and plate the metal on the pattern, and then Stripping the photoresist, performing metal wet etching, forming a redistribution layer (RDL) wire, coating or printing a second dielectric layer, etc., and then forming a second die 122 on the die attach material 124, and then The second die 122 is placed and attached to the first die 104 (if the bond 2 is strong enough, the second dielectric layer can be used as an adhesive material). If the wire bonding _ ‘ν« is used, the first die 122 does not cover the first bonding pads 1 〇 8 , so that the first bonding pads 1 〇 8 can be exposed for electrical connection. The second die 122 has a second bond pad 126 formed thereon. Next, the second wire 128 200939448 is coupled to the second bond pad 126 and the first contact pad 113. The process of the second wire can be the same as the process of the first wire. Next, as shown in FIG. 4D, the dielectric layer 118 is coated (molded, printed or dispersed) and cured on the active surface of the first die 1 and the second die 122 and the substrate 102. On the upper surface, the first wire 112, the first die 104, the second wire 128, the second die 122, and the substrate are protected. If a lamination procedure is used to form the wires, a plurality of dielectric layers are used for the lamination process, and the protective substrate 119 is selectively adhered to the dielectric layer by the adhesive layer n9a, which is packaged by the protective layer and is lasered at the top. The surface is marked. The terminal contact is formed on the second contact pad 5 by printing a solder paste (or a solder ball). The stacking process can also be selectively applied to the underlying surface of the substrate coated with the die, f coupling the second contact pad to the terminal pad (the terminal pad can be in the form of an array) then the 'multiple conductive bumps 12 are connected by infrared rays The reflow (IR can be) method is formed 'and coupled to the second contact pad 115 or the termination pad. Subsequently, the encapsulated wafer form) is adhered to a capsule 302 for use in the die division; The wafer final test or board wafer burn-in (burn_in) package is implemented before the partition. The selected metal I or the conductive layer 110 is selectively formed on the sidewall of the receiving via 105 in the substrate 1 , 2, and the metal can be turned on the side of the retort... U(4) genus can be used during the substrate manufacturing process by the helmet The electro-rectification (electr〇-iess platingR (4) procedure is added to the pre-formation. The metal film (or layer) can be splashed or electro-mineraled on the back side of the first to serve as the first spot Λ < 〇 4 丨The two brothers are glued to the material 106 to obtain a more reasonable demand. 乂1 main heat according to another aspect of the present invention, the present invention also provides another method for 20 200939448 to form a die receiving through hole 205 and conductive A semiconductor 7L package structure 2A for connecting via structures 214. Referring to Figures 7a through 7h, there are shown cross-sectional views of a method of forming a semiconductor device package structure 200 in accordance with another embodiment of the present invention. The step of forming the semiconductor device package structure 200 includes providing a substrate having a die receiving via 205, a conductive connection via structure 214, a first contact pad 2 = ❹ 1 on its face, and a second contact pad 215 on a lower surface thereof. As shown in Figure 7a, 'Substrate 2〇2 Bonding to the above-mentioned die re-worker, in other words, the 'active surface of the base #反〇2〇2 (for soldering and splicing) is adhered to the grain redistribution by I7 1丨 patterned adhesive (not shown) In the figure, b, the first grain 204 has a first bonding pad 208 formed on the t-plane of the first die, and the first adhesive material 206 (which may be selected as a adhesive film) is formed on the tool. On the back side of the first die 2〇4, the s-grain 204 is placed on the back side of the first die 204 by picking and placing the precision alignment tool on the 刀ιΛη L t The patterned adhesive is tightly adhered to the grain resurfacing tool 300 by the drawing / 曰 恻 并 : : : 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Connected to the first contact pad 213. / to make the first bonding pass as shown in the seventh d, with the German, the first day of the day granule 222 is formed on the die, and then formed in the first Above the die 2〇4, the bond is 2G8. The second die 222 has a grain ==::? 226. Then the 'first-adhesive material=:material 224 is cured. Formed to lightly The first lead is restored. The pad 226 and the first contact pad 21 200939448 213 ° as shown in the seventh f, then the dielectric layer 218 is formed on the active surface and the substrate of the first die 204 and the second die 222 'on the upper surface of the 202' to completely cover the first wire 212 and the second wire 228 and fill the space between the edge of the die and the sidewall of the die receiving via 205 as the second adhesive material 207, and thereafter The dielectric layer 218 is cured. As shown in the seventh g, subsequently, after the package structure is separated from the die redistribution tool 300 by separating the patterned adhesive, the back side of the substrate 202 and the first one are cleaned. Adhesive material 206 (to remove residual patterned adhesive). Alternatively, the terminal contact pads are formed over the second contact pads 215 by printing solder paste (or solder balls). A plurality of conductive bumps 22 are selectively formed and coupled to the second contact pads 215. Thereafter, the semiconductor device package structure 200 is adhered to a film 302 for grain division. A metal or conductive layer 210 is selectively formed on the sidewalls of the die receiving vias 205 in the substrate 2A, which are preformed as described above. Another process step for forming the first adhesive material 206 includes seed metal sputtering, patterning, electroplating (copper), photoresist removal, metal wet etching, etc. to form a metal layer.乂 As shown in the seventh h diagram, in one embodiment, a conventional cutting blade 232 is utilized in the grain division. During the segmentation process, the dicing blade 232 is aligned with the dicing line 23 to align the dies (the semiconductor elements are singulated to separate the individual dies. In one embodiment, the steps of forming the conductive bumps 12 〇 and 22 由 are by infrared reflow ( The implementation of the IRrefl〇w) method. ', the bad 22 200939448 The skilled person in the art should note that the material discs described herein are arranged to describe the invention 'and not to limit the invention. The configuration can be adjusted according to the needs of different situations. Descending the invention - the embodiment provides a semiconductor component package with a connection hole and a conductive connection via structure, and the basin Z provides - ultrathin The package structure has a thickness smaller than the package size slightly larger than the grain size. Furthermore, the present invention provides a good = ❹ = case for peripheral applications. The present invention provides a package; and the method can improve reliability Degree and good structure, coffee can also reduce the cost of the material and simple process of the multi-grain junction = cost. It is the problem that the package structure and its method can provide the prior art =:=: decision=. The method can be implemented Use, and "implement and adjust to other phases=this seems to be (4) read fortune, the upper (4) application of the invention is not intended to limit the invention. Its patent protection model = art does not leave this patent In the spirit or scope, the equivalent change in the spirit of the present invention can be understood by the following description of several preferred embodiments and detailed descriptions of 23 200939448 and the following figures. The preferred embodiment of the present invention is intended to be illustrative and not to limit the scope of the present application, wherein: x % • The first a diagram is implemented in accordance with one of the present invention A cross-sectional view of a semiconductor element sealing structure (wire bonding type), and a first cross-sectional view of a semiconductor element sealing structure according to an embodiment of the present invention (redistributed layer type). x ❹ Second a BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view showing a semiconductor device package according to another embodiment of the present invention. A second cross-sectional view of a semiconductor device package according to another embodiment of the present invention. A cross-sectional view of a semiconductor device package structure according to another embodiment of the present invention (wire bonding type). A third b diagram is a cross-sectional view of a semiconductor device package structure according to another embodiment of the present invention (redistribution layer) The fourth figure is a bottom view of a semiconductor element structure according to an embodiment of the present invention. The fifth figure is a top view of a semiconductor element structure according to an embodiment of the present invention. σ semi-conducting diagram is a cross-sectional view of a method of forming a bob-conductor encapsulation structure in accordance with an embodiment of the present invention. The formation of a + conductor is packaged according to another embodiment of the present invention. Schematic diagram of the cross-section of the structure method. [Main component symbol description] 24 200939448 100 semiconductor device package structure 102 substrate 104 first die 105 die receiving via 106 first adhesive material 107 second adhesive material 108 first bond pad 110 Metal or conductive layer 第一 112 first wire 113 first contact pad 114 conductive connection via structure 115 second contact 塾 118 dielectric layer 118a dielectric layer 118b dielectric layer 118 c dielectric layer® 1 19 protective substrate 119a adhesive layer 120 conductive bump 122 second die 124 die attach material 126 second bond pad 128 second wire 150 metal layer 200 semiconductor device package structure 202 substrate 204 first die 205 die receiving pass Hole 206 first adhesive material 207 second adhesive material 208 first bond 塾 210 metal or conductive layer 212 first wire 213 first contact pad 214 conductive connection via structure 215 second contact pad 218 dielectric layer 218 a dielectric layer 218b dielectric layer 218c dielectric layer 219 protects substrate 219a adhesive layer 220 conductive bump 222 second die 224 die attach material 226 second bond pad 228 second wire 230 cut line 25 200939448 232 cutting blade 302 film 300 Grain resurfacing tool
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