TWI394260B - Semiconductor device package structure with multi-chips and method of the same - Google Patents

Description

Semiconductor component package structure with multi-die and method thereof

The present invention relates to a semiconductor device package structure, and more particularly to a semiconductor device package structure having a multi-die and a method thereof, which can reduce package size and improve yield and reliability.

In recent years, high-tech electronics manufacturing has introduced more characteristic and more humane electronic products. The rapid growth of semiconductor technology has led to rapid progress in semiconductor package size, multi-pin, fine pitch, and shrinking of electronic components. The purpose and advantages of wafer level packaging include reducing production costs and reducing the effects of parasitic capacitance and parasitic inductance by using a shorter wire path to achieve better noise ratio (ie, signal to noise ratio).

Such techniques are time consuming for manufacturing processes because conventional packaging techniques must divide the dies on the wafer into individual dies and then package the dies separately. Since the chip packaging technology is greatly affected by the development of the integrated circuit, when the size of the electronic device becomes high, the packaging technology is also the same. For the above reasons, the trend of packaging technology is toward today's solder ball array (BGA), flip chip package (Crystal Tin Ball Array (FC-BGA)), chip size package (CSP), wafer level package (WLP). . Wafer Level Packaging (WLP) is understood to be performed on the entire package on the wafer, all interconnects, and other process steps before being split into dies. In general, after completing all assembly or packaging processes, a separate semiconductor package is separated from a wafer having a plurality of semiconductor dies. This wafer-level package is extremely small and combines excellent electrical characteristics.

In the manufacturing method, the wafer level wafer size package (WLCSP) technology is an advanced packaging technology, which is fabricated and tested by the die on the wafer, and then separated by cutting for use in the surface bonding production line. In the assembly. Because wafer-level packaging technology uses the entire wafer as a target rather than a single wafer or die, packaging and testing are done before the segmentation process. In addition, wafer level packaging (WLP) is such an advanced technology that the procedures for wire bonding, die attach and underfill can be ignored. By using wafer-level packaging technology, the cost and manufacturing time can be reduced and the final structure size of the wafer-level package can be equivalent to the die size, so the technology can meet the miniaturization requirements of electronic devices. Furthermore, Wafer Level Wafer Size Package (WLCSP) has the advantage of being able to print a redistribution circuit directly on the die by utilizing the peripheral region of the die as a junction. This is achieved by redistributing an array of regions on the surface of the die, making it possible to fully utilize the monolithic regions of the die. The junction is located on the redistribution circuit by forming a flip chip, so that the bottom side of the die is directly connected to a printed circuit board (PCB) having micro-separation junctions.

Although wafer level wafer size packaging (WLCSP) can greatly reduce signal path distance, it is still very difficult to accommodate all joints on the die surface when the integration of the die and internal components is higher. When the degree of integration is higher, the number of pins on the die increases, so the weight distribution of the pins in the area array is difficult to achieve. Even if the pin redistribution is successful, the distance between the pins will be too small to match the printed circuit board (PCB) spacing. That is, due to the large package size, such prior art procedures and structures suffer from problems of yield and reliability. Another disadvantage of prior art methods is higher cost and manufacturing time consuming.

Although wafer-level packaging technology has the above advantages, there are still some problems that affect the acceptance of wafer-level packaging technology. For example, the difference in thermal expansion coefficient between the material of the wafer level package structure and the printed circuit board (PCB) becomes another key factor that causes mechanical instability of the structure. The packaging scheme disclosed in U.S. Patent Application No. 6,271,469 suffers from a problem of mismatch in thermal expansion coefficients. This is due to the prior art utilizing the ruthenium grains wrapped by the molding mixture. As is well known in the art, the thermal expansion coefficient of the tantalum material is 2.3, whereas the coefficient of thermal expansion of the molded mixture is about 20 to 80. Since the curing temperature of the mixture and the dielectric layer material is high, this configuration causes the grain position to shift during the process, and the interconnect pads are also offset, causing yield and performance problems. It is difficult to return to the original position during the temperature cycle (if the curing temperature is adjacent to or above the glass transition temperature (Tg), it is caused by the characteristics of the epoxy resin). It means that the previous structural package cannot be manufactured in a large size and causes a high manufacturing cost.

Furthermore, several techniques involve the use of grains formed directly on the upper surface of the substrate. As is well known in the art, the pads formed on the semiconductor die are redistributed into a plurality of metal pads in the form of a regional array through a conventional redistribution process involving the redistribution layer (RDL). The laminate will increase the size of the package. Therefore, the thickness of the package will increase. It may be inconsistent with the need to reduce wafer size.

Furthermore, prior art has been plagued by the need for complex processes to form a plate package. It requires a molding tool for wrapping and injecting molding materials. Since the mixture deforms after heat curing, it is impossible to control the grain surface to be at the same level as the mixture, so a chemical mechanical polishing (CMP) procedure is required to plan the uneven surface. The cost is therefore increased.

In view of the above, the present invention provides a novel multi-die structure and method thereof for use in a panel scale package (PSP) to overcome the above problems.

The invention will be described in terms of several preferred embodiments. However, it will be appreciated by those skilled in the art that the present invention may be widely practiced in other embodiments. The scope of the present invention is not limited by such embodiments and should be determined by the scope of the following claims.

It is an object of the present invention to provide a semiconductor device package structure and method thereof that can provide a novel ultra-thin package structure having stacked dies.

Another object of the present invention is to provide a semiconductor device package structure and method thereof, which can provide better reliability since the substrate and the printed circuit board have the same thermal expansion coefficient.

Still another object of the present invention is to provide a semiconductor device package structure and method thereof, which can provide a simple process for forming a semiconductor device package.

Still another object of the present invention is to provide a semiconductor device package structure and method thereof which can reduce cost and improve yield.

Another object of the present invention is to provide a semiconductor device package structure and method thereof that provide a good low pin count component solution.

The present invention provides a semiconductor device package structure including a substrate having at least one die receiving via and a conductive via structure, and the first contact on the upper surface of the substrate through the conductive via structure The pad is coupled to the second contact pad on the lower surface of the substrate; at least one first die having a first bonding pad and disposed in the die receiving via; the first adhesive material formed on the Under the first die; a second adhesive material filled in the space between the first die and the sidewall of the die receiving via of the substrate; the first wire is formed to couple the first a bonding pad and the first contact pad; at least one second die having a second bonding pad attached to the first die; and a die attaching material formed under the second die; a second wire formed to couple the second bonding pad and the first contact pad; and a plurality of dielectric layers formed on the first and second wires, the first and second dies, and the substrate .

The present invention provides a method for forming a semiconductor device package, comprising: providing a substrate having at least one die receiving via and a conductive connection via structure, wherein the substrate passes through the conductive connection via structure and the upper surface of the substrate The first contact pad is coupled to the second contact pad on the lower surface of the substrate; the patterned adhesive is printed on the die re-wiring tool; and the substrate is bonded to the die re-wiping tool by the patterned adhesive Relocating at least one first die having a first bond pad to the die re-wiring tool by a pick and place precision alignment system to have a desired spacing and to have an active face of the first die The patterned adhesive is tightly adhered; the first adhesive material is formed on the back side of the first die (which can be implemented as a wafer before cutting); and the second adhesive material is filled into the first die The edge is spaced from the die receiving via of the substrate; and the package structure (or the plate wafer, meaning the substrate having the embedded die and the adhesive material) is separated from the die by separating the patterned adhesive weight Separating the cloth tool; forming a first wire to connect the first bonding pad to the first contact pad; attaching and placing at least one second die having the second bonding pad to the first crystal by using a die attach material On the granules (the die attach material may be applied to the wafer in the form of a wafer or after the first conductive wire is formed to print the die attach material on the first die); forming a second wire to connect the second bonding pad and the above a first contact pad; connecting the first contact pad to the second contact pad by a conductive connection via structure (preformed in the substrate); forming a plurality of dielectric layers on the wire, the first and second die And the upper surface of the substrate; and the above-mentioned package structure (plate type) is adhered to the film and cut to form independent crystal grains. It can perform final testing and/or burn-in procedures in the form of plate wafers prior to dicing the dies.

The present invention provides a method for forming a semiconductor device package, comprising: providing a substrate having at least one die receiving via and a conductive connection via structure, wherein the substrate passes through the conductive connection via structure and the upper surface of the substrate The first contact pad is coupled to the second contact pad on the lower surface of the substrate; the patterned adhesive is printed on the die re-wiring tool; and the substrate is bonded to the die re-wiping tool by the patterned adhesive Relocating at least one first die having a first bonding pad to the die re-wiring tool by picking and placing a precision alignment system, such that the back side of the first die is adhered by the patterning Bonding and having a desired distance between the die receiving vias; forming a first wire to connect the first bonding pad to the first contact pad; and having at least one second die having a second bonding pad Laying/attaching to the first die (adhesive film/material attached to the back side of the second die); forming a second wire to couple the second bonding pad and the first contact pad; forming a dielectric Layer on The active surface of the first and second crystal grains and the upper surface of the substrate and filled in the space between the edge of the first die and the sidewall of the die receiving via of the substrate; by separating the pattern The adhesive separates the package structure (or a plate-type structure, meaning a substrate having a die and an adhesive material, that is, a dielectric layer herein) from the die-removing tool; and attaching the package structure (plate type) to the glue The film is cut and formed to form individual crystal grains (semiconductor elements).

In the following description, the specific embodiments of the present invention invention. However, it will be appreciated by those skilled in the art that the present invention may be practiced without one or more specific details or may be implemented in other methods, components, and materials.

Referring to a first diagram and a first diagram, a cross-sectional view of a semiconductor device package structure 100 in accordance with an embodiment of the present invention is shown. The semiconductor device package structure 100 includes a substrate 102 , a first die 104 , a die receiving via 105 , a first adhesive material 106 , a second adhesive material 107 , a first bonding pad 108 , a metal or conductive layer 110 , and a first conductive line 112 . a first contact pad 113, a conductive connection via structure 114, a second contact pad 115, a second die 122, a second bond pad 126, a die attach material 124, a second wire 128, a dielectric layer 118, and a plurality of conductive Bumps 120. The first b-picture shows a plurality of dielectric layers 118a, 118b, and 118c formed using a stacked structure and method.

In the first a diagram and the first b diagram, the substrate 102 has a die receiving via 105 formed therein to receive the first die 104. The die receiving via 105 is formed from the upper surface of the substrate 102 and penetrates the substrate 102 to the lower surface of the substrate 102. The die receiving vias 105 are formed in advance in the substrate 102. The first adhesive material 106 is coated (adhered) under the lower surface of the first die 104, which can be implemented as a germanium wafer prior to the dicing separation, thereby sealing the first die 104. The second adhesive material 107 is also refilled in the space between the edge of the first die 104 and the sidewall of the die receiving via 105. Both the first adhesive material 106 and the second adhesive material 107 can utilize the same material.

The substrate 102 also includes a conductive connection via structure 114 formed therein. The first contact pad 113 and the second contact pad 115 (for the organic substrate) are respectively formed on the upper surface and the lower surface of the conductive connection via structure 114 and on the upper surface and the lower surface of the portion of the substrate 102. The electrically conductive material is refilled into the electrically conductive connection via structure 114 for electrical connection. This is a pre-formation procedure when the substrate 102 is manufactured.

The metal or conductive layer 110 is selectively coated (by sputtering or electro-less plating) on the sidewall of the die receiving via 105, that is, the metal or conductive layer 110 is formed by the first The first die 104 surrounded by the second adhesive material 107 and the substrate 102. The adhesion strength between the edge of the die and the sidewall of the die receiving via 105 of the substrate 102 can be improved by utilizing a plurality of special adhesive materials, particularly rubber type adhesive materials.

The first die 104 is disposed in the die receiving via 105 in the substrate 102. As is well known to those skilled in the art, the first bond pads 108 are formed in the upper surface of the first die 104. The first wire 112 is formed to couple the first bond pad 108 and the first contact pad 113. The first wire 112 can be implemented in wire bonding or stack redistribution for electrical connection.

The present invention also includes a second die 122 formed on the die attach material 124 and then placed/attached to the active face of the first die 104 (or placed/attached to the dielectric layer when utilizing the buildup structure) ). In other words, the second die 122 is placed/attached over the first die 104 to expose the first bond pad 108 for electrical connection (if wire bonding is used). The second die 122 has a plurality of second bonding pads 126 formed on the upper surface of the second die 122. The second wire 128 is formed to couple the second bond pad 126 and the first contact pad 113 (which may be a bond wire or a laminate structure). Next, the dielectric layer 118 is formed to cover the first wire 112, the second wire 128, the upper surface of the first die 104 and the second die 122, and the substrate 102. When utilizing a laminate structure and method, the dielectric layer can be a plurality of dielectric layer structures 118a, 118b, 118c, as shown in the first b-figure.

A buildup (redistribution layer (RDL)) structure and its programming are selectively implemented on the underside of the substrate coated with the wafer to couple the second contact pad to the termination pad. The termination pad structure can be in the form of a solder ball array (BGA) or a planar gate grid array (LGA).

Thereafter, the plurality of conductive bumps 120 are formed by printing a solder paste (or a solder ball) on the surface and coupled to the termination pad. Subsequently, a reflow process is performed to return the solder paste. Therefore, the first die 104 and the second die 122 are electrically connected to the conductive bumps 120 through the conductive connection via structures 114 , the first wires 112 , and the second wires 128 .

The protective substrate 119 is utilized to prevent the package from being subjected to forces that may damage the package. It includes an adhesive layer 119a to adhere the dielectric layer 118 and the protective substrate 119. The top dielectric layer 118c can also be used as the adhesive layer 119a if it is sufficiently viscous. Since the second adhesive material 107 has elastic (elongation) characteristics, the metal or conductive layer 110 and the second adhesive material 107 serve as a buffer region that absorbs thermomechanical stress between the first die 104 and the substrate 102 during temperature cycling. . The above structure constitutes a planar gate grid array (LGA) package (surrounding type).

In one embodiment, the material of the substrate 102 comprises an epoxy type high temperature resistant glass fiber board (FR5), a glass fiber board (FR4), a polybenzamine (PI) or a double maleammine triazole having a glass fiber inside. Benzene resin (BT). The material of the substrate 102 can also be metal, alloy, glass, germanium, ceramic or printed circuit board (PCB). The alloy also contains a nickel-iron alloy (Alloy 42) (42% nickel - 58% iron) or a Kover alloy (29% nickel - 17% cobalt - 54% iron). Furthermore, the alloy is preferably composed of a nickel-iron alloy (Alloy 42), which is a nickel-iron alloy, and its expansion coefficient makes it suitable for adding a germanium wafer in a microelectronic circuit, which is composed of 42% nickel and 58%. The composition of the iron. The alloy may also consist of Kover, which consists of 29% nickel, 17% cobalt, and 54% iron.

The material of the substrate 102 is preferably an organic substrate, such as an epoxy type high temperature resistant glass fiber board (FR5) having a defined through hole, polyimide (PI), and bismaleimide triazabenzene resin (BT). Or a printed circuit board (PCB), or a copper metal layer with a pre-etched circuit. The coefficient of thermal expansion (CTE) is preferably the same as that of a printed circuit board (PCB). Since the thermal expansion coefficient (CTE) of the substrate 102 matches the thermal expansion coefficient (CTE) of a printed circuit board (PCB) or a mother board, the present invention can provide a structure with better reliability. The organic substrate having a high glass transition temperature (Tg) is preferably an epoxy type high temperature resistant glass fiber board (FR5) or a bismaleimide triazine resin (BT) type substrate. Copper metal (a thermal expansion coefficient of about 16) can also be utilized. Glass, ceramics, and tantalum can also be utilized as a substrate. The second adhesive material 107 is preferably formed of a silicone elastic material, and an epoxy resin may also be used.

In one embodiment, the materials of the first adhesive material 106 and the second adhesive material 107 comprise an ultraviolet (UV) curing type and a heat curing type material, an epoxy resin or a rubber type material. The material of the first adhesive material 106 may also comprise a metallic material. Furthermore, when wire bonding is used, the material of the dielectric layer 118 includes a liquid compound, a resin, a silicone, and when a laminated structure is used, the material of the dielectric layer 118 contains benzocyclobutene (BCB), A siloxane polymer (SINR) or polyamidamine (PI).

In one embodiment, the material of the protective substrate 119 includes, but is not limited to, a high temperature resistant glass fiber board (FR5), a glass fiber board (FR4), a polybenzamine (PI), or a bismaleimine trinitrogen having a glass fiber inside. Heterobenzene resin (BT) or metal. A protective substrate 119 can be attached to the top of the dielectric layer 118 to protect the package, and the protective substrate 119 can also be marked on top of it by a laser program.

In one embodiment, the material of the die attach material 124 includes, but is not limited to, an elastomeric material. The die attach material 124, such as an adhesive tape, has internal spaces therein as buffer regions for absorbing thermal mechanical means between the first die 104 and the second die 122 during temperature cycling and during thermal curing. stress.

Referring to FIG. 2A, it is a cross-sectional view of a semiconductor device package structure 200 in accordance with another embodiment of the present invention. The substrate 202 includes conductive connection via structures 214 formed on four sides of the substrate 202, that is, the conductive connection via structures 214 are formed on both sides (four-terminal sides) of the substrate 202, respectively. The first contact pad 213 and the second contact pad 215 are respectively formed on the upper surface and the lower surface of the conductive connection via structure 214 and a portion of the upper surface and the lower surface of the substrate 202. The electrically conductive material is refilled into the electrically conductive connection via structure 214 for electrical connection. After the segmentation is completed, each individual package shares half of the conductive connection via structure.

In addition, the semiconductor device package structure 200 includes a second die 222 having a plurality of second bonding pads 226 formed on an upper surface of the second die 222. The second die 222 is formed on the die attach material 224, and then the second die 222 is placed/attached to the active surface of the first die 204. If a wiring is used instead of forming a wire, the second die 222 Attached to the first laminate of the first die). In other words, the second die 222 is placed on the first die 204 to expose the first bond pad 208 for electrical connection (if wire bonding is used). The second wire 228 is formed to couple the second bond pad 226 and the first contact pad 213. Next, a buildup layer (redistribution layer (RDL)) is formed on the underside of the substrate coated with the die to couple the second contact pad 215 and the termination pad, and the plurality of conductive bumps 220 are coupled to the termination pad . Therefore, the first bonding pad 208 formed in the first die 204 and the second bonding pad 226 formed in the second die 222 can be electrically connected to the via structure 214, the first wire 212 and the second wire. 228 is electrically connected to the conductive bumps 220.

A metal or conductive layer 210 is selectively applied to sidewalls of the die receiving vias 205, that is, a metal or conductive layer 210 is formed between the first die 204 and the substrate 202 surrounded by the second adhesive material 207. .

Further, as shown in the first and second figures, a plurality of elements in the semiconductor element package structure 200 are similar to those in the semiconductor element package structure 100, and a detailed description thereof will be omitted.

Second b is a cross-sectional view showing the structure of a semiconductor device package structure 200 according to an embodiment of the present invention. The first contact pad 213 is formed over the conductive connection via structure 214. The electrically conductive connection via structure 214 is located on the area of the dicing line 230. In other words, each of the semiconductor device package structures has half of the conductive connection via structures 214 after dicing (since several regions are cut, the size is actually less than half). The interior of the conductive connection via structure 214 is filled with a conductive material and/or the remaining regions are filled with epoxy. It improves the solder fusion quality during the surface bonding process and also reduces the foot print. Similarly, the structure of the one-half conductive via structure 214 can be formed on the sidewalls of the die receiving vias 205 (not shown), which can replace the metal or conductive layer 210. The conductive connection via structure 214 is also selectively referred to as a connecting trench.

3A and 3B are cross-sectional views of a semiconductor device package structure 200 according to another embodiment of the present invention. An alternate embodiment can be viewed in the third a and third b images. The semiconductor device package structure 200 can be formed without forming the conductive bumps 220 on the second contact pads 215. The other components are similar to those of the first a diagram and the first b diagram, and detailed description thereof will be omitted.

The thickness b from the surface of the dielectric layer 218 to the upper surface of the substrate 202 is preferably about 118 to 218 microns. The thickness a from the upper surface to the lower surface of the substrate 202 is preferably about 60 to 150 μm. Thus, the present invention provides an ultra-thin structure having a total thickness of less than 500 microns and a package size of about 0.5 mm to 1 mm per side of the die size for use in a conventional printed circuit board (PCB) process. A wafer size package (CSP) is formed.

Referring to a fourth diagram, there is shown a bottom view of a semiconductor device package structure 100 in accordance with an embodiment of the present invention. The back side of the semiconductor device package structure 100 includes a substrate 102 (the solder mask layer is not shown in the drawing), a second adhesive material 107 formed therein, and a plurality of second contact pads 115 surrounded therearound. As shown in the area outside the dotted line in the figure, the semiconductor device package structure 100 selectively includes a metal layer 150 which is sputtered or plated on the back side of the first die 104 to replace the first adhesive material 106. It can increase the thermal conductivity. The area within the dotted line in the figure indicates the area of the second die 122. The metal layer 150 can be soldered to the printed circuit board (PCB) by solder paste, which can conduct heat (generated from the heat of the die) through the copper metal of the printed circuit board.

Referring to a fifth diagram, there is shown a top view of a semiconductor device package structure 100 in accordance with an embodiment of the present invention. The top side of the semiconductor device package structure 100 includes a substrate 102 and a first die 104 formed on the first adhesive material 106. A plurality of first contact pads 113 are formed around the edge regions of the substrate 102. The first wire 112 is formed to couple the first bond pad 108 with the first contact pad 113. Furthermore, a second die 122 is formed over the first die 104 to expose the first bond pad 108 (when wire bonding is used). The second wire 128 is formed to couple the second bond pad 126 with the first contact pad 113. It should be noted by those skilled in the art that the first wire 112 and the second wire 128 are not visible after the dielectric layer 118 and the protective substrate 119 are formed.

Further, the semiconductor element package structure 100 can be applied to a higher pin count. This embodiment is similar to the fifth figure, and a detailed description thereof will be omitted. Therefore, this peripheral type of invention provides a good low-foot package solution.

According to another aspect of the present invention, the present invention further provides a method for forming a semiconductor device package structure 100 having a plurality of dies, such as a first die 104 and a second die 122. Referring to FIGS. 6a to 6D, which are schematic cross-sectional views of a method for forming the semiconductor device package structure 100. The implementation steps are as follows.

As shown in FIG. 6a, a substrate 102 having a die receiving via 105, a conductive connection via structure 114, a first contact pad 113 on an upper surface thereof, and a second contact pad 115 on a lower surface thereof is first provided, The die receiving vias 105 , the conductive connection via structures 114 , the first contact pads 113 , and the second contact pads 115 are formed in the substrate 102 in advance. A die rework tool 300 having an alignment pattern formed thereon is provided, and a patterned adhesive is printed on the tool (not shown). The substrate 102 is bonded to the above-described crystal grain resurfacing tool 300. As shown in FIG. b, the first die 104 having the first bond pad 108 is redistributed on the die redistribution tool 300 by the pick and place precision alignment system to have a desired spacing and placed in the substrate 102. The die is received in the via 105, and the first die 104 is adhered to the die redistribution tool 300 by the patterned adhesive. That is, the active surface of the first die 104 is adhered to the die redistribution tool 300 by a patterned adhesive (not shown). After the second adhesive material 107 is filled in the space between the first die 104 (side wall) and the first adhesive material 106 on the back side of the first die 104, the first adhesive material 106 and the second adhesive material 107 are continued. Cured. In this application, the first adhesive material 106 and the second adhesive material 107 may be made of the same material. Thereafter, the package structure (in the form of a plate wafer) is separated from the die redistribution tool 300.

After cleaning the first bonding pad 108 and the upper surface of the first contact pad 113 (the patterned adhesive may remain on the upper surface of the first bonding pad 108 and the first contact pad 113), as shown in FIG. The first wire 112 is formed to connect the first bond pad 108 to the first contact pad 113, wherein the wire can be formed by a wire bonding process or a lamination process. The layering process can be implemented on the dielectric layer on the upper surface of the substrate 102 and used to open the first bonding pad, for example, then sputtering a seed metal layer, forming a photoresist to form a wire pattern and plating the metal on the pattern, after which The photoresist is stripped, metal wet etching is performed to form a redistribution layer (RDL) wire, a second dielectric layer is coated or printed, and the like. Subsequently, the second die 122 is formed on the die attach material 124, and then the second die 122 is placed and attached to the first die 104. If the adhesion is strong, the second dielectric layer is available. As an adhesive material). If a wire bonding application is implemented, the second die 122 does not cover the first bond pad 108, so the first bond pad 108 can be exposed for electrical connection. The second die 122 has a second bond pad 126 formed thereon. Next, the second wire 128 is coupled to the second bond pad 126 and the first contact pad 113. The process of the second wire can be the same as the process of the first wire.

Next, as shown in FIG. 4D, the dielectric layer 118 is coated (molded, printed, or spread) and cured on the active surfaces of the first die 104 and the second die 122 and the upper surface of the substrate 102. The first wire 112, the first die 104, the second wire 128, the second die 122, and the substrate 102 are protected. If a laminate process is used to form the wires, a plurality of dielectric layers are used for the lamination process, and the protective substrate 119 is selectively adhered to the dielectric layer by the adhesive layer 119a to protect the package and to be lasered on the top surface. mark. The terminal contact pads are formed on the second contact pads 115 by printing solder paste (or solder balls). The layering process can also be selectively applied to the underlying surface of the substrate coated with the die and the second contact pad can be coupled to the termination pad (the termination pad can be in the form of an array). Next, the plurality of conductive bumps 120 are formed by an IR reflow method and coupled to the second contact pads 115 or the termination pads. Subsequently, the package structure (in the form of a plate wafer) is adhered to a film 302 for use in a die division process. The plate wafer final test or board wafer burn-in procedure can also be implemented prior to package segmentation.

A metal or conductive layer 110 is selectively formed on the sidewalls of the die receiving vias 105 in the substrate 102. The metal can be added to the substrate during the substrate process by electro-less plating or sputtering. A resistance program or the like is formed in advance. The metal film (or layer) may be sputtered or plated on the back side of the first die 104 to serve as the first adhesive material 106 for better heat treatment requirements.

In accordance with another aspect of the present invention, the present invention also provides another method for forming a semiconductor device package structure 200 having die receiving vias 205 and conductive via structures 214. Referring to Figures 7a through 7h, there are shown cross-sectional views of a method of forming a semiconductor device package structure 200 in accordance with another embodiment of the present invention.

The step of forming the semiconductor device package structure 200 includes providing a substrate 202 having a die receiving via 205, a conductive connection via structure 214, a first contact pad 213 on an upper surface thereof, and a second contact pad 215 on a lower surface thereof. As shown in FIG. 7a, the substrate 202 is bonded to the above-described crystal grain resurfacing tool 300. In other words, the active surface of the substrate 202 (for solder fusion) is adhered to the die rework tool 300 by printing a patterned adhesive (not shown). As shown in FIG. 7b, the first die 204 has a first bonding pad 208 formed on the upper surface of the first die 204, and the first adhesive material 206 (which may be an adhesive film) Formed on the back side of the first die 204. The first die 204 is redistributed on the die redistribution tool 300 by the pick and place precision alignment system, so that the back side of the first die 204 is adhered to the die redistribution tool 300 by the patterned adhesive. And make it have the desired distance. As shown in FIG. 7c, thereafter, the first wire 212 is formed to connect the first bond pad 208 to the first contact pad 213.

As shown in FIG. d, subsequently, a second die 222 is formed over the die attach material 224 and then formed over the first die 204 to expose the first bond pad 208. The second die 222 has a second bond pad 226 formed within the second die 222. Next, the first adhesive material 206 and the die attach material 224 are cured. As shown in FIG. 7e, the second wire 228 is formed to couple the second bond pad 226 and the first contact pad 213.

As shown in the seventh f, the dielectric layer 218 is formed on the active surface of the first die 204 and the second die 222 and the upper surface of the substrate 202 to completely cover the first wire 212 and the second wire. 228, and filled into the space between the edge of the die and the sidewall of the die receiving via 205 as the second adhesive material 207, and then the dielectric layer 218 is cured. As shown in the seventh g, subsequently, after the package structure is separated from the die redistribution tool 300 by separating the patterned adhesive, the back side of the substrate 202 and the first adhesive material 206 are cleaned (to remove the residual pattern). Viscose).

In addition, the terminal contact pads are formed on the second contact pads 215 by printing solder paste (or solder balls). A plurality of conductive bumps 220 are selectively formed and coupled to the second contact pads 215. Thereafter, the semiconductor device package structure 200 is adhered to a film 302 for grain division.

A metal or conductive layer 210 is selectively formed on sidewalls of the die receiving vias 205 in the substrate 202, which are preformed as described above. Another process step for forming the first adhesive material 206 includes the steps of seed metal sputtering, patterning, electroplating (copper), photoresist removal, metal wet etching, etc. to form a metal layer.

As shown in the seventh figure h, in one embodiment, a conventional cutting blade 232 is utilized during the die dividing process. The dicing blade 232 is aligned with the dicing line 230 during the singulation process to separate the dies (semiconductor component package) into individual dies.

In one embodiment, the steps of forming the conductive bumps 120 and 220 are performed by an IR reflow method.

It should be noted by those skilled in the art that the materials and structures described herein are used to describe the invention and not to limit the invention. The configuration of materials and structures can be adjusted according to the needs of different conditions.

According to an embodiment of the present invention, the present invention provides a semiconductor device package structure having a die receiving via and a conductive connection via structure, which can provide an ultra-thin package structure having a thickness of less than 500 μm and a package thereof. The size is slightly larger than the grain size. Furthermore, the present invention provides a good low pin count component solution for use in peripheral applications. The present invention provides a simple method of forming a semiconductor device package which can improve reliability and yield. In addition, the present invention further provides a novel multi-die structure with a stacked structure, and thus also minimizes the size of the wafer-sized package structure, and reduces the cost by a lower cost material and a simple process. Therefore, the ultra-thin wafer size package structure and method thereof disclosed by the present invention can provide the effects unpredictable by the prior art and solve the problems of the prior art. The method can be implemented in a wafer or panel type industry and can be implemented and adjusted for other related applications.

The above description of the preferred embodiments is intended to be illustrative of the invention and is not intended to limit the invention. The scope of patent protection is subject to the scope of the patent application and its equivalent fields. Any modification or refinement made by those skilled in the art without departing from the spirit or scope of the present invention is equivalent to the equivalent change or design made in the spirit of the present disclosure, and should be included in the following patent application scope. Inside.

100. . . Semiconductor component package structure

102. . . Substrate

104. . . First grain

105. . . Die receiving through hole

106. . . First adhesive material

107. . . Second adhesive material

108. . . First bond pad

110. . . Metal or conductive layer

112. . . First wire

113. . . First contact pad

114. . . Conductive connection via structure

115. . . Second contact pad

118. . . Dielectric layer

118a. . . Dielectric layer

118b. . . Dielectric layer

118c. . . Dielectric layer

119. . . Protective substrate

119a. . . Adhesive layer

120. . . Conductive bump

122. . . Second grain

124. . . Grain attachment material

126. . . Second bonding pad

128. . . Second wire

150. . . Metal layer

200. . . Semiconductor component package structure

202. . . Substrate

204. . . First grain

205. . . Die receiving through hole

206. . . First adhesive material

207. . . Second adhesive material

208. . . First bond pad

210. . . Metal or conductive layer

212. . . First wire

213. . . First contact pad

214. . . Conductive connection via structure

215. . . Second contact pad

218. . . Dielectric layer

218a. . . Dielectric layer

218b. . . Dielectric layer

218c. . . Dielectric layer

219. . . Protective substrate

219a. . . Adhesive layer

220. . . Conductive bump

222. . . Second grain

224. . . Grain attachment material

226. . . Second bonding pad

228. . . Second wire

230. . . Cutting line

232. . . Cutting blade

300. . . Grain resurfacing tool

302. . . Film

The invention may be understood by the description of the preferred embodiments and the detailed description and the accompanying drawings. However, those skilled in the art should understand that the preferred embodiments of the present invention are intended to be illustrative and not to limit the scope of the invention. A schematic cross-sectional view of the component package structure (wire bonding type).

The first b-ray is a schematic cross-sectional view (redistributed layer type) of a semiconductor device package structure according to an embodiment of the present invention.

The second a is a schematic cross-sectional view of a semiconductor device package structure according to another embodiment of the present invention.

Figure 2b is a cross-sectional view showing a semiconductor device package structure according to another embodiment of the present invention.

The third a diagram is a cross-sectional view (wire bonding type) of a semiconductor device package structure according to another embodiment of the present invention.

The third b-ray is a schematic cross-sectional view (redistributed layer type) of a semiconductor device package structure according to another embodiment of the present invention.

The fourth drawing is a bottom view of a semiconductor element package structure according to an embodiment of the present invention.

The fifth drawing is a top view of a semiconductor device package structure according to an embodiment of the present invention.

6A to 6D are cross-sectional views showing a method of forming a semiconductor device package structure according to an embodiment of the present invention.

7A through 7h are cross-sectional views showing a method of forming a semiconductor device package structure according to another embodiment of the present invention.

100. . . Semiconductor component package structure

102. . . Substrate

104. . . First grain

105. . . Die receiving through hole

106. . . First adhesive material

107. . . Second adhesive material

108. . . First bond pad

110. . . Metal or conductive layer

112. . . First wire

113. . . First contact pad

114. . . Conductive connection via structure

115. . . Second contact pad

118. . . Dielectric layer

119. . . Protective substrate

120. . . Conductive bump

122. . . Second grain

124. . . Grain attachment material

126. . . Second bonding pad

128. . . Second wire

Claims (29)

A semiconductor device package structure comprising: a substrate having at least one die receiving via and a conductive via; and through the conductive via structure and a first contact pad on an upper surface of the substrate a second contact pad on the lower surface of the substrate is coupled; at least one first die having a first bond pad disposed in the die receiving via; a first adhesive material formed on the first a second adhesive material filled in the space between the first die and the sidewall of the die receiving via of the substrate; a first wire formed to couple the first a bonding pad and the first contact pad; at least one second die having a second bonding pad attached to the first die; a die attach material formed under the second die; a second wire formed to couple the second bonding pad and the first contact pad; and a plurality of dielectric layers formed on the first and second wires, the first and second die, and the Above the substrate. The semiconductor device package structure of claim 1, wherein the first and second wires comprise a redistribution layer (RDL) formed on a lower surface of the substrate coated with the die to couple the terminal pad and the Second contact pad. The semiconductor device package structure of claim 2, further comprising a plurality of conductive bumps coupled to the termination pad, wherein the plurality of conductive bumps are electrically connected to the bonding pad through the conductive connection via structure. The semiconductor device package structure of claim 1, further comprising a protective substrate formed on a top surface of the plurality of dielectric layers, wherein the material of the protective substrate comprises a fiberglass board (FR4) and a high temperature resistant fiberglass board (FR5) ), polyamine (PI), bismaleimide triazabenzene resin (BT) or metal. The semiconductor device package structure of claim 1, wherein the die comprises a semiconductor component, a passive component, or an electronic component. The semiconductor device package structure of claim 1, wherein the wires comprise bonding wires and a redistribution layer (RDL), wherein the structure of the redistribution layer is formed in the plurality of dielectric layers. The semiconductor device package structure of claim 1, further comprising a metal or conductive layer formed on a sidewall of the die receiving via of the substrate. The semiconductor device package structure of claim 1, wherein the conductive connection via structure is formed on a side of the substrate (a half via structure). The semiconductor device package structure according to claim 1, wherein the material of the substrate comprises an epoxy type high temperature resistant glass fiber board (FR5)/glass fiber board (FR4), polyamidamine (PI), and bismaleimide. Azabenzene resin (BT), metal, alloy, glass, tantalum, ceramic or printed circuit board (PCB). The semiconductor device package structure of claim 1, wherein the material of the first adhesive material and the second adhesive material comprises an ultraviolet curing type and a heat curing type material, an epoxy resin or a rubber type material, wherein the first adhesive layer The material of the material comprises one of a metal sputtered or plated on the back side of the first die. The semiconductor device package structure of claim 1, wherein the material of the die attach material comprises an elastic material. The semiconductor device package structure according to claim 1, wherein the material of the dielectric layer comprises a liquid compound, a resin, a silicone, a benzocyclobutene (BCB), a siloxane polymer (SINR) or a poly Indoleamine (PI). A method for forming a package of a semiconductor device, comprising: providing a substrate having at least one die receiving via and a conductive via; the substrate passing through the conductive via structure and the first surface on the substrate The contact pad and the second contact pad on the lower surface of the substrate are coupled; the patterned adhesive is printed on the die resurfacing tool; and the substrate is bonded to the die resurfacing tool by the patterned adhesive; Relocating at least one first die having a first bond pad to the die resurfacing tool by the patterned adhesive and pick and place precision alignment system to have a desired spacing; forming a first adhesive The material is on the back side of the first die; a second adhesive material is filled into the space between the edge of the first die and the die receiving via of the substrate; by separating the patterned adhesive Separating the package structure from the die re-wiring tool; forming a first wire to connect the first bond pad to the first contact pad; attaching at least one second die having a second bond pad to the first On the die; forming a second wire to Connecting the second bonding pad and the first contact pad; forming a plurality of dielectric layers on the active surface of the first and second dies and the upper surface of the substrate; and bonding the package structure to a film and It is cut to form individual crystal grains. The method for forming a semiconductor device package according to claim 13, wherein the wires comprise a redistribution layer (RDL) formed on the lower surface of the substrate coated with the die to couple the termination pad and the Second contact pad. The method for forming a semiconductor device package according to claim 14, further comprising the step of fusing a plurality of solder bumps on the termination pad, wherein the step of forming the solder bumps is performed by an infrared reflow method. The method for forming a package of a semiconductor device according to claim 13, further comprising the step of forming a protective substrate on a top surface of the plurality of dielectric layers by an adhesive material. The method for forming a semiconductor device package according to claim 13, wherein the wires comprise a bonding wire or a redistribution layer (RDL), wherein the redistribution layer process comprises forming a dielectric layer, opening a bonding pad, and a contact pad, Sputtering the seed metal layer, performing a photoresist process to form a wire pattern, plating the wire, stripping the photoresist, and etching the seed metal to ultimately form the wire into a redistribution layer. The method for forming a semiconductor device package according to claim 13, further comprising the step of adhering the active surface of the first die to the die re-wiping tool through the printed pattern adhesive. The method for forming a semiconductor device package according to claim 13, further comprising the step of curing the first and second adhesive materials. The method for forming a semiconductor device package according to claim 13, further comprising forming a die attach material under the second die, wherein the material of the die attach material comprises an elastic material. The method for forming a semiconductor device package as described in claim 13, further comprising the step of curing the dielectric layer. The method for forming a semiconductor device package according to claim 13, further comprising the step of forming a metal or conductive layer on a sidewall of the die receiving via of the substrate. The method for forming a semiconductor device package according to claim 13, further comprising the step of cleaning the top surface of the package structure before forming the wire. A method for forming a package of a semiconductor device, comprising: providing a substrate having at least one die receiving via and a conductive via; the substrate passing through the conductive via structure and the first surface on the substrate The contact pad and the second contact pad on the lower surface of the substrate are coupled; the patterned adhesive is printed on the die resurfacing tool; and the substrate is bonded to the die resurfacing tool by the patterned adhesive; Relocating at least one first die having a first bond pad to the die re-wiring tool by picking and placing a precision alignment system, so that the back side of the first die is tightly bonded by the patterned adhesive Having a desired distance therebetween; forming a first wire to connect the first bonding pad to the first contact pad; placing at least one second die having a second bonding pad on the first die; forming a second wire for connecting the second bonding pad and the first contact pad; forming a dielectric layer on the active surface of the first and second die and the upper surface of the substrate and filling the first die The edge of the substrate and the die receiving via of the substrate Of the partition walls; glue patterned by separating the package structure will be separated from the die redistribution tool; and the package is adhered to a film and be cut to form independent grains. The method for forming a semiconductor device package according to claim 24, further comprising the step of fusing the plurality of conductive bumps on the second contact pad, wherein the step of forming the conductive bump is performed by infrared reflow. The method for forming a semiconductor device package as described in claim 24, further comprising the step of curing the dielectric layer. The method for forming a semiconductor device package according to claim 24, further comprising the step of forming a first adhesive material on the back side of the first die. The method for forming a semiconductor device package according to claim 24, further comprising forming a die attach material on the back side of the second die, wherein the material of the die attach material comprises an elastic material. The method for forming a semiconductor device package according to claim 24, further comprising the step of forming a metal layer on a sidewall of the die receiving via of the substrate.