CN104409424B - 一种基于玻璃转接板的叠层封装体及其制备方法 - Google Patents

一种基于玻璃转接板的叠层封装体及其制备方法 Download PDF

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CN104409424B
CN104409424B CN201410818164.5A CN201410818164A CN104409424B CN 104409424 B CN104409424 B CN 104409424B CN 201410818164 A CN201410818164 A CN 201410818164A CN 104409424 B CN104409424 B CN 104409424B
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glass
laminated packaging
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王谆
姜峰
张文奇
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Abstract

本发明公开了一种基于玻璃转接板的叠层封装体及其制备方法，在经过背面减薄和露头的玻璃转接板的上表面堆叠芯片层，同时芯片层的外部和层间填充有密封材料，在密封材料与芯片层的上表面设有钝化层，在玻璃转接板的正面钝化层内嵌有正面布线，在背面钝化层内嵌有背面布线，背面布线与正面布线之间通过穿透玻璃转接板和包封体的金属柱相连。本发明实现了从玻璃转接板上表面到下表面堆叠芯片的直接互连，实现了基于玻璃转接板的叠层封装制作。避免了传统方法使用多层复杂布线工艺来达到上表面和下表面的电性连接、制作成本昂贵和良率低下等问题。

Description

一种基于玻璃转接板的叠层封装体及其制备方法
技术领域
本发明公开了一种基于玻璃转接板的叠层封装体，本发明涉及半导体封装领域。
背景技术
随着人们对电子产品的要求向小型化、多功能、环保型等方向的发展，人们努力寻求将电子系统越做越小，集成度越来越高，功能越做越多、越来越强，由此产生了许多新技术、新材料和新设计，其中叠层芯片封装技术以及系统级封装（System-in-Package，SIP）技术就是这些技术的典型代表。
晶圆级封装以晶圆为加工对象，在晶圆上同时对多个芯片进行封装、测试，最后切割成单个器件，以倒扣焊的方式组装，它使封装尺寸减小至芯片尺寸，是一种先进的超小型封装技术。与传统封装技术不同，传统晶片封装是切割后再封装和测试，封装后尺寸会比原晶片尺寸增加约20%，而晶圆级封装是先在整片晶圆上进行封装和测试，然后再进行划线分割，封装后的体积与IC裸芯片的尺寸几乎相同，进一步促进集成电路封装的小型化发展。
现今，半导体封装产业为了满足各种高密度封装的需求，逐渐发展出各种不同型式的封装构造，比如硅通孔封装、晶圆级封装构造（wafer level package，WLP）、芯片尺寸封装构造（chip scale package，CSP）以及无外引脚封装构造（qua-flat no-leadpackage，QFN）等。由于传统的WLP所实现的芯片间互联都建立在通过多层布线实现芯片间的互联，而同时这些技术也会引入一些其他的问题，比如信号延迟，干扰等。
在公开号为US 2014/0036454 A1的文件中，介绍了一种焊孔阵列(BVA)技术。在新型POP封装中，通过增加PoP的中间层带宽来延迟对TSV的需求。BVA PoP是基于铜线键合的封装堆叠互连技术，能够减少间距，并在PoP周围的堆叠装置中大量的互连。但是该技术同时面临一个问题就是在芯片之间的互连是通过重复制作的引线实现的，该技术会引来一系列的电性能问题和可靠性问题，比如焊接不完全和焊接区域隐裂等问题。
发明内容
本发明的目的之一是克服现有技术中存在的不足，提供一种基于玻璃转接板的叠层封装体。
叠层封装体的结构为，在玻璃转接板的上表面堆叠芯片层，同时所述芯片层的外部和层间填充有密封材料，在密封材料与所述芯片层的上表面设有钝化层，在玻璃转接板的正面钝化层内嵌有正面布线，在背面钝化层内嵌有背面布线，背面布线与正面布线之间通过穿透玻璃转接板和包封体的金属柱实现互连。
上述芯片层可以是一层芯片，也可以是多层堆叠芯片。如果是多层堆叠芯片，则其堆叠方式可以是倒装焊或者正面贴装或者其他常规方式。
进一步，上述金属柱分布在芯片层的外周区域，如在所述外周区域，金属柱的分布呈长方形、方形等四方形形状。
另外，本发明还提供一种基于上述玻璃转接板的叠层封装体的制备方法，其包含以下步骤：
1）制作含有通孔的玻璃转接板，并完成通孔内金属的填充，形成金属柱；
2)进行正面布线层的制作，与金属柱互连；
3)对玻璃转接板的背面实施减薄，并对玻璃进行刻蚀，金属柱露出转接板背面一定高度，并且转接板背面上堆叠一层芯片或者多层芯片时，芯片的顶面低于金属柱的端面或与该端面水平；
4)对上述一层芯片或者多层芯片进行密封，然后露出金属柱和芯片，进行背面布线，使得芯片与金属柱互连。
第3步中的刻蚀可以是干法刻蚀或湿法刻蚀。
第1步中进行金属的填充工艺前，先在通孔内依次完成阻挡层、种子层的沉积。
本发明主要通过干法刻蚀、激光或者喷砂的方法实现玻璃通孔制作，然后填充金属，最后在背面利用干法刻蚀或者湿法刻蚀的方法，露出超高铜柱为特征的工艺方法，以及利用该方法制备的相应叠层封装体。因为利用芯片叠加工艺和密封工艺可以实现基底层与堆叠芯片的一体化微组装，从而实现了从玻璃转接板的上表面到下表面的直接互连，实现了超薄多层封装体的封装制作，避免了传统方法使用多层复杂布线工艺、制作成本昂贵和良率低下等问题。
附图说明
下面结合附图对本发明的具体实施作进一步说明。
图1为在玻璃转接板上完成通孔的制作以及正面布线后的结构示意图；
图2为对玻璃转接板的背面实施减薄、刻蚀，完成芯片层堆叠后的示意图；
图3为完成密封以及背面布线并且互连的结构示意图；
图4为叠层封装体的俯视图。
具体实施方式
本发明提供的一种基于上述玻璃转接板的叠层封装体的制备方法的第一步，是提供一个玻璃转接板1。然后在其上制作通孔，采用的技术可以是湿法刻蚀、干法刻蚀、深反应离子刻蚀或激光刻蚀。通孔的深宽比可以达到10:1，深度在30至300微米范围，直径最小可达到5微米。随后完成通孔内金属的填充，形成金属柱4，填充的方式可以采用常规的电镀填充、化学气象沉积，优选采用电镀填充方式。填充的金属材料可以是铜或钨，优选为铜。如果通孔深度值较小时。以及制备正面布线2和绝缘层3，结束后的结构示意图如图1所示，其中的黑色方框代表一个芯片的面积。
接下来对玻璃转接板的背面实施减薄,减薄的方式采用刻蚀，刻蚀的方式可以是干法刻蚀或湿法刻蚀。之后完成芯片层的堆叠，如图2所示，对玻璃转接板的背面实施减薄，随后对玻璃进行刻蚀，使得金属柱露出转接板背面一定高度，并且转接板背面上堆叠一层芯片6或者多层芯片6时，芯片的顶面低于金属柱的端面或与该端面水平。
图3为完成密封以及背面布线并且互连的结构示意图。
图4为叠层封装体的一个实施例的俯视效果图，金属柱分布在芯片层的外周区域，在该外周区域内，金属柱的分布呈四方形形状。
传统的芯片层与基底层之间的电性连接都是通过锡球、凸点或者金属引线的方式实现的。这些方法制作成本高，而且因为不是一体形成，所以效率低、可靠性差。
在玻璃转接板的上表面堆叠芯片层6，同时芯片层的外部和层间填充有密封材料5，在密封材料与芯片层的上表面设有钝化层7，在玻璃转接板的正面钝化层内嵌有正面布线，在背面钝化层内嵌有背面布线，背面布线与正面布线之间通过穿透玻璃转接板和包封体的金属柱4相连。
对于本领域普通技术人员而言，显然本发明不限于上述示范性实施例的细节，在不背离本发明的精神或基本特征的情况下，也能够以其他的具体形式实现本发明。因此，均应将上述实施例看作是示范性的，而且是非限制性的。

Claims (1)

1.一种基于玻璃转接板的叠层封装体的制备方法，其特征是包含以下步骤：
1）制作含有通孔的玻璃转接板，依次在通孔内完成阻挡层、种子层的沉积，并完成通孔内金属的填充，形成金属柱；
2）进行正面布线层的制作，与金属柱互连；
3）对玻璃转接板的背面实施减薄，并对玻璃进行干法或湿法刻蚀，金属柱露出转接板背面一定高度，并且转接板背面上堆叠一层芯片或多层芯片时，芯片的顶面低于金属柱的端面或与该端面水平；
4）对上述一层芯片或多层芯片进行密封，然后露出金属柱和芯片，进行背面布线，使得芯片与金属柱互连。
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