CN105161451B - 半导体叠层封装方法 - Google Patents

半导体叠层封装方法 Download PDF

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CN105161451B
CN105161451B CN201510460961.5A CN201510460961A CN105161451B CN 105161451 B CN105161451 B CN 105161451B CN 201510460961 A CN201510460961 A CN 201510460961A CN 105161451 B CN105161451 B CN 105161451B
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CN105161451A (zh
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李骏
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Tongfu Microelectronics Co Ltd
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Abstract

本发明提供一种半导体叠层封装方法，包括：A：制作上封装体，B：制作封装有芯片的下封装体，C：将所述上封装体和所述下封装体叠层封装，步骤B包括：S101：提供制作下封装体的金属板；S102：在金属板上表面形成凹坑，下表面形成凸起；S103：将芯片连接在金属板的下表面；S104：用塑封底填料将芯片固定和封装于金属板上形成塑封体；S105：打磨塑封体至露出凸起和芯片的上表面；S106：打磨或者蚀刻金属板下表面以去除凹坑；S107：在步骤S106处理后的塑封体的上表面形成再布线金属层，在再布线金属层上形成第一焊球。本发明提供的封装方法在金属板上形成凸起以作为下封装体的电极，实现芯片在封装体中的上下导通；打磨塑封体减小封装厚度，提高封装密度。

Description

半导体叠层封装方法
技术领域
本发明涉及一种半导体封装方法，尤其涉及一种半导体叠层封装方法。
背景技术
随着半导体制造技术以及立体封装技术的不断发展，电子器件和电子产品对多功能化和微型化的要求越来越高，同时要求芯片的封装尺寸不断减小。为了实现芯片封装的微型化，提高芯片封装的集成度，叠层芯片封装(stacked die package)技术逐渐成为技术发展的主流。
叠层芯片封装技术，又称三维封装技术，具体是在同一个封装体内堆叠至少两个芯片的封装技术。叠层芯片封装技术能够实现半导体器件的大容量、多功能、小尺寸、低成本等技术需求，因此叠层芯片技术近年来得到了蓬勃发展。以使用叠层封装技术的存储器为例，相较于没有使用叠层技术的存储器，采用叠层封装技术的存储器能够拥有两倍以上的存储容量。此外，使用叠层封装技术更可以有效地利用芯片的面积，多应用于大存储空间的U盘、SD卡等方面。
叠层芯片封装技术能够通过多种技术手段来实现，例如打线工艺、硅通孔(through silicon via，简称TSV)技术、或者塑封通孔(through molding via，简称TMV)技术。
例如，硅通孔(TSV)技术，就是在芯片上形成通孔，在通孔侧壁形成金属层再填充导电物质形成通孔效果实现上下连接。该工艺成本高，良品率低，直接在硅片上开口易对芯片造成损伤或是令整片晶元强度减低导致破片等问题，实现难度较大。
又如，塑封通孔(TMV)技术是指在塑封层开口，即塑封后使用激光等方法打通塑封层，填充导电物质，但该工艺在塑封层开口深度方面以及打通塑封层的孔边缘绝缘层方面不易控制。
其余的就是一些先预制可导通材质如凹型架构，进行打磨，打线等工艺用于连接。
通过孔内填充介电质不易形成电极，实现多个封装体封装的芯片在一个整封装体中上下导通的难度较大，且成本较高。
发明内容
在下文中给出关于本发明的简要概述，以便提供关于本发明的某些方面的基本理解。应当理解，这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分，也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
本发明的目的是提供一种半导体叠层封装方法，解决现有封装工艺(例如TSV、TMV等工艺)中形成电极较难，不易实现叠层封装的芯片在一个整体封装中上下导通的问题。
本发明提供了一种半导体叠层封装方法，包括：
A：制作上封装体，
B：制作封装有芯片的下封装体，
C：将所述上封装体和所述下封装体叠层封装，
其中，所述B包括：
S101：提供制作所述下封装体的金属板；
S102：在所述金属板上表面形成凹坑，所述凹坑的的厚度小于所述金属板的厚度；在所述金属板的下表面形成凸起，所述凸起的厚度大于等于待装载芯片的厚度；
S103：将所述待装载的芯片连接在所述金属板的下表面；
S104：用塑封底填料将上述芯片固定和封装于所述金属板上形成塑封体，所述塑封体包覆所述凸起；
S105：打磨所述塑封体至露出所述凸起和所述芯片的上表面；
S106：打磨或者蚀刻所述金属板的下表面以去除凹坑；
S107：在步骤S106处理后的塑封体的上表面形成再布线金属层，在所述再布线金属层上对应所述凸起和所述芯片的布线处形成第一焊球。
本发明提供的一种半导体叠层封装方法，通过在金属板上形成凸起实现互联，解决现有封装技术中通过孔内填充介电质形成电极较难的问题，实现层叠的芯片在一个封装体上下导通；下封装体的芯片通过塑封底填料将芯片固定和封装在金属板上，一次性完成固定和封装两个步骤，减少传统叠层封装中封装体翘曲的问题；同时通过打磨塑封体和去除凹坑高度范围的金属板，减小整个封装体的厚度，封装更加节省空间，实现芯片封装的微型化，提高芯片封装的集成度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明制作封装有芯片的下封装体的流程图；
图2-图7为本发明制作封装有芯片的下封装体的过程示意图；
图8为本发明叠层封装结构示意图。
附图标记：
1-金属板 2-凹坑 3-凸起
4-芯片 5-塑封体 6-再布线金属层
7-第一焊球 8-第二焊球 9-上封装体
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意，为了清楚的目的，附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明提供一种半导体叠层封装方法，包括：
A：制作上封装体，
B：制作封装有芯片的下封装体，
C：将所述上封装体和所述下封装体叠层封装，
其中，如图1所示为制作封装有芯片的下封装体的步骤B包括：
S101：提供制作所述下封装体的金属板；
S102：在所述金属板上表面形成凹坑，所述凹坑的厚度小于所述金属板的厚度；在所述金属板的下表面形成凸起，所述凸起的厚度大于等于待装载芯片的厚度；
S103：将所述待装载的芯片连接在所述金属板的下表面；
S104：用塑封底填料将上述芯片固定和封装于所述金属板上形成塑封体，所述塑封体包覆所述凸起；
S105：打磨上述塑封体至露出所述凸起和所述芯片的上表面；
S106：打磨或者蚀刻所述金属板的下表面以去除凹坑；
S107：在步骤S106处理后的塑封体的上表面形成再布线金属层，在所述再布线金属层上对应所述凸起和所述芯片的布线处形成第一焊球。
上述步骤提供了一种制作封装有芯片的下封装体的方法，如图2-图3所示，实施步骤S101-S103，提供所述金属板1；在所述金属板1上表面形成凹坑2，在金属板2的下表面形成凸起3；将待装载芯片4连接在金属板1的下表面。其中，需要使得凹坑2的厚度小于金属板1的厚度；凸起3的厚度大于等于待装载芯片4的厚度。
可选的，步骤S101中提供的金属板1的材料为具有高导电和高熔点的金属材料，如铜等，例如，金属板1可为铜板，方便后续形成的凸起3以作为下封装体的电极。
可选的，步骤S102通过细针冲压技术在所述金属板1上形成凹坑2与凸起3；且在金属板1上下表面，凹坑2与凸起3的位置上下一一对应。
进一步地，上述步骤S101中金属板1的厚度大于待装载芯片的厚度。本实施例中，将待装载芯片与芯片上凸点的高度合起来称为待装载芯片的厚度。例如，待装载芯片的厚度优选为150um，由于凸起3的厚度不能小于待装载的芯片3的高度150um，并且金属板1上的凹坑2与凸起3一一对应形成，而凹坑2的厚度要小于金属板1的厚度，则凹坑2的厚度对应的不小于150um，为了尽可能的减小封装厚度，可以将金属板1的厚度优选为160～200um，故为了方便后续形成厚度高于待装载芯片的凸起，需要保证步骤S101中提供的金属板的厚度需要大于待装载芯片的厚度。
如图4所示，实施步骤S104，用塑封底填料将芯片4固定和封装于金属板1上形成塑封体5，塑封体5包覆所述凸起3。
可选的，步骤S104中芯片4以塑封底填料固定于金属板1上并且包封在塑封体4内部。芯片的封装采用模塑底部填充技术，将芯片和所述凸起都包在塑封体内部。
上述用于模塑底部填充技术的胶为一种化学胶，主要成分可为环氧树脂，将芯片与金属板以及金属板上的凸起之间的空隙填满，并且包裹所述芯片和凸起，对填充胶进行加热固化，即可达到加固的目的，有保证了焊接工艺的电气安全性。
如图5所示，接着实施步骤S105，打磨上述塑封体至露出凸起3和芯片4的上表面。
这个步骤使得凸起的高度与芯片的厚度相同，塑封底填料与芯片的上表面平齐，露出凸起3和芯片4的上表面，一方面方便后续在凸起和芯片的上表面形成再布线金属层，另一方面减薄了封装体的厚度使得封装更加趋于高密度。
然后实施步骤S106，打磨或者蚀刻图5中金属板1的下表面以去除凹坑4，在一定程度上减薄封装体的厚度。
进一步地，在步骤S106中通过去除凹坑至露出芯片的下表面，形成如图6所示的结构。通过这个步骤，进一步减薄了封装体的厚度使得封装更加趋于高密度。
如图7所示，实施步骤S107，在步骤S106处理后的塑封体的上表面形成再布线金属层6，在再布线金属层6上对应凸起3和芯片4的布线处形成第一焊球7。
通过在步骤S106处理后的塑封体的上表面形成再布线金属层6，接着在再布线金属层6上与凸起3和芯片4的布线处对应的位置形成第一焊球7，这样便于以后焊接于印刷电路板上。
经过上述步骤，封装有芯片的下封装体制作完成，接着进行步骤C：将所述上封装体和所述下封装体叠层封装，需要将上封装体和所述下封装体对接，再进行回流焊接以形成如图8所示的半导体叠层封装结构。如图8所示，本发明实施例中的上封装体9的基板底部优选为金属板,以作为上封装体9的导电连接部位。
进一步地，步骤C包括在步骤S106处理后的塑封体的下表面对应凸起的位置形成第二焊球8；上封装体9导电连接部位通过凸起下表面设置的第二焊球8与下封装体对接，再进行回流焊接形成半导体叠层封装结构，形成如图8所示的叠层封装结构。
可选的，在步骤S106处理后的塑封体的下表面对应凸起的位置形成多个第二焊球与上封装体导线连接部位进行对接。这种凸起的形式作为电极，相比于通过金属凸点的形式作为电极，凸起的下表面的范围较大，可形成多个焊球，进一步增强焊接的强度。
但是本发明上述实施例提供的下封装体，仍然适用于上封装体的下表面有锡球或者锡球加金属凸点的情况，例如，可在上封装体9的金属板的下表面形成第二焊球8；将上封装体9通过第二焊球8与所述下封装体的凸起3所在的位置对接，再进行回流焊接形成半导体叠层封装结构，形成如图8所示的叠层封装结构。
可选的，由于下封装体上凸起所覆盖的范围相比于金属凸点的范围较宽，可以在上封装体9导电连接部位形成多个第二焊球与下封装体的凸起对应的位置进行对接，增强焊接的强度。
图8为本发明叠层封装结构示意图，下封装体通过凸起3和上封装体9实现电互连，并且经过打磨塑封体后所述凸起3的的高度等于所述芯片4的厚度，通过对接和回流焊接处理后，上下封装体结合到一起形成了叠层封装结构。同时，本方案提出的叠层封装为上下两个封装体的连接，根据实际的需要，叠层封装的封装体个数可以根据实际情况决定，可以在上封装体上表面叠层封装更多的芯片封装层，也可以在上封装体与下封装体之间叠层封装更多的芯片封装层，增加叠层封装的结构。
本发明提供的半导体叠层封装方法在制备下封装体的过程中，通过在金属板上制备凹坑，形成凸起，以凸起作为电极，实现上下封装体的连接，解决了TSV、TMV等封装方法中通过孔内填充介电质形成电极较难的问题，同时也解决了锡球互联的体积等限制，方便实现叠层封装的芯片在一个封装体上下导通；下封装体的芯片通过塑封底填料将芯片固定和封装在金属板上，一次性完成固定和封装两个步骤，减少传统叠层封装中封装体翘曲的问题，减少了制造的时间，并且提高了机械稳定性，降低成本，提高可靠性；通过打磨塑封体，以及去除凹坑所在高度范围的金属板，乃至露出芯片的下表面，进一步地减小整个封装体的厚度，使得叠层封装更加高密度。
在本发明的装置和方法等实施例中，显然，各部件或各步骤是可以分解、组合和/或分解后重新组合的。这些分解和/或重新组合应视为本发明的等效方案。同时，在上面对本发明具体实施例的描述中，针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用，与其它实施方式中的特征相组合，或替代其它实施方式中的特征。
应该强调，术语“包括/包含”在本文使用时指特征、要素、步骤或组件的存在，但并不排除一个或更多个其它特征、要素、步骤或组件的存在或附加。
最后应说明的是：虽然以上已经详细说明了本发明及其优点，但是应当理解在不超出由所附的权利要求所限定的本发明的精神和范围的情况下可以进行各种改变、替代和变换。而且，本发明的范围不仅限于说明书所描述的过程、设备、手段、方法和步骤的具体实施例。本领域内的普通技术人员从本发明的公开内容将容易理解，根据本发明可以使用执行与在此所述的相应实施例基本相同的功能或者获得与其基本相同的结果的、现有和将来要被开发的过程、设备、手段、方法或者步骤。因此，所附的权利要求旨在在它们的范围内包括这样的过程、设备、手段、方法或者步骤。

Claims (10)

1.一种半导体叠层封装方法，包括：
A：制作上封装体，
B：制作封装有芯片的下封装体，
C：将所述上封装体和所述下封装体叠层封装，
其特征在于，所述B包括：
S101：提供制作所述下封装体的金属板；
S102：在所述金属板上表面形成凹坑，所述凹坑的厚度小于所述金属板的厚度；在所述金属板的下表面形成凸起，所述凸起的厚度大于等于待装载芯片的厚度；
S103：将所述待装载的芯片连接在所述金属板的下表面；
S104：用塑封底填料将上述芯片固定和封装于所述金属板上形成塑封体，所述塑封体包覆所述凸起；
S105：打磨所述塑封体至露出所述凸起和所述芯片的上表面；
S106：打磨或者蚀刻所述金属板的下表面以去除凹坑；
S107：在步骤S106处理后的塑封体的上表面形成再布线金属层，在所述再布线金属层上对应所述凸起和所述芯片的布线处形成第一焊球。
2.根据权利要求1所述的方法，其特征在于，步骤S106打磨或者蚀刻所述金属板的下表面以去除凹坑，并露出所述芯片的下表面。
3.根据权利要求1或2所述的方法，其特征在于，所述C包括：
在所述步骤S106处理后的塑封体的下表面对应所述凸起的位置形成第二焊球；
上封装体导电连接部位通过所述第二焊球与所述下封装体对接，再进行回流焊接形成半导体叠层封装结构。
4.根据权利要求1或2所述的方法，其特征在于，所述C包括：
在上封装体导电连接部位形成第二焊球；
上封装体通过所述第二焊球与所述下封装体的凸起所在的位置对接，再进行回流焊接形成半导体叠层封装结构。
5.根据权利要求1所述的方法，其特征在于，步骤S101所述金属板为铜板。
6.根据权利要求5所述的方法，其特征在于，步骤S101所述金属板的厚度大于待装载芯片的厚度。
7.根据权利要求5所述的方法，其特征在于，步骤S102通过细针冲压技术在所述金属板上形成凹坑与凸起；
且在所述金属板上，所述凹坑与所述凸起的位置上下一一对应。
8.根据权利要求1所述的方法，其特征在于，步骤S104所述芯片以塑封底填料固定于所述金属板上并且包封在所述塑封体内部。
9.根据权利要求3所述的方法，其特征在于，在所述步骤S106处理后的塑封体的下表面对应凸起的位置形成多个第二焊球与上封装体导线连接部位进行对接。
10.根据权利要求4所述的方法，其特征在于，在所述上封装体导电连接部位形成多个第二焊球与所述下封装体的凸起所在的位置进行对接。
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