CN104081516B - 堆叠型半导体封装及其制造方法 - Google Patents

堆叠型半导体封装及其制造方法 Download PDF

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CN104081516B
CN104081516B CN201280068297.4A CN201280068297A CN104081516B CN 104081516 B CN104081516 B CN 104081516B CN 201280068297 A CN201280068297 A CN 201280068297A CN 104081516 B CN104081516 B CN 104081516B
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semiconductor chip
structure body
chip structure
electrode
semiconductor
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CN104081516A (zh
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权容台
李俊奎
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NEPES
Nepes Co Ltd
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Nepes Co Ltd
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

本发明提供一种堆叠型半导体封装，其堆叠有不同大小的半导体芯片。本发明一个实施例的堆叠型半导体封装包括第一半导体芯片结构体和第二半导体芯片结构体，所述第一半导体芯片结构体包括：第一半导体芯片；第一成型层，包围所述第一半导体芯片；及第一贯通电极，贯通所述第一成型层，与所述第一半导体芯片电连接，所述第二半导体芯片结构体相对于所述第一半导体芯片结构体垂直堆叠，并包括：第二半导体芯片；及第二贯通电极，与所述第一贯通电极电连接，其中，所述第一半导体芯片结构体和所述第二半导体芯片结构体具有相同大小。

Description

堆叠型半导体封装及其制造方法
技术领域
本发明的技术思想涉及一种半导体封装，更详细而言，涉及一种堆叠具有不同大小的半导体芯片的堆叠型半导体封装及其制造方法。
背景技术
最近，半导体元件随着工序技术的微化及功能多样化而使得芯片尺寸减小且输入输出端子数量增加，电极衬垫间距逐渐微小化，而且随着加速多种功能的融合，将多个元件集成到一个封装内的系统级封装技术正在兴起。并且，为了最小化操作噪音以及提高信号速度，系统级封装技术变为能够维持短信号距离的三维堆叠技术方式。另一方面，为了这种技术改善要求以及控制产品价格上升而提高生产率并节省制造成本，引入堆叠多个半导体芯片而构成的堆叠型封装。
为了实现堆叠型封装，优选在一个封装内堆叠的半导体芯片具有相同大小。所堆叠的半导体芯片具有不同大小的情况下，尤其位于下侧的半导体芯片小于位于上侧的半导体芯片的情况下，不容易进行半导体芯片的堆叠。韩国公开专利第2005-0048323号(2005年5月24日公开)中公开有一种堆叠具有不同大小的半导体芯片的半导体封装。所述专利中，在具有相对小的大小的半导体芯片上增加周边区域，从而调整为与相对大的半导体芯片相同的大小。但是，所述周边区域由形成半导体芯片的晶圆来提供，因此具有会减低单位晶圆的半导体芯片产出率，不易适用于各种大小的半导体芯片的局限性。
发明内容
(一)要解决的技术问题
本发明的技术思想欲实现的技术问题为提供一种能够容易堆叠不同大小的半导体芯片的堆叠型半导体封装。
并且，本发明的技术思想欲实现的另一技术问题为提供所述堆叠型半导体封装的制造方法。
(二)技术手段
为了实现上述技术问题，根据本发明技术思想的堆叠型半导体封装包括第一半导体芯片结构体和第二半导体芯片结构体，所述第一半导体芯片结构体包括：第一半导体芯片；第一成型层，包围所述第一半导体芯片；及第一贯通电极，贯通所述第一成型层，与所述第一半导体芯片电连接，所述第二半导体芯片结构体相对于所述第一半导体芯片结构体垂直堆叠，并包括：第二半导体芯片；及第二贯通电极，与所述第一贯通电极电连接，其中，所述第一半导体芯片结构体和所述第二半导体芯片结构体可以具有相同大小。
所述第一成型层的至少一侧大小可与所述第二半导体芯片结构体的至少一侧的大小相同。
所述第一半导体芯片的一侧大小可与所述第二半导体芯片的一侧的大小相同。
所述第一半导体芯片结构体可以以位于所述第二半导体芯片结构体上侧的方式堆叠。
所述第二半导体芯片结构体可以以位于所述第一半导体芯片结构体上侧的方式堆叠。
所述第一半导体芯片的活性面可以面对(facing)所述第二半导体芯片地设置。
所述第一半导体芯片的活性面可以与所述第二半导体芯片相对(opposite)地设置。
所述第一贯通电极和所述第二贯通电极可位于同一位置。
所述第一半导体芯片包括第一芯片衬垫，所述第一半导体芯片结构体可进一步包括重新布线图案，所述重新布线图案将所述第一半导体芯片的所述第一芯片衬垫和所述第一贯通电极电连接，形成于所述第一成型层上。
所述第二半导体芯片结构体可进一步包括包围所述第二半导体芯片的第二成型层。
所述堆叠型半导体封装进一步包括第三半导体芯片结构体，所述第三半导体芯片结构体相对于所述第一半导体芯片结构体或所述第二半导体芯片结构体垂直堆叠，所述第三半导体芯片结构体可与所述第一半导体芯片结构体及所述第二半导体芯片结构体中的至少一个具有相同的大小。
所述第三半导体芯片结构体可包括：第三半导体芯片；第三成型层，包围所述第三半导体芯片；及第三贯通电极，贯通所述第三成型层。
所述第三半导体芯片可与所述第一半导体芯片及所述第二半导体芯片中的至少一个具有不同的大小。
本发明另一方面的堆叠型半导体封装的制造方法包括：形成包围第一半导体芯片的第一成型层的步骤；形成贯通所述第一成型层的第一贯通电极的步骤；在所述第一成型层上形成将所述第一贯通电极和所述第一芯片衬垫电连接的重新布线图案，从而形成第一半导体芯片结构体的步骤；在所述第一半导体芯片结构体上堆叠具有第二半导体芯片和第二贯通电极的第二半导体芯片结构体的步骤；以及将所述第一半导体芯片结构体的所述第一贯通电极和所述第二半导体芯片结构体的所述第二贯通电极电连接的步骤，其中，所述第一半导体芯片结构体和所述第二半导体芯片结构体可具有相同的大小。
(三)有益效果
根据本发明技术思想的堆叠型半导体封装，形成包围大小小的半导体芯片的成型层，从而形成与大小大的半导体芯片具有相同大小的半导体芯片结构体，由此能够将堆叠的半导体芯片调整为相同大小。
并且，所述成型层适用于差别化的半导体芯片，因此能够容易地调整具有不同大小的半导体芯片的大小。
并且，无需变更对于具有不同大小的不同种类元件的晶圆设计，能够直接利用来实现堆叠型半导体芯片封装，因此可实现各种应用程序的半导体元件之间的融合。
并且，可以以晶圆级来实现，因此能够提高生产率以及降低制造费用。对于芯片的元件上部或下部堆叠面的方向的设计自由，因此可根据封装的适用领域，实现具可靠性的堆叠结构。将通过芯片的重新布线的板(或者基板)形态作为中介层(介质)基板使用，因此能够容易进行不同种类元件的堆叠。
附图说明
图1是表示本发明一实施例的堆叠型半导体封装的截面图。
图2及图3是本发明一实施例的图1的堆叠型半导体封装中所包括的第一半导体芯片结构体和第二半导体芯片结构体的俯视图。
图4至图13是本发明一实施例的堆叠型半导体封装的截面图。
图14及图15是本发明一实施例的堆叠型半导体封装的截面图
图16至图21是根据工序步骤表示制造本发明一实施例的图1的堆叠型半导体封装的制造方法的截面图。
具体实施方式
以下，参照附图，对本发明的优选实施例进行详细说明。本发明的实施例为了向本领域技术人员更完整地说明本发明的技术思想而提供，下述实施例可变更为多种其它方式，本发明的技术思想不限于下述实施例。相反，实施例是为了使本公开更充实更完善，向本领域技术人员完整地传达技术思想而提供。如本说明书中所使用，术语“和/或”包括所列举的项目中任意一个或一个以上的所有组合。同一附图标记始终表示同一构成要件。并且，示意表示附图的多种构成要件和区域。因此，本发明的技术思想不限于附图中所表示的相对大小或间隔。
图1是表示本发明一实施例的堆叠型半导体封装100的截面图。
参照图1，堆叠型半导体封装100包括基板10、基板10上依次堆叠的第一半导体芯片结构体20和第二半导体芯片结构体30。
基板10例如可以包括印刷电路基板(PCB)、挠性基板、带基板等。基板10可包括玻璃、陶瓷、塑料或者聚合物。基板10还可包括第一半导体芯片结构体20和第二半导体芯片结构体30电连接的基板衬垫12。并且，基板10还可包括将第一半导体芯片结构体20和第二半导体芯片结构体30与外部电连接的外侧连接部件14。外侧连接部件14可与基板衬垫12电连接。外侧连接部件14例如可以为锡球。
第一半导体芯片结构体20可包括第一半导体芯片21、包围第一半导体芯片21的第一成型层22以及贯通第一成型层22并与第一半导体芯片21电连接的第一贯通电极23。
第二半导体芯片结构体30可包括第二半导体芯片31以及与第一贯通电极23电连接的第二贯通电极33。本实施例中，第二半导体芯片结构体30由第二半导体芯片31构成，第二贯通电极33构成为贯通第二半导体芯片31。
第二半导体芯片结构体30可相对于第一半导体芯片结构体20垂直堆叠。本实施例中，第二半导体芯片结构体30堆叠在第一半导体芯片结构体20的上侧。并且，第一半导体芯片结构体20和第二半导体芯片结构体30可具有相同的大小。对此，参照图2及图3，进行详细说明。
第一半导体芯片21和第二半导体芯片31可以为同种产品或者异种产品。例如，第一半导体芯片21和第二半导体芯片31可以是存储器芯片或逻辑芯片。这些存储器芯片可包括例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、闪烁存储器(flash)、相变随机存取存储器(PRAM)、电阻式随机存取存储器(ReRAM)、铁电随机存取存储器(FeRAM)或者磁随机存取存储器(MRAM)。这种逻辑芯片可以是控制存储器芯片的控制器。例如，第一半导体芯片21可以是包括逻辑电路的逻辑芯片，第二半导体芯片31可以是存储器芯片，或者也可以与此相反。堆叠型半导体封装100可以是片上系统(SOC)或者系统级封装(systemin package，SIP)。
第一成型层22可包围第一半导体芯片21。第一成型层22可包括绝缘物，例如可包括环氧模塑化合物(epoxy mold compound，EMC)。第一半导体芯片21从第一成型层22露出，可包括形成有元件(未图示)的活性面21a、嵌入第一成型层22内的非活性面21b及侧面21c。作为替换方案，第一成型层22可包围第一半导体芯片21的侧面21c，露出活性面21a和非活性面21b。堆叠型半导体封装100中，第一半导体芯片21可具有活性面21a朝向上侧露出的面朝上(face-up)结构。第一半导体芯片21的活性面21a可以面对第二半导体芯片31地设置。
第一半导体芯片21可在活性面21a上具有第一芯片衬垫24。第一芯片衬垫24可与形成在第一半导体芯片21上的元件(未图示)电连接。第一芯片衬垫24可与位于第一成型层22上的第一重新布线图案25电连接。第一重新布线图案25可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。第一重新布线图案25可通过衬垫26与第一贯通电极23电连接。即，第一重新布线图案25可电连接第一芯片衬垫24和第一贯通电极23。由此，第一半导体芯片21可通过第一芯片衬垫24、第一重新布线图案25、衬垫26以及第一贯通电极23与基板10电连接。第一贯通电极23和基板10可通过衬垫26和凸点(bump)80电连接。第一半导体芯片21连接于第一重新布线图案25，由此第二半导体芯片20可具有扇出结构。
第二半导体芯片结构体30可通过第二芯片衬垫34和凸点80与基板10电连接。具体而言，第二半导体芯片31可通过第二芯片衬垫34和凸点80与衬垫26连接，接着可通过第一贯通电极23、衬垫26及凸点80与基板10电连接。
并且，第二半导体芯片结构体30可通过第二芯片衬垫34和凸点80与第一半导体芯片结构体20电连接。具体而言，第二半导体芯片31可通过第二芯片衬垫34和凸点80与衬垫26连接，接着可通过第一芯片衬垫24与第一半导体芯片21电连接。
第二半导体芯片31可具有相反的第一面31a和第二面31b。第二半导体芯片31的第一面31a为活性面的情况下，可具有如上所述的电连接关系。相反，第二半导体芯片31的第二面31b为活性面的情况下，形成在所述活性面上的元件(未图示)可通过第二贯通电极33与基板10电连接。
第一贯通电极23和第二贯通电极33可通过凸点80电连接，为此可位于相同位置。在这里，相同位置是指以基板10为基准在一垂直线上配置第一贯通电极23和第二贯通电极33，意味着在平面上位于同一坐标。即，第一贯通电极23和第二贯通电极33的占用面积(foot print)相同。
选择性地，堆叠型半导体芯片100还可包括密封第一半导体芯片结构体20和第二半导体芯片结构体30的外侧密封部件90。外侧密封部件90可包括绝缘物，例如可包括环氧模塑化合物。外侧密封部件90可包含与第一成型层22相同的物质或者不同物质。
并且，第一半导体芯片结构体20上堆叠多个第二半导体芯片结构体30的情况也包括在本发明的技术思想中。
图2及图3是本发明一实施例的图1的堆叠型半导体封装100中所包括的第一半导体芯片结构体20和第二半导体芯片结构体30的俯视图。
参照图2，第一半导体芯片结构体20的第一成型层20的至少一侧大小可与第二半导体芯片结构体30的至少一侧大小相同。
第一半导体芯片结构体20中第一半导体芯片21的第一芯片衬垫24可通过第一重新布线图案25与第一成型层22上的衬垫26电连接。第一半导体芯片21可具有长度L1和宽度W1。长度L1和宽度W1可以相同或者不同。
第一成型层22可包围第一半导体芯片21。第一成型层22可具有比第一半导体芯片21的长度L1大的长度L2和比第一半导体芯片21的宽度W1大的宽度W2。长度L2和宽度W2可以相同或者不同。
第二半导体芯片结构体30可具有长度L3和宽度W3。长度L3和宽度W3可以相同或者不同。本实施例是第二半导体芯片结构体30由第二半导体芯片31构成的情况。
第一成型层22的长度L2可与第二半导体芯片结构体30的长度L3相同，第一成型层22的宽度W2可与第二半导体芯结构体片30的宽度W3相同。由此，第一半导体芯片结构体20和第二半导体芯片结构体30可具有相同的大小。即，第一半导体芯片21具有小于第二半导体芯片31的大小的情况下，形成包围第一半导体芯片21的第一成型层22，由此相互堆叠的第一半导体芯片结构体20和第二半导体芯片结构体30可以以相同的大小构成。
参照图3，第一半导体芯片21的一侧大小可以与第二半导体芯片31的一侧大小相同。并且，第一半导体芯片结构体20的第一成型层22的一侧大小可以与第二半导体芯片结构体30的另一侧大小相同。
第一半导体芯片结构体20可包括具有长度L1的第一半导体芯片21和具有大于长度L1的长度L2的第一成型层22。相反，第一半导体芯片21和第一成型层22的宽度W2可以相同。并且，第二半导体芯片结构体30可具有长度L3和宽度W3。第一成型层22的长度L2可与第二半导体芯片结构体30的长度L3相同，第一成型层22的宽度W2可与第二半导体芯片结构体30的宽度W3相同。
图4至图13是表示本发明一实施例的堆叠型半导体封装200、300、400、500、600、700、800、900、100、1100的截面图。本实施例的堆叠型半导体封装200、300、400、500、600、700、800、900、100、1100是从上述实施例的堆叠型半导体封装变更一部分结构的堆叠型半导体封装，因此省略重复说明。
参照图4，堆叠型半导体封装200包括在基板10上依次堆叠的第一半导体芯片结构体20和第二半导体芯片结构体30。与图1的堆叠型半导体封装100相比，堆叠型半导体封装200是第一半导体芯片21翻覆的情况。堆叠型半导体芯片200中，第一半导体芯片21可具有活性面21a朝向下侧露出的面朝下(face-down)结构。第一半导体芯片21的活性面21a可以与第二半导体芯片31相对地设置。并且，第一半导体芯片结构体20上堆叠多个第二半导体芯片结构体30的情况也包括在本发明的技术思想中。
参照图5，堆叠型半导体封装300包括在基板10上依次堆叠的第二半导体芯片结构体30和第一半导体芯片结构体20。与图1的堆叠型半导体封装100相比，堆叠型半导体封装300是第一半导体芯片结构体20和第二半导体芯片结构体30的堆叠顺序相反的情况。即，第一半导体芯片结构体20可位于第二半导体芯片结构体30的上侧。堆叠型半导体封装300中，第一半导体芯片21可具有活性面21a朝向上侧露出的面朝上结构。第一半导体芯片21的活性面21a可以与第二半导体芯片31相对地设置。
参照图6，堆叠型半导体封装400包括在基板10上依次堆叠的第一半导体芯片结构体20和第二半导体芯片结构体30。与图1的堆叠型半导体封装100相比，堆叠型半导体封装400是第一半导体芯片结构体20和第二半导体芯片结构体30的堆叠顺序相反，且第一半导体芯片21翻覆的情况。堆叠型半导体芯片400中，第一半导体芯片21可具有活性面21a朝向下侧露出的面朝下结构。第一半导体芯片21的活性面21a可以与第二半导体芯片31相对地设置。
图7是表示本发明一实施例的堆叠型半导体封装500的截面图。本实施例的堆叠型半导体封装500是从上述实施例的堆叠型半导体封装变更一部分结构的堆叠型半导体封装，因此省略重复的结构。
参照图7，堆叠型半导体封装500包括第一半导体芯片结构体20和第二半导体芯片结构体30a。第一半导体芯片结构体20可与图1的堆叠型半导体封装100中说明的第一半导体芯片结构体20相同。
第二半导体芯片结构体30a可包括第二半导体芯片31aa和包围第二半导体芯片31aa的第二成型层32。第二成型层32包围第二半导体芯片31aa，第一成型层22包围第一半导体芯片21，由此第二半导体芯片结构体30a可具有与第一半导体芯片结构体20相同的大小。
第二成型层32可包括绝缘物，例如可包括环氧模塑化合物。第二成型层32可包含与第一成型层22相同的物质或者不同物质。
第二半导体芯片31aa可具有第二芯片衬垫34a。第二芯片衬垫34a可与形成在第二半导体芯片31aa的元件(未图示)电连接。第二芯片衬垫34a可与位于第二成型层32上的第二重新布线图案35a电连接。第二重新布线图案35a可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。第二重新布线图案35a可通过衬垫36与第二贯通电极33电连接。即，第二重新布线图案35a可电连接第二芯片衬垫34a和第二贯通电极33。第二贯通电极33可通过第一贯通电极23和凸点80电连接，为此，可位于相同位置。第二半导体芯片31aa连接于第二重新布线图案35a，由此第二半导体芯片30a可具有扇出结构。
与如上所述类似地，第一半导体芯片21和第二半导体芯片31aa的活性面的方向可进行各种变化。
参照图8，堆叠型半导体封装600包括在基板10上依次堆叠的第二半导体芯片结构体30、第一半导体芯片结构体20及第二半导体芯片结构体30。即，在图5的堆叠型半导体封装300上，在第一半导体芯片结构体20上进一步堆叠第二半导体芯片结构体30的情况。第一半导体芯片结构体20上堆叠的第二半导体芯片结构体30可通过第一半导体芯片结构体20的第一贯通电极23与基板10电连接。
参照图9，堆叠型半导体封装700包括在基板10上依次堆叠的第二半导体芯片结构体30、第一半导体芯片结构体20及第二半导体芯片结构体30。即，在图6的堆叠型半导体封装400上，在第一半导体芯片结构体20上进一步堆叠第二半导体芯片结构体30的情况。第一半导体芯片结构体20上堆叠的第二半导体芯片结构体30可通过第一半导体芯片结构体20的第一贯通电极23与基板10电连接。
参照图10，堆叠型半导体封装800包括第一半导体芯片结构体20、第二半导体芯片结构体30以及在第一半导体芯片结构体20的上侧垂直堆叠的第三半导体芯片结构体50。第三半导体芯片结构体50可与第一半导体芯片结构体20及第二半导体芯片结构体30中的至少任意一个具有相同的大小。
第三半导体芯片结构体50可包括第三半导体芯片51、包围第三半导体芯片51的第三成型层52以及贯通第三成型层52且与第三半导体芯片51电连接的第三贯通电极53。
第三半导体芯片51可以为存储器芯片或逻辑芯片。第三半导体芯片51可以与第一半导体芯片21或第二半导体芯片31为同种产品或者异种产品。第三半导体芯片51的大小可以比第一半导体芯片21大，或者小，或者相同。或者第三半导体芯片51的大小可以比第二半导体芯片31大或者小，或者相同。
第三成型层52可包围第三半导体芯片51。第三成型层52可包括绝缘物，例如可包括环氧模塑化合物。第三成型层52可包含与第一成型层22相同的物质或者不同物质。
第三半导体芯片51可具有第三芯片衬垫54。第三芯片衬垫54可与形成在第三半导体芯片51上的元件电连接。第三芯片衬垫54可与位于第三成型层52上的第三重新布线图案55电连接。第三重新布线图案55可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。第三重新布线图案55可通过衬垫56与第三贯通电极53电连接。即，第三重新布线图案55可电连接第三芯片衬垫54和第三贯通电极53。第三贯通电极53可通过第一贯通电极23和凸点80电连接，为此可位于相同位置。第三半导体芯片51连接于第三重新布线图案55，由此第三半导体芯片50可具有扇出结构。
堆叠型半导体封装800中，第一半导体芯片21具有活性面21a朝向上侧露出的面朝上结构，第三半导体芯片51具有活性面51a朝向上侧露出的面朝上结构。
图11至图13示出对堆叠型半导体封装800改变第一半导体芯片21和第三半导体芯片51的活性面的方向的实施例。
参照图11，堆叠型半导体封装900中，第一半导体芯片21具有活性面21a朝向下侧露出的面朝下结构，第三半导体芯片51具有活性面51a朝向下侧露出的面朝下结构。
参照图12，堆叠型半导体封装1000中，第一半导体芯片21具有活性面21a朝向下侧露出的面朝下结构，第三半导体芯片51具有活性面51a朝向上侧露出的面朝上结构。
参照图13，堆叠型半导体封装1100中，第一半导体芯片21具有活性面21a朝向上侧露出的面朝上结构，第三半导体芯片51具有活性面51a朝向下侧露出的面朝下结构。
图14及图15是表示本发明一实施例的堆叠型半导体封装1200、1300的截面图。本实施例的堆叠型半导体封装1200、1300是从上述实施例的堆叠型半导体封装变更一部分结构的堆叠型半导体封装，因此省略重复的结构。
参照图14，堆叠型半导体封装1200包括基板10、在基板10上依次堆叠的第一半导体芯片结构体20和第二半导体芯片结构体30。第一半导体芯片结构体20可包括第四成型层62。因此，第一半导体芯片21可插入到第四成型层62中。第四成型层62可以是预先形成的基板。例如可以是中介层(interposer)。
第四成型层62内部可具有第四贯通电极67，第四贯通电极67可与第一半导体芯片21的第一芯片衬垫24电连接。第四贯通电极67可与第四重新布线图案65电连接，第四重新布线图案65可与第四衬垫66电连接。第四重新布线图案65可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。由此，第一半导体芯片21可通过第四贯通电极67、第四重新布线图案65及第四衬垫66与基板10电连接。并且，第五贯通电极63可执行图1的第二贯通电极33的功能，由此，第二半导体芯片结构体30的第二半导体芯片31可通过第五贯通电极63与基板10电连接。
本实施例中，第一半导体芯片21可具有活性面21a朝向下侧与第四贯通电极67连接的面朝下结构。第四成型层62和第一半导体芯片21的最上表面可以为同一平面，或者也可以不是同一平面。
作为替换方案，第一半导体芯片21可以是仿真芯片(dummy chip)。并且，第四成型层62能够执行对第二半导体芯片结构体30进行重新布线的功能。
参照图15，堆叠型半导体封装1300包括基板10、在基板10上依次堆叠的第一半导体芯片结构体20及第二半导体芯片结构体30。第一半导体芯片结构体20可包括第四成型层62。因此，第一半导体芯片21可插入到第四成型层62内。第四成型层62可以是预先形成的基板。例如可以是中介层。
第四成型层62内部可具有第四贯通电极67，第四贯通电极67可与第一半导体芯片21的第一芯片衬垫24电连接。这里，第一半导体芯片21可具有电连接第四贯通电极67和第一芯片衬垫24的第六贯通电极68。第一半导体芯片21通过第六贯通电极68、第四贯通电极67、第四重新布线图案65及第四衬垫66与基板10电连接。并且，第五贯通电极63可执行图1的第二贯通电极33的功能，由此，第二半导体芯片结构体30的第二半导体芯片31可通过第五贯通电极63与基板10电连接。
本实施例中，第一半导体芯片21可具有活性面21a朝向上侧与第四贯通电极67连接的面朝上结构。第四成型层62和第一半导体芯片21的最上表面可以为同一平面，或者也可以不是同一平面。
作为替换方案，第一半导体芯片21可以是仿真芯片。并且，第四成型层62能够执行对第二半导体芯片结构体30进行重新布线的功能。
图1至图15所示的堆叠型半导体封装中示出堆叠两个或三个半导体芯片结构体的结构，但这是例示，四个或更多数量的半导体芯片结构体堆叠的情况也包括在本发明的技术思想中。
图16至图21是根据工序步骤表示制造本发明一实施例的图1的堆叠型半导体封装的制造方法的截面图。
参照图16，形成分别包围多个第一半导体芯片21的第一成型层22。如上所述，注意配置第一半导体芯片21，以使第一半导体芯片21由第一成型层22包围而构成的个别的第一半导体芯片结构体20(参照图19)的大小与个别的第二半导体芯片结构体30的大小相同(参照图19)。
参照图17，形成贯通第一成型层22的第一贯通电极23。本步骤中，形成贯通第一成型层22的开口部之后，可由导电物填充所述开口部来形成第一贯通电极23。如上所述，注意形成为，第一贯通电极23与第二半导体芯片结构体30(参照图19)的第二贯通电极33(参照图19)位于相同的位置。
参照图18，在第一成型层22上形成电连接第一半导体芯片21和第一贯通电极23的第一重新布线图案25及衬垫26。第一重新布线图案25及衬垫26可利用蒸镀、镀金等多种方法形成。由此，可形成具有多个第一半导体芯片21的第一半导体芯片结构体20。
参照图19，在第一成型层22上堆叠具有第二半导体芯片31和第二贯通电极33的第二半导体芯片结构体30。并且，电连接第一半导体芯片结构体20的第一贯通电极23和第二半导体芯片结构体30的第二贯通电极33。第一贯通电极23和第二贯通电极33的连接可利用回焊工序实现。第一贯通电极23和第二贯通电极33位于相同位置。由此，第一半导体芯片结构体20和第二半导体芯片结构体30可垂直堆叠，第一半导体芯片21和第二半导体芯片31可一对一地对应堆叠。如上所述，第一半导体芯片结构体20和第二半导体芯片结构体30堆叠顺序相反的情况也包括在本发明的技术思想中。
第一半导体芯片结构体20和第二半导体芯片结构体30的堆叠可通过晶圆相互堆叠的晶圆级(wafer level)方式实现。
参照图20，使第一半导体芯片结构体20和第二半导体芯片结构体30的堆叠物差别化。
参照图21，在第一半导体芯片结构体20的下侧粘贴基板10，电连接第一半导体芯片结构体20和基板10。接着，选择性地，形成密封第一半导体芯片结构体20及第二半导体芯片结构体30的外侧密封部件90来完成图1的堆叠型半导体封装100。
以上说明的本发明的技术思想不限于前述实施例以及附图，本发明的技术思想所属技术领域的技术人员明确可知在不脱离本发明的技术思想的范围内可进行各种替换、变形及变更。

Claims (11)

1.一种堆叠型半导体封装，其包括第一半导体芯片结构体和第二半导体芯片结构体，
所述第一半导体芯片结构体包括：第一半导体芯片；第四成型层，包围所述第一半导体芯片；第四贯通电极，贯通所述第四成型层的下部面，与所述第一半导体芯片电连接；第五贯通电极，贯通所述第四成型层，在所述第五贯通电极之间设置所述第一半导体芯片；及第四重新布线图案，形成于所述第四成型层的下部面，对所述第四贯通电极进行重新布线，与所述第五贯通电极电连接，
所述第二半导体芯片结构体相对于所述第一半导体芯片结构体垂直堆叠，并包括：第二半导体芯片；及第二贯通电极，与所述第二半导体芯片电连接，并且与所述第五贯通电极位于同一位置，
其中，所述第一半导体芯片结构体和所述第二半导体芯片结构体具有相同大小。
2.根据权利要求1所述的堆叠型半导体封装，其特征在于，所述第四成型层的至少一侧大小与所述第二半导体芯片结构体的至少一侧的大小相同。
3.根据权利要求1所述的堆叠型半导体封装，其特征在于，所述第一半导体芯片结构体以位于所述第二半导体芯片结构体上侧的方式堆叠。
4.根据权利要求1所述的堆叠型半导体封装，其特征在于，所述第二半导体芯片结构体以位于所述第一半导体芯片结构体上侧的方式堆叠。
5.根据权利要求1所述的堆叠型半导体封装，其特征在于，所述第一半导体芯片的活性面面对所述第二半导体芯片地设置。
6.根据权利要求1所述的堆叠型半导体封装，其特征在于，所述第一半导体芯片的活性面与所述第二半导体芯片相对地设置。
7.根据权利要求1所述的堆叠型半导体封装，其特征在于，所述第一半导体芯片包括第一芯片衬垫，
所述第四贯通电极贯通所述第四成型层，与所述第一芯片衬垫电连接。
8.根据权利要求1所述的堆叠型半导体封装，其特征在于，所述第二半导体芯片结构体进一步包括包围所述第二半导体芯片的第二成型层。
9.根据权利要求1所述的堆叠型半导体封装，其特征在于，进一步包括第三半导体芯片结构体，所述第三半导体芯片结构体相对于所述第一半导体芯片结构体或所述第二半导体芯片结构体垂直堆叠，
所述第三半导体芯片结构体与所述第一半导体芯片结构体及所述第二半导体芯片结构体具有相同的大小。
10.根据权利要求9所述的堆叠型半导体封装，其特征在于，所述第三半导体芯片结构体包括：第三半导体芯片；第三成型层，包围所述第三半导体芯片；及第三贯通电极，与所述第三半导体芯片电连接，在与所述第二贯通电极及第五贯通电极相同位置贯通所述第三成型层。
11.根据权利要求10所述的堆叠型半导体封装，其特征在于，所述第三半导体芯片与所述第一半导体芯片及所述第二半导体芯片中的至少一个具有不同的大小。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11784164B2 (en) 2019-05-31 2023-10-10 Kepler Computing Inc. 3D stacked compute and memory with copper-to-copper hybrid bond
US11829699B1 (en) 2021-08-06 2023-11-28 Kepler Computing Inc. Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576620B (zh) * 2013-10-22 2017-06-20 日月光半导体制造股份有限公司 半导体封装结构与其制造方法
US10128205B2 (en) * 2014-03-06 2018-11-13 Intel Corporation Embedded die flip-chip package assembly
US11024757B2 (en) * 2016-01-15 2021-06-01 Sony Corporation Semiconductor device and imaging apparatus
US9824988B1 (en) 2016-08-11 2017-11-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR102605618B1 (ko) 2016-11-14 2023-11-23 삼성전자주식회사 이미지 센서 패키지
KR102508552B1 (ko) 2018-04-30 2023-03-10 에스케이하이닉스 주식회사 쓰루 몰드 비아를 포함하는 스택 패키지
KR102464066B1 (ko) 2018-04-30 2022-11-07 에스케이하이닉스 주식회사 쓰루 몰드 비아를 포함하는 스택 패키지
US11171115B2 (en) 2019-03-18 2021-11-09 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
US12086410B1 (en) 2019-05-31 2024-09-10 Kepler Computing Inc. Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
CN112490129A (zh) * 2019-09-11 2021-03-12 华邦电子股份有限公司 半导体封装及其制造方法
KR20210096532A (ko) 2020-01-28 2021-08-05 에스케이하이닉스 주식회사 베이스 모듈에 복수의 칩들이 스택된 반도체 패키지
CN111477612B (zh) * 2020-03-23 2022-06-10 中国电子科技集团公司第十三研究所 可调芯片

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893053A (zh) * 2005-07-08 2007-01-10 三星电子株式会社 插件结构及其制造方法、晶片级堆叠结构和封装结构
CN101330068A (zh) * 2007-06-18 2008-12-24 海力士半导体有限公司 模制重配置晶片、使用其的叠置封装及该封装的制造方法
CN101877349A (zh) * 2009-04-30 2010-11-03 三洋电机株式会社 半导体模块及便携式设备

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867501B2 (en) * 2001-11-01 2005-03-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100642746B1 (ko) * 2004-02-06 2006-11-10 삼성전자주식회사 멀티 스택 패키지의 제조방법
US7667333B2 (en) * 2006-01-27 2010-02-23 Infineon Technologies Ag Stack of semiconductor chips
KR100840788B1 (ko) * 2006-12-05 2008-06-23 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
US20080157316A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US8421244B2 (en) * 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
KR100923562B1 (ko) * 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US20110024890A1 (en) * 2007-06-29 2011-02-03 Stats Chippac, Ltd. Stackable Package By Using Internal Stacking Modules
US8101460B2 (en) * 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US8106504B2 (en) * 2008-09-25 2012-01-31 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
KR20100037300A (ko) * 2008-10-01 2010-04-09 삼성전자주식회사 내장형 인터포저를 갖는 반도체장치의 형성방법
JP2010287710A (ja) * 2009-06-11 2010-12-24 Renesas Electronics Corp 半導体装置およびその製造方法
US8558392B2 (en) * 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US20120049334A1 (en) * 2010-08-27 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
KR101209980B1 (ko) * 2010-12-09 2012-12-07 주식회사 네패스 반도체 패키지 및 그 제조 방법
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US8552567B2 (en) * 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US9190297B2 (en) * 2011-08-11 2015-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US9385009B2 (en) * 2011-09-23 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP
US8779601B2 (en) * 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8823180B2 (en) * 2011-12-28 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
TWI497645B (zh) * 2012-08-03 2015-08-21 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI496270B (zh) * 2013-03-12 2015-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
KR102094924B1 (ko) * 2013-06-27 2020-03-30 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
US9299640B2 (en) * 2013-07-16 2016-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Front-to-back bonding with through-substrate via (TSV)
US9676611B2 (en) * 2013-10-18 2017-06-13 Nxp Usa, Inc. Sensor device packages and related fabrication methods
CN203721707U (zh) * 2014-02-28 2014-07-16 矽力杰半导体技术(杭州)有限公司 芯片封装结构
KR102317263B1 (ko) * 2014-03-11 2021-10-25 삼성전자주식회사 반도체 패키지 및 이를 포함하는 데이터 저장 장치
KR102258743B1 (ko) * 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893053A (zh) * 2005-07-08 2007-01-10 三星电子株式会社 插件结构及其制造方法、晶片级堆叠结构和封装结构
CN101330068A (zh) * 2007-06-18 2008-12-24 海力士半导体有限公司 模制重配置晶片、使用其的叠置封装及该封装的制造方法
CN101877349A (zh) * 2009-04-30 2010-11-03 三洋电机株式会社 半导体模块及便携式设备

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11784164B2 (en) 2019-05-31 2023-10-10 Kepler Computing Inc. 3D stacked compute and memory with copper-to-copper hybrid bond
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
US11829699B1 (en) 2021-08-06 2023-11-28 Kepler Computing Inc. Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging
US11841757B1 (en) 2021-08-06 2023-12-12 Kepler Computing Inc. Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic
US11899613B1 (en) 2021-08-06 2024-02-13 Kepler Computing Inc. Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

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