CN203721707U - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

Info

Publication number
CN203721707U
CN203721707U CN201420090766.9U CN201420090766U CN203721707U CN 203721707 U CN203721707 U CN 203721707U CN 201420090766 U CN201420090766 U CN 201420090766U CN 203721707 U CN203721707 U CN 203721707U
Authority
CN
China
Prior art keywords
chip
layer
top layer
electrode
middle level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN201420090766.9U
Other languages
English (en)
Inventor
叶佳明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hefei Silicon Microelectronics Technology Co ltd
Original Assignee
Hangzhou Silergy Semiconductor Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Silergy Semiconductor Technology Ltd filed Critical Hangzhou Silergy Semiconductor Technology Ltd
Priority to CN201420090766.9U priority Critical patent/CN203721707U/zh
Application granted granted Critical
Publication of CN203721707U publication Critical patent/CN203721707U/zh
Priority to US14/613,593 priority patent/US20150249068A1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16113—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本实用新型公开了一种芯片封装结构，包括芯片载体和芯片层，所述的芯片层至少包括顶层芯片，在顶层芯片内设有导电孔，所述的导电孔通向顶层芯片的背面，并将顶层芯片上有源面的电极或顶层芯片内有源区的电极引至顶层芯片的背面，在顶层芯片的背面设置重新布线层，在重新布线层上引出电极通过引线键合至芯片载体上。由于通过在芯片内形成导电孔，并对导电孔进行重新布线后，将电极引出从而引线键合至芯片载体或其他层的芯片，在芯片有源面位置有限的情况下，可以从其背面将电极引出，布局更加合理，同时芯片内的部分器件的有源区靠近芯片背面，通过导电孔将有源区从背面引出更为方便。

Description

芯片封装结构
技术领域
本实用新型涉及半导体封装领域，更具体地涉及一种芯片封装结构。
背景技术
众所周知，半导体芯片的正面为具有电极的有源面，其背面为不具有电极的封装体。芯片倒装即将芯片有源面通过导电凸块连接于芯片载体上。随着芯片倒装工艺的不断发展和日趋成熟，倒装工艺以其良好的电学热学性能以及能减小芯片的封装尺寸等优点，从而被广泛应用。
但是，芯片集成度越高，则在芯片有源面上需要引出的电极也就越多，而有源面的表面尺寸非常有限，由于在倒装时需要引出的电极则要通过导电凸块电连接至芯片载体上，在有源面上能够排布的导电凸块非常有限，这就导致部分电极难以被引出。同时，考虑到部分器件（如：功率器件）在芯片中的位置，其中器件内的某些电极难以引至有源面。
综上所述，现有技术的芯片封装结构由于有源面尺寸有限，无法满足集成化和小型化条件下导电凸块排布和电极引出的需要。在芯片内集成特殊器件时，若器件的某一电极位于靠近芯片背面一侧，也会给电极的引出带来不便。
实用新型内容
有鉴于此，本实用新型的目的在于提供一种的芯片封装结构，以解决现有技术中芯片没有足够的位置来引出电极和芯片内部分器件的电极不方便引出的问题。
本实用新型的技术解决方案是，提供一种以下结构的芯片封装结构，包括芯片载体和芯片层，所述的芯片层至少包括顶层芯片，所述的顶层芯片至少包括一块芯片，在顶层芯片内设有导电孔，所述的导电孔通向顶层芯片的背面，并将顶层芯片上有源面的电极或顶层芯片内有源区的电极引至顶层芯片的背面，在顶层芯片的背面设置重新布线层，在重新布线层上引出电极通过引线键合至芯片载体上。
优选地，所述顶层芯片的有源面通过导电凸块与芯片载体电连接；实现顶层芯片在芯片载体上的倒装。
优选地，所述的芯片层还包括位于顶层芯片下方的底层芯片，所述的底层芯片内也设有导电孔，所述导电孔通向底层芯片的背面，并将底层芯片上有源面的电极或底层芯片内有源区的电极引至底层芯片的背面，在底层芯片背面也设置重新布线层，底层芯片的有源面通过导电凸块与芯片载体电连接；优选地，所述顶层芯片的有源面通过导电凸块与底层芯片背面的重新分布层电连接。
优选地，在顶层芯片和底层芯片之间设有至少一层中层芯片，所述中层芯片内也设有导电孔，所述导电孔通向中层芯片的背面，并将中层芯片上有源面的电极或中层芯片内有源区的电极引至中层芯片的背面，在中层芯片背面也设置重新布线层，顶层芯片的有源面通过导电凸块与中层芯片背面的重新布线层电连接，中层芯片的有源面通过导电凸块与底层芯片背面的重新分布层电连接。
优选地，在所述顶层芯片背面的重新布线层上引出电极通过引线键合至底层芯片或/和中层芯片背面的重新分布层上。
优选地，所述的底层芯片或/和中层芯片背面的重新分布层上引出电极通过引线键合至芯片载体上。
优选地，所述的芯片封装结构还包括被动元件层，所述的被动元件层放置在顶层芯片上，并与顶层芯片的重新布线层电连接；提高了产品的集成化程度。
优选地，所述顶层芯片、底层芯片和中层芯片的重新分布层均包括绝缘层和图案化导电层，所述绝缘层覆设于芯片的背面，图案化导电层设置在绝缘层上，并与相应的导电孔电连接。
采用本实用新型的结构，与现有技术相比，具有以下优点：由于通过在芯片内形成导电孔，并对导电孔进行重新布线后，将电极引出从而引线键合至芯片载体或其他层的芯片，在芯片有源面位置有限的情况下，可以从其背面将电极引出，布局更加合理，同时芯片内的部分器件的有源区靠近芯片背面，通过导电孔将有源区从背面引出更为方便。
附图说明
图1为本实用新型芯片封装结构的结构示意图（实施例1）；
图2为本实用新型芯片封装结构的结构示意图（实施例2）；
图3为本实用新型芯片封装结构的结构示意图（实施例3）；
图4为本实用新型芯片封装结构的结构示意图（实施例4）；
具体实施方式
以下将参照附图更详细地描述本实用新型的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。
为了清楚起见，附图中的各个部分没有按比例绘制。为了简明起见，可以在一幅图中描述经过数个步骤后获得的组件结构。此外，还可能省略某些公知的细节。对于芯片的位置，以下实施例附图中，均为有源面朝下，背面朝上。
实施例1：
如图1所示，本实施例中的芯片层只包括顶层芯片110，所述顶层芯片110的有源面（有源面朝下，背面朝上）通过导电凸块120与芯片载体130电连接。在顶层芯片内设有导电孔140，所述的导电孔140通向顶层芯片110的背面，并将顶层芯片110上有源面的电极或顶层芯片110内有源区的电极引至顶层芯片110的背面，在顶层芯片110的背面设置重新布线层150。所述的重新分布层为包括绝缘层151和图案化导电层152，所述绝缘层151覆设于顶层芯片110的背面，图案化导电层152设置在绝缘层151上，并与相应的导电孔140电连接。在顶层芯片110背面的重新布线层150上设置焊垫160，从焊垫160引线键合至芯片载体130。
实施例2：
如图2所示，实施例2与1的不同在于：所述的芯片层包括顶层芯片210和底层芯片270，所述的底层芯片270内也设有导电孔240，所述导电孔通向底层芯片270的背面，并将底层芯片270上有源面的电极或底层芯片内有源区的电极引至底层芯片270的背面，在底层芯片270背面也设置重新布线层250（包括绝缘层251和图案化导电层252），底层芯片的有源面通过导电凸块220与芯片载体230电连接。所述顶层芯片210的有源面通过导电凸块220与底层芯片270背面的重新分布层250电连接。在所述顶层芯片210背面的重新布线层250上引出电极通过引线键合至底层芯片270，即在顶层芯片210的重新分布层上设置焊垫260，从焊垫260引线键合至底层芯片270。
实施例3：
如图3所示，实施例3是在实施例2的基础上，在顶层芯片310和底层芯片370之间设有一层中层芯片380（本实施例以一层中层芯片为例，可以根据需要采用若干层中层芯片）。所述中层芯片380内也设有导电孔，所述导电孔通向中层芯片380的背面，并将中层芯片380上有源面的电极或中层芯片内有源区的电极引至中层芯片380的背面，在中层芯片380背面也设置重新布线层350，顶层芯片310的有源面通过导电凸块320与中层芯片380背面的重新布线层350电连接，中层芯片380的有源面通过导电凸块320与底层芯片380背面的重新分布层350电连接。在所述顶层芯片310背面的重新布线层上350引出电极（形成焊垫360）通过引线键合至底层芯片370或/和中层芯片380背面的重新分布层350上，所述的“或/和”是指既可以同时引线键合至底层芯片和中层芯片，也可以只引线键合至底层芯片，或者只引线键合至中层芯片。本实施例以同时键合至底层芯片和中层芯片背面的重新分布层上为例。
实施例4：
如图4所示，本实施例是在实施例1的基础上，设置被动元件层490，所述的被动元件层490放置在顶层芯片410背面上，并与重新布线层450（（包括绝缘层451和图案化导电层452）电连接，一般通过焊接连接。顶层芯片410通过导电凸块420与芯片载体430电连接。重新分布层450上设有焊垫460，焊垫460通过引线键合至芯片载体430上。被动元件层490与顶层芯片410背面通过焊接方式连接，并在二者之间填充有非导电填充料。所述被动元件层490至少包括一个被动元件（也称为无源元件），如电感、电容、电阻等。
以上各个实施例在结构上并非完全独立的，可以相互组合和变形，并不限于上述几种实施例，由于难以一一列举和附图。例如，将实施例4中的被动元件层运用于实施例2、3中也一样可行。所述的导电孔可以是通孔，也可以是盲孔，例如，并不一定要打通芯片，只需通至芯片的有源区即可，所述有源区是指芯片上做有源器件的区域，即将有源器件的某一极通过导电孔引出至芯片背面。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (9)

1.一种芯片封装结构，包括芯片载体和芯片层，所述的芯片层至少包括顶层芯片，其特征在于：在顶层芯片内设有导电孔，所述的导电孔通向顶层芯片的背面，并将顶层芯片上有源面的电极或顶层芯片内有源区的电极引至顶层芯片的背面，在顶层芯片的背面设置重新布线层，在重新布线层上引出电极通过引线键合至芯片载体上。
2.根据权利要求1所述的芯片封装结构，其特征在于：所述顶层芯片的有源面通过导电凸块与芯片载体电连接。
3.根据权利要求1所述的芯片封装结构，其特征在于：所述的芯片层还包括位于顶层芯片下方的底层芯片，所述的底层芯片内也设有导电孔，所述导电孔通向底层芯片的背面，并将底层芯片上有源面的电极或底层芯片内有源区的电极引至底层芯片的背面，在底层芯片背面也设置重新布线层，底层芯片的有源面通过导电凸块与芯片载体电连接。
4.根据权利要求3所述的芯片封装结构，其特征在于：所述顶层芯片的有源面通过导电凸块与底层芯片背面的重新分布层电连接。
5.根据权利要求3所述的芯片封装结构，其特征在于：在顶层芯片和底层芯片之间设有至少一层中层芯片，所述中层芯片内也设有导电孔，所述导电孔通向中层芯片的背面，并将中层芯片上有源面的电极或中层芯片内有源区的电极引至中层芯片的背面，在中层芯片背面也设置重新布线层，顶层芯片的有源面通过导电凸块与中层芯片背面的重新布线层电连接，中层芯片的有源面通过导电凸块与底层芯片背面的重新分布层电连接。
6.根据权利要求5所述的芯片封装结构，其特征在于：在所述顶层芯片背面的重新布线层上引出电极通过引线键合至底层芯片或/和中层芯片背面的重新分布层上。
7.根据权利要求5所述的芯片封装结构，其特征在于：所述的底层芯片或/和中层芯片背面的重新分布层上引出电极通过引线键合至芯片载体上。
8.根据权利要求1或3或5所述的芯片封装结构，其特征在于：所述的芯片封装结构还包括被动元件层，所述的被动元件层放置在顶层芯片上，并与顶层芯片的重新布线层电连接。
9.根据权利要求1或3或5所述的芯片封装结构，其特征在于：所述顶层芯片、底层芯片和中层芯片的重新分布层均包括绝缘层和图案化导电层，所述绝缘层覆设于芯片的背面，图案化导电层设置在绝缘层上，并与相应的导电孔电连接。
CN201420090766.9U 2014-02-28 2014-02-28 芯片封装结构 Expired - Lifetime CN203721707U (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201420090766.9U CN203721707U (zh) 2014-02-28 2014-02-28 芯片封装结构
US14/613,593 US20150249068A1 (en) 2014-02-28 2015-02-04 Chip package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420090766.9U CN203721707U (zh) 2014-02-28 2014-02-28 芯片封装结构

Publications (1)

Publication Number Publication Date
CN203721707U true CN203721707U (zh) 2014-07-16

Family

ID=51160843

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420090766.9U Expired - Lifetime CN203721707U (zh) 2014-02-28 2014-02-28 芯片封装结构

Country Status (2)

Country Link
US (1) US20150249068A1 (zh)
CN (1) CN203721707U (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105609480A (zh) * 2015-12-24 2016-05-25 合肥祖安投资合伙企业(有限合伙) 叠层芯片封装结构
US10333019B2 (en) 2016-05-27 2019-06-25 Silergy Semiconductor Technology (Hangzhou) Ltd. Package structure of light emitter and light sensor with light-blocking layer and method for manufacturing the same
CN110148566A (zh) * 2019-06-03 2019-08-20 珠海格力电器股份有限公司 一种堆叠结构的智能功率模块及其制造方法
CN113097169A (zh) * 2021-03-31 2021-07-09 中国科学院半导体研究所 用于高发热量芯片镍钯金线键合与锡植球共同封装结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101394203B1 (ko) * 2011-12-29 2014-05-14 주식회사 네패스 적층형 반도체 패키지 및 그 제조 방법
KR102494655B1 (ko) 2017-06-19 2023-02-03 삼성전자주식회사 반도체 패키지

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171585B2 (en) * 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8445325B2 (en) * 2007-05-04 2013-05-21 Stats Chippac, Ltd. Package-in-package using through-hole via die on saw streets
US7829998B2 (en) * 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US8169058B2 (en) * 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8716855B2 (en) * 2010-11-10 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit system with distributed power supply comprising interposer and voltage regulator module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105609480A (zh) * 2015-12-24 2016-05-25 合肥祖安投资合伙企业(有限合伙) 叠层芯片封装结构
US10333019B2 (en) 2016-05-27 2019-06-25 Silergy Semiconductor Technology (Hangzhou) Ltd. Package structure of light emitter and light sensor with light-blocking layer and method for manufacturing the same
CN110148566A (zh) * 2019-06-03 2019-08-20 珠海格力电器股份有限公司 一种堆叠结构的智能功率模块及其制造方法
CN110148566B (zh) * 2019-06-03 2020-12-25 珠海零边界集成电路有限公司 一种堆叠结构的智能功率模块及其制造方法
CN113097169A (zh) * 2021-03-31 2021-07-09 中国科学院半导体研究所 用于高发热量芯片镍钯金线键合与锡植球共同封装结构

Also Published As

Publication number Publication date
US20150249068A1 (en) 2015-09-03

Similar Documents

Publication Publication Date Title
CN203721707U (zh) 芯片封装结构
US8669650B2 (en) Flip chip semiconductor device
KR101046394B1 (ko) 스택 패키지
US8154108B2 (en) Dual-leadframe multi-chip package and method of manufacture
CN106711118B (zh) 电子封装件及其制法
US9299685B2 (en) Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
US9167686B2 (en) 3D stacked package structure and method of manufacturing the same
KR20110055973A (ko) 반도체 칩 모듈 및 이를 포함하는 반도체 패키지
US20210249952A1 (en) Power delivery for multi-chip-package using in-package voltage regulator
CN105244347B (zh) 一种嵌入式封装及封装方法
CN103325755A (zh) 半导体封装结构
US9437587B2 (en) Flip chip semiconductor device
CN107680951A (zh) 一种多芯片叠层的封装结构及其封装方法
CN203521406U (zh) 多芯片叠合封装结构
CN105374805A (zh) 一种多芯片封装结构
CN105489578B (zh) 叠层芯片封装结构
CN104916599B (zh) 芯片封装方法和芯片封装结构
CN103400826B (zh) 半导体封装及其制造方法
KR101537390B1 (ko) 인터포저를 이용한 적층형 반도체 패키지
KR101219086B1 (ko) 패키지 모듈
CN205282470U (zh) 叠层芯片封装结构
CN201994292U (zh) 高密度系统级封装结构
CN205211727U (zh) 一种指纹识别多芯片封装结构
TWI604593B (zh) 半導體封裝件及其製法
CN105609480B (zh) 叠层芯片封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160118

Address after: 230000, Hefei province high tech Zone, 2800 innovation Avenue, 201 innovation industry park, H2 building, room two, Anhui

Patentee after: Hefei Silicon Microelectronics Technology Co.,Ltd.

Address before: 310012 Wensanlu Road, Hangzhou Province, No. 90 East Software Park, science and technology building A1501

Patentee before: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) Co.,Ltd.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20140716