CN101335262A - 叠层封装及其制造方法 - Google Patents

叠层封装及其制造方法 Download PDF

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Publication number
CN101335262A
CN101335262A CNA2007101962460A CN200710196246A CN101335262A CN 101335262 A CN101335262 A CN 101335262A CN A2007101962460 A CNA2007101962460 A CN A2007101962460A CN 200710196246 A CN200710196246 A CN 200710196246A CN 101335262 A CN101335262 A CN 101335262A
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semiconductor chip
stacked package
wafer
silicon path
wafers
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CN101335262B (zh
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郑冠镐
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种叠层封装及其制造方法。所述叠层封装包括放置的第一和第二半导体芯片，使得所述叠层封装的其上形成结合焊垫的表面相互面对；形成于第一和第二半导体芯片内的多个贯穿硅通路；和成于第一和第二半导体芯片的表面上从而连接所述贯穿硅通路至对应的结合焊垫的多个再分布层形，其中所述第一和第二半导体芯片的再分布层相互接触。通过用这种方式形成叠层封装，可以防止在制造工艺期间形成的捡取误差和裂纹，并且因此可以可靠地形成叠层封装。

Description

叠层封装及其制造方法
技术领域
本发明涉及一种叠层封装及其制造方法，更具体地，涉及防止晶片和半导体芯片翘曲并且防止在制造工艺期间出现裂纹的叠层封装及其制造方法。
背景技术
半导体集成电路的封装技术在不断进化，以便满足小型化和高容量的需求。最近，本领域中已经公开了许多叠层封装的技术，对于小型化、高容量和安装效率提供了满意的结果。
术语“层叠”在半导体工业中指称垂直地堆放至少两个芯片或封装。在存储器件的情形，通过层叠芯片或封装，可以同时实现具有比通过半导体集成工艺可获得的更大的存储容量的产品并且改善安装面积的使用效率。
叠层封装制造方法可以被分为第一方法，其中单独的半导体芯片被层叠并且层叠的半导体芯片被封装，和第二方法，其中单独封装的半导体芯片相互层叠。在叠层封装中，通过金属布线或贯穿硅通路而形成电连接。
图1是示出使用金属布线的传统叠层封装的截面图。
参考图1，在使用金属布线的传统叠层封装100中，至少两个半导体芯片110通过粘接介质层叠在基底120上，并且各个芯片110和基底120通过金属布线116而相互电连接。
在图1中，未解释的参考标号112指示结合焊垫，122指示连接焊垫，124指示球形焊盘，170指示外部连接端子，并且190指示密封剂。
然而，在使用金属布线的传统叠层封装100中，由于电信号交换通过金属布线116进行，所以各个半导体芯片110的运行速度低。此外，使用多个金属布线116引起各个芯片的电特性降低。此外，在使用金属布线的传统叠层封装100中，为了形成使用金属布线116的电连接，在容纳金属布线116的基底内需要额外的区，并且因此叠层封装100的尺寸增加了。另外，在使用金属布线的传统叠层封装100中，需要间隙以便将金属布线116结合至对应的芯片110，因而需要增加叠层封装100的整体高度。
因此，为了克服使用金属布线的叠层封装的问题、防止叠层封装的电特性的降低，并且使叠层封装的小型化成为可能，在本领域中建议使用贯穿硅通路(TSV)的叠层封装。
图2是示出使用贯穿硅通路的传统叠层封装的截面图。
参考图2，在使用贯穿硅通路的传统叠层封装200中，具有形成于其内的贯穿硅通路230的半导体芯片210以这样的方式层叠在基底220上，使得芯片210的贯穿硅通路相互面对。
在图2中，未解释的参考标号212指示绝缘层、214指示金属仔晶层、222指示连接焊垫、224指示球形焊盘、270指示外部连接端子并且218指示金属线。
在使用贯穿硅通路的叠层封装200中，由于通过贯穿硅通路230形成电连接，所以可以防止各个芯片210的电性能的降低。因此，可以增加半导体芯片210的运行速度，并且可以小型化半导体芯片210。
无论如何，在晶片级或芯片级使用贯穿硅通路形成叠层封装的情形，待层叠的晶片或半导体芯片由于形成贯穿硅通路的研磨工艺而具有明显减小的厚度。因此，当层叠具有贯穿硅通路的晶片或半导体芯片时，由于热膨胀系数的不同，晶片或半导体芯片有可能翘曲，并且难于恰当地层叠晶片或半导体芯片。具体地，可以出现捡取误差并且在晶片或半导体芯片内形成裂纹，从而导致制造产率下降。
发明内容
本发明的实施例涉及防止晶片和半导体芯片翘曲和防止在制造工艺中出现裂纹的叠层封装，及其制造方法。
另外，本发明的实施例涉及通过防止晶片和半导体芯片翘曲并且防止出现裂纹而保持制造产率的叠层封装，及其制造方法。
在一个方面，叠层封装包括放置的第一和第二芯片，使得其上形成结合焊垫的其表面相互面对；形成于第一和第二半导体芯片中的多个贯穿硅通路；和形成于第一和第二半导体芯片的表面上从而将所述贯穿硅通路连接至对应的结合焊垫的多个再分布层，其中第一半导体芯片的再分布层接触第二半导体芯片的再分布层。
贯穿硅通路和再分布层可以相互集成形成。
贯穿硅通路和再分布层可以由锡(Sn)、镍(Ni)、铜(Cu)、金(Au)、铝(Al)或其合金形成。
可以使第一半导体芯片的再分布层和第二半导体芯片的再分布层通过各向异性导电膜或焊膏的介质而相互接触。
叠层封装还包括填充第一和第二半导体芯片之间未被相互接触的再分布层占据的空间的填充材料。
叠层封装还包括对其贴附层叠的第一和第二半导体芯片的基底。
叠层封装还包括在未贴附到基底的半导体芯片上形成的保护层。
在另一方面中，叠层封装包括至少两个叠层封装单元，各个封装单元包括放置的第一和第二芯片，使得其上形成结合焊垫的其表面相互面对；形成于第一和第二半导体芯片内的多个贯穿硅通路；并且形成于第一和第二半导体芯片的表面上从而将所述贯穿硅通路连接至对应的结合焊垫的多个再分布层，并且使得第一半导体芯片的再分布层接触对应的第二半导体芯片的再分布层，其中封装单元被层叠，使得其贯穿硅通路相互接触。
贯穿硅通路和再分布层可以相互集成形成。
贯穿硅通路和再分布层可以由锡(Sn)、镍(Ni)、铜(Cu)、金(Au)、铝(Al)或其合金形成。
可以使在各个封装单元内的再分布层和在所述叠层封装单元内的贯穿硅通路通过各向异性导电膜或焊膏的介质而相互接触。
叠层封装还可以包括在各个封装单元内填充不被再分布线所占据的第一和第二半导体芯片之间的空间的填充材料。叠层封装还可以包括填充贯穿硅通路不相互接触的叠层封装单元之间的空间的填充材料。
叠层封装还包括对其贴附层叠的第一和第二半导体芯片的基底。
叠层封装还包括形成于在叠层封装单元中最上的封装单元的向上定位的半导体芯片上的保护层。
在又一方面中，叠层封装的制造方法包括的步骤是：在包括分别具有多个结合焊垫的半导体芯片的各个第一和第二晶片内界定多个凹槽，所述凹槽形成至一定的深度使得凹槽不透过第一和第二晶片；在所述第一和第二晶片的凹槽内形成贯穿硅通路并且形成再分布层以将所述贯穿硅通路连接至对应的结合焊垫；相互贴附第一和第二晶片使得其对应的再分布层相互接触；研磨第一和第二晶片的下表面，使得在第一和第二晶片内形成的贯穿硅通路被暴露；并且切割半导体芯片之间的贴附的第一和第二晶片，由此形成多个封装单元。
形成贯穿硅通路和再分布层的步骤包括的步骤是：在第一和第二晶片内所界定的凹槽的侧壁上形成绝缘层；在各个晶片、绝缘层和各个凹槽的底部上形成金属仔晶层；在金属仔晶层上形成金属层从而填充凹槽；并且构图金属层和金属仔晶层。
贯穿硅通路和再分布层可以由锡(Sn)、镍(Ni)、铜(Cu)、金(Au)、铝(Al)或其合金形成。
各向异性的导电膜或焊膏的介质可以形成于对应的再分布层之间使第一和第二晶片实行接触。
在相互贴附第一和第二晶片的步骤和研磨第一和第二晶片的下表面的步骤之间，所述方法还可以包括在未被再分布层占据的贴附的第一和第二晶片之间的空间内填充填充材料的步骤。
研磨第一和第二晶片的下表面的步骤包括的步骤是：贴附第一带至第一晶片的下表面；研磨第二晶片的下表面，使得贯穿硅通路被暴露；去除贴附到第一晶片的下表面的第一带；贴附第二带至被研磨过的第二晶片的下表面；研磨第一晶片的下表面，使得贯穿硅通路被暴露；并且去除贴附到第二晶片的下表面的第二带。
在形成多个封装单元的步骤之后，所述方法还包括贴附所形成的封装单元至基底的步骤；和在封装单元的向上定位的半导体芯片上形成保护层的步骤。
在形成多个封装单元的步骤之后，所述方法还包括层叠至少两个封装单元，使得其贯穿硅通路相互接触的步骤；贴附叠层的封装单元至基底的步骤；和在叠层封装单元的最上的封装单元的向上定位的半导体芯片上形成保护层的步骤。
各向异性导电膜或焊膏的介质可以形成于贯穿硅通路之间以便实行接触。
附图说明
图1是示出使用金属布线的传统叠层封装的截面图。
图2是示出使用贯穿硅通路的传统叠层封装的截面图。
图3是根据本发明一实施例的叠层封装的截面图。
图4A至4I是示出根据本发明另一实施例的叠层封装的制造方法的工艺的截面图。
图5是示出根据本发明又一实施例的叠层封装的截面图。
具体实施方式
在本发明中，使用了一种方法，其中在层叠待电连接的晶片之后，两个晶片的下表面被背研磨，由此在晶片级或芯片级实现了使用贯穿硅通路的叠层封装。此外，在本发明中，叠层封装以这样的方式实现，使得单个封装单元或多个封装单元通过贯穿硅通路安装到具有基底的外部电路。贯穿硅通路通过背研磨对应的层叠晶片的下表面而被暴露。通过这样做，本发明解决了在传统技术中由于晶片和半导体芯片的厚度减小所引起的问题。
更确切地说，在本发明中，形成有贯穿硅通路和再分布层的第一和第二半导体芯片在晶片级上以这样的方式相互贴附，使得再分布层相互接触，再分布层将贯穿硅通路和结合焊垫相互连接。然后，通过将所得的封装安装到基底而形成封装单元。另外，多个封装单元可以被层叠，并且随后安装至基底，由此形成层叠封装。
因而，在本发明中，由于叠层封装通过以这样的方式背研磨两个晶片的下表面而形成(在层叠待电连接的晶片之后)，使得贯穿硅通路通过晶片的下表面被暴露。通过以这样的方式形成封装，可以抑制或者防止由于晶片的厚度减小所导致的翘曲所引起的捡取误差和裂纹。因此，本发明可以解决在制造叠层封装的传统方法中所导致的问题。
结果，在本发明中可以可靠地形成叠层封装，由此增加叠层封装的产率，并且具体地，可以容易地实现具有减小了的厚度的叠层封装。
以下，将详细描述叠层封装及其制造方法。
图3使示出根据本发明一实施例的叠层封装的截面图。
参考图3，放置第一和第二半导体芯片310a和310b，使得其表面(在其上形成结合焊垫321)相互面对。贯穿硅通路320形成于对应的第一和第二半导体芯片310a和310b内，并且再分布层322形成于贯穿硅通路320和结合焊垫312之间。第一和第二半导体芯片310a和310b通过在再分布层322之间形成的焊膏(未示出)、以及填充在第一和第二半导体芯片310a和310b之间的空间的例如非导电膏的第一填充材料324a的介质而相互电连接或者物理连接。
层叠的第一和第二半导体芯片310a和310b贴附至基底340，基底340在其上表面上具有连接焊垫。焊料球344贴附到基底340的下表面。向下定位的第一半导体芯片310a和基底340通过在第一半导体芯片310a的贯穿硅通路320和基底340的连接焊垫342之间的焊膏(未示出)、以及填充在第一半导体芯片310a和基底340之间的例如非导电膏的第二填充材料324b的介质而相互电和物理连接。
第一和第二半导体芯片310a和310b之间的层叠和第一半导体芯片310a和基底340之间的贴附还可以使用各向异性导电膜进行。
贯穿硅通路320和再分布层322由锡(Sn)、镍(Ni)、铜(Cu)、金(Au)、铝(Al)或其合金形成，并且相互集成。未解释的参考标号316指示绝缘层，318指示金属仔晶层。
图4A至4I是示出根据本发明另一实施例的叠层封装的制造方法的工艺步骤的截面图。
参考图4A，掩模图案314形成于经历制造工艺的晶片300上，使得晶片包括多个半导体芯片310，每个半导体芯片在其上表面上具有多个结合焊垫312和界定至合适的深度多个凹槽T使得所述凹槽不透过晶片300。
参考图4B，绝缘层316形成于晶片300的上表面和凹槽T的表面上。随后进行回蚀刻工艺使得绝缘层316仅残留在凹槽T的侧壁上。
参考图4C，金属仔晶层318形成于晶片300上，绝缘层316形成于凹槽T的侧壁和凹槽的底部上。然后，通过在金属仔晶层318上进行镀覆工艺，在晶片上形成金属层320a从而填充凹槽T。金属层320a由锡(Sn)、镍(Ni)、铜(Cu)、金(Au)、铝(Al)或其合金形成。
参考图4D，在金属层320a上进行回蚀刻工艺，使得金属层320a的高度减小至适合于形成希望的叠层封装的厚度。此后，通过构图工艺部分去除金属层320a和金属仔晶层318，形成再分布层322从而相互连接结合焊垫312和贯穿硅通路320。
参考图4E，形成具有与在图4D中所示出的相同结构的第二晶片300b之后，第一和第二晶片300a和300b相互贴附，使得对应的再分布层322相互接触。第一和第二晶片300a和300b通过夹置在再分布层322(其相互接触)之间的焊膏(未示出)、以及填充在排除了再分布层322的第一和第二晶片300a和300b之间的空间内的第一填充材料324a的介质而相互电和物理连接。作为替代，第一和第二晶片300a和300b可以通过在第一和第二晶片300a和300b之间和再分布层322之间都形成的各向异性导电膜而相互电和物理连接。
参考图4F，研磨层压带326贴附至第一晶片300a的下表面。通过进行研磨工艺和蚀刻工艺的至少之一，第二晶片300b的下表面被背研磨，由此暴露第二晶片300b的贯穿硅通路320。
参考图4G，从第一晶片300a的下表面去除研磨层压带326。随后第一晶片300a的贯穿硅通路通过与图4F相同的工艺而被暴露。
参考图4H，一带(未示出)被贴附至第一晶片300a或者第二晶片300b的下表面，以便进行切割工艺。然后切割相互贴附的第一和第二晶片300a和300b，并且第一和第二晶片的结合被划分为芯片级。此时，在芯片级层叠的半导体芯片310a和310b被分类为封装单元330。通过层叠多个封装单元330，可以形成叠层封装。
参考图4I，在芯片级层叠的第一和第二半导体芯片310a和310b被贴附至基底340，基底340在其上表面上具有连接焊垫342。焊料球344贴附至基底340的下表面。保护层350形成于向上定位的第二半导体芯片310b的下表面上，以便保护第二半导体芯片310b。向下定位的第一半导体芯片310a和基底340通过夹置在向下定位的第一半导体芯片310a的贯穿硅通路320和基底340的连接焊垫342之间的焊膏(未示出)的介质，并且还通过填充在第一半导体芯片310a和基底340的连接焊垫342之间的空间的第二填充材料而相互电和物理连接。作为替代，第一半导体芯片310a和基底340可以通过在第一半导体芯片310a和基底340之间、以及在贯穿硅通路320和基底340的连接焊垫342之间都形成的各向异性导电膜而相互电和物理连接。
如上所述，在本实施例中，待相互电连接的两个晶片被层叠之后，通过背研磨对应的晶片的下表面，形成叠层封装，其具有通过对应的晶片的下表面暴露的贯穿硅通路。因此，可以解决在形成叠层封装的工艺期间由于使用具有减小了的厚度的晶片而导致的翘曲所引起的问题。因而，在本发明中，可以可靠地形成叠层封装，由此增加叠层封装的制造产率，并且可以容易地实现具有减小了的厚度的叠层封装。
同时，在本发明中，可以通过相互层叠多个(在图4H中形成的)封装单元而形成叠层封装。
图5是示出根据本发明又一实施例的叠层封装的截面图。
参考图5，至少两个具有与在图4H中所示出的相同结构的封装单元430被层叠，使得对应的封装单元430的贯穿硅通路相互接触。叠层封装单元430贴附至基底440，基底440在其上表面上具有多个连接焊垫442。保护层450形成于最上的叠层封装单元430上，并且焊料球444形成于基底440的下表面上。
封装单元430通过夹置在对应的封装单元430的贯穿硅通路420之间的焊膏(未示出)、和填充在排除了贯穿硅通路420的封装单元430之间的空间的第三填充材料424c(例如非导电膏)的介质而相互电和物理连接。作为替代，封装单元430可以通过在封装单元430之间和贯穿硅通路420之间的空间都形成的各向同性导电膜的介质而相互电和物理连接。
制备封装单元430从而形成叠层封装的方法与在图4A至4F中所示出的相同，并且后续的贴附封装单元430至基底440的工艺与在图4I中所示出的相同。
从以上的描述显见，在本发明中，叠层封装以在层叠两个待相互电连接的晶片之后背研磨晶片的下表面的方式形成叠层封装。因此，可以防止在形成叠层封装期间由于使用具有减小了的厚度的晶片或者半导体芯片导致的翘曲而出现的捡取误差和裂纹。因而，在本发明中，可以可靠地形成叠层封装，由此增加叠层封装的制造产率，并且可以容易地实现具有减小了厚度的叠层封装。
此外，在本发明中，由于在层叠两个晶片之后进行晶片切割工艺，所以无需防止出现裂纹的激光切割工艺，并且因此可以使用传统设备进行切割工艺。
尽管为了说明的目的描述了本发明的具体实施例，但是本领域的技术人员应当理解可以进行各种改进、添加和替代，而不偏离在所附权利要求中所公开的精神和范围。
本申请要求于2007年6月26日提交的韩国专利申请第10-2007-0063181号的优先权，其通过引用的方式全文引入于此。

Claims (23)

1.一种叠层封装，包括：
第一半导体芯片和第二半导体芯片，每个具有第一侧和第二侧并且每个具有在所述第一侧上形成的多个结合焊垫，其中所述第一半导体芯片的第一侧面对所述第二半导体芯片的第一侧；
在所述第一和第二半导体芯片内形成的多个贯通硅通路；和
在所述第一和第二半导体芯片的第一表面上形成的多个再分配层，使得各个贯通硅通路连接至对应的结合焊垫，
其中各第一半导体芯片的再分配层接触所述第二半导体芯片的对应的再分配层。
2.根据权利要求1的叠层封装，其中所述贯穿硅通路和再分配层相互集成形成。
3.根据权利要求1的叠层封装，其中所述贯穿硅通路和再分配层由锡、镍、铜、金、铝、或其合金形成。
4.根据权利要求1的叠层封装，其中使所述第一半导体芯片的再分配层和第二半导体芯片的再分配层通过各向异性导电膜或焊膏的介质而相互接触。
5.根据权利要求1的叠层封装，还包括：
填充所述第一和第二半导体芯片之间不被相互接触的再分配层所占据的空间的填充材料。
6.根据权利要求1的叠层封装，还包括：
对其贴附所述第一半导体芯片的第二侧的基底。
7.根据权利要求6的叠层封装，还包括：
在所述第二半导体芯片的第二侧上形成的保护层。
8.一种包括多个叠层封装单元的叠层封装，各个封装单元包括：
第一半导体芯片和第二半导体芯片，每个具有第一侧和第二侧并且每个具有在所述第一侧内形成的多个结合焊垫，其中所述第一半导体芯片的第一侧面对第二半导体芯片的第一侧；
在所述第一和第二半导体芯片内形成的多个贯通硅通路；和
在所述第一和第二半导体芯片的第一表面上形成的多个再分配层，使得各个贯穿硅通路连接至对应的结合焊垫，
其中各个所述第一半导体芯片的再分配层接触第二半导体芯片的对应的再分配层，
其中所述封装单元被层叠，使得在封装单元内所述第二半导体芯片的第二侧面对另一封装单元的第一半导体芯片的第二侧，并且使其贯穿硅通路相互接触。
9.根据权利要求8的叠层封装，其中所述贯穿硅通路和再分配层相互集成形成。
10.根据权利要求8的叠层封装，其中所述贯穿硅通路和再分配层由锡、镍、铜、金、铝、或其合金形成。
11.根据权利要求8的叠层封装，其中使在各个封装单元内的所述再分配层和在所述叠层封装单元内的贯穿硅通路通过各向异性导电膜或焊膏的介质而相互接触。
12.根据权利要求8的叠层封装，还包括：
填充各封装单元内所述第一和第二半导体芯片之间空间内的第一填充材料，其中所述填充材料不填充在所述第一和第二半导体芯片之间由再分配层所占据的空间内；
填充所述层叠单元之间贯穿硅通路不相互接触的空间内的第二填充材料。
13.根据权利要求8的叠层封装，还包括：
对其贴附最底的封装单元的第一半导体芯片的基底。
14.根据权利要求8的叠层封装，还包括：
在所述封装单元内最上封装单元的第二半导体芯片上形成的保护层。
15.一种叠层封装的制造方法，包括的步骤是：
在第一晶片和第二晶片的上表面内界定多个凹槽，使得所述凹槽不透过第一和第二晶片的整个深度，其中所述第一和第二晶片每个具有多个半导体芯片并且各个半导体芯片具有多个结合焊垫；
在第一和第二晶片的凹槽中形成贯穿硅通路；
在第一和第二晶片的上表面上形成再分布层从而将各个贯穿硅通路连接至其对应的结合焊垫；
将所述第一晶片的上表面贴附到所述第二晶片的上表面，使得对应的再分布层相互接触；
研磨第一和第二晶片的下表面，使得在所述第一和第二晶片内形成的贯穿硅通路被暴露；并且
切割在所述第一和第二半导体晶片内的半导体芯片之间的所述被贴附的第一和第二晶片，从而形成多个封装单元。
16.根据权利要求15的方法，其中所述形成贯穿硅通路和再分布层的步骤包括的步骤是：
在所述第一和第二晶片中界定的凹槽的侧壁上形成绝缘层；
在各个晶片、在凹槽的侧壁的绝缘层、和各个凹槽的底部上形成金属仔晶层；
在所述金属仔晶层上形成金属层从而填充所述凹槽；并且
构图所述金属层和金属仔晶层。
17.根据权利要求16的方法，其中所述贯穿硅通路和再分布层由锡、镍、铜、金或其合金形成。
18.根据权利要求16的方法，其中各向异性导电膜或焊膏的介质形成于所述第一晶片的再分布层和第二晶片的再分布层之间。
19.根据权利要求15的方法，还包括：在相互贴附所述第一和第二晶片的步骤和研磨所述第一和第二晶片的下表面的步骤之间，在未被所述再分布层占据的贴附的第一和第二晶片之间的空间内填充填充材料。
20.根据权利要求15的方法，其中所述研磨第一和第二晶片的下表面的步骤包括的步骤是：
贴附第一带至所述第一晶片的下表面；
研磨所述第二晶片的下表面使得所述贯穿硅通路被暴露；
去除贴附到所述第一晶片的下表面的第一带；
贴附第二带至所述研磨过的第二晶片的下表面；
研磨所述第一晶片的下表面使得所述贯穿硅通路被暴露；并且
去除贴附到所述第二晶片的下表面的第二带。
21.根据权利要求15的方法，还包括的步骤是：
在形成所述多个封装单元之后，
贴附所述形成的封装单元至基底；并且
在所述封装单元的向上定位的半导体芯片上形成保护层。
22.根据权利要求15的方法，还包括的步骤是：
在形成多个封装单元的步骤之后
层叠多个封装单元使得所述被暴露的贯穿硅通路相互接触；
贴附最底的叠层封装单元至基底；并且
在叠层封装内的最上的封装单元的顶部形成保护层。
23.根据权利要求22的方法，其中各向异性导电膜或焊膏的介质形成于所述贯穿硅通路之间。
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Publication number Priority date Publication date Assignee Title
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CN102097335B (zh) * 2009-12-10 2013-03-20 日月光半导体制造股份有限公司 封装结构及其封装工艺
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Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8334599B2 (en) * 2008-08-21 2012-12-18 Qimonda Ag Electronic device having a chip stack
KR20100048610A (ko) 2008-10-31 2010-05-11 삼성전자주식회사 반도체 패키지 및 그 형성 방법
KR20100056247A (ko) * 2008-11-19 2010-05-27 삼성전자주식회사 접착층을 구비하는 반도체 패키지
US8168470B2 (en) * 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
US20100206737A1 (en) * 2009-02-17 2010-08-19 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
JP2010198869A (ja) * 2009-02-24 2010-09-09 Advanced Systems Japan Inc スルーシリコンビア構造を有するウエハーレベルコネクタ
KR101046385B1 (ko) * 2009-03-31 2011-07-05 주식회사 하이닉스반도체 반도체 패키지
JP5409084B2 (ja) 2009-04-06 2014-02-05 キヤノン株式会社 半導体装置の製造方法
US8216912B2 (en) 2009-08-26 2012-07-10 International Business Machines Corporation Method, structure, and design structure for a through-silicon-via Wilkinson power divider
KR20110061404A (ko) 2009-12-01 2011-06-09 삼성전자주식회사 칩 실리콘 관통 비아와 패키지간 연결부를 포함하는 반도체 패키지들의 적층 구조 및 그 제조 방법
TWI427753B (zh) * 2010-05-20 2014-02-21 Advanced Semiconductor Eng 封裝結構以及封裝製程
JP2012054395A (ja) * 2010-09-01 2012-03-15 Nec Corp 半導体パッケージ
US8987137B2 (en) 2010-12-16 2015-03-24 Lsi Corporation Method of fabrication of through-substrate vias
US8742535B2 (en) 2010-12-16 2014-06-03 Lsi Corporation Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
JP5970071B2 (ja) * 2011-09-30 2016-08-17 インテル・コーポレーション デバイス構造の製造方法および構造
US8796822B2 (en) 2011-10-07 2014-08-05 Freescale Semiconductor, Inc. Stacked semiconductor devices
US9076664B2 (en) * 2011-10-07 2015-07-07 Freescale Semiconductor, Inc. Stacked semiconductor die with continuous conductive vias
US9620430B2 (en) * 2012-01-23 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Sawing underfill in packaging processes
US8895360B2 (en) 2012-07-31 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated semiconductor device and wafer level method of fabricating the same
US9136213B2 (en) * 2012-08-02 2015-09-15 Infineon Technologies Ag Integrated system and method of making the integrated system
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KR101994930B1 (ko) * 2012-11-05 2019-07-01 삼성전자주식회사 일체형 단위 반도체 칩들을 갖는 반도체 패키지
KR102094924B1 (ko) * 2013-06-27 2020-03-30 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
US20150069609A1 (en) * 2013-09-12 2015-03-12 International Business Machines Corporation 3d chip crackstop
US9082757B2 (en) * 2013-10-31 2015-07-14 Freescale Semiconductor, Inc. Stacked semiconductor devices
JP6259737B2 (ja) * 2014-03-14 2018-01-10 東芝メモリ株式会社 半導体装置及びその製造方法
US9356009B2 (en) 2014-05-27 2016-05-31 Micron Technology, Inc. Interconnect structure with redundant electrical connectors and associated systems and methods
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
JP6335099B2 (ja) 2014-11-04 2018-05-30 東芝メモリ株式会社 半導体装置および半導体装置の製造方法
CN107004672B (zh) * 2014-12-18 2020-06-16 索尼公司 半导体装置、制造方法及电子设备
US10074594B2 (en) * 2015-04-17 2018-09-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
JP6443362B2 (ja) 2016-03-03 2018-12-26 株式会社デンソー 半導体装置
KR102570582B1 (ko) 2016-06-30 2023-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
JP6800788B2 (ja) 2017-03-15 2020-12-16 キオクシア株式会社 半導体記憶装置
JP6981800B2 (ja) * 2017-07-28 2021-12-17 浜松ホトニクス株式会社 積層型素子の製造方法
JP6496389B2 (ja) * 2017-11-28 2019-04-03 東芝メモリ株式会社 半導体装置及びその製造方法
KR102508552B1 (ko) * 2018-04-30 2023-03-10 에스케이하이닉스 주식회사 쓰루 몰드 비아를 포함하는 스택 패키지
KR102464066B1 (ko) * 2018-04-30 2022-11-07 에스케이하이닉스 주식회사 쓰루 몰드 비아를 포함하는 스택 패키지
KR102534734B1 (ko) 2018-09-03 2023-05-19 삼성전자 주식회사 반도체 패키지
JP2023531029A (ja) * 2021-02-05 2023-07-20 長江存儲科技有限責任公司 フリップチップスタッキング構造体およびそれを形成するための方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100364635B1 (ko) * 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
JP4028211B2 (ja) * 2001-11-01 2007-12-26 ローム株式会社 半導体装置
JP2003249620A (ja) * 2002-02-22 2003-09-05 Toray Eng Co Ltd 半導体の接合方法およびその方法により作成された積層半導体
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
JP4183070B2 (ja) * 2003-01-20 2008-11-19 富士通マイクロエレクトロニクス株式会社 マルチチップモジュール
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US20060284298A1 (en) * 2005-06-15 2006-12-21 Jae Myun Kim Chip stack package having same length bonding leads
JP4551321B2 (ja) * 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
KR20070063748A (ko) * 2005-12-15 2007-06-20 삼성전자주식회사 웨이퍼 레벨 패키지 및 이의 제조 방법
KR100743648B1 (ko) * 2006-03-17 2007-07-27 주식회사 하이닉스반도체 웨이퍼 레벨 시스템 인 패키지의 제조방법
US7288835B2 (en) * 2006-03-17 2007-10-30 Stats Chippac Ltd. Integrated circuit package-in-package system
JP2008135553A (ja) * 2006-11-28 2008-06-12 Fujitsu Ltd 基板積層方法及び基板が積層された半導体装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097335B (zh) * 2009-12-10 2013-03-20 日月光半导体制造股份有限公司 封装结构及其封装工艺
CN102157402A (zh) * 2011-03-23 2011-08-17 南通富士通微电子股份有限公司 系统级封装方法
CN102157402B (zh) * 2011-03-23 2013-02-13 南通富士通微电子股份有限公司 系统级封装方法
CN104347593A (zh) * 2013-07-25 2015-02-11 爱思开海力士有限公司 层叠封装体及其制造方法
CN104347593B (zh) * 2013-07-25 2019-03-08 爱思开海力士有限公司 层叠封装体及其制造方法
CN103413798A (zh) * 2013-08-02 2013-11-27 南通富士通微电子股份有限公司 芯片结构、芯片封装结构
CN104425467B (zh) * 2013-08-29 2019-02-01 爱思开海力士有限公司 叠层封装体及其制造方法
CN104916619A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置及其制造方法
CN104916619B (zh) * 2014-03-14 2019-07-12 东芝存储器株式会社 半导体装置及其制造方法
CN105161451A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法
CN105161451B (zh) * 2015-07-30 2017-11-07 通富微电子股份有限公司 半导体叠层封装方法

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