JP2009010312A - スタックパッケージ及びその製造方法 - Google Patents
スタックパッケージ及びその製造方法 Download PDFInfo
- Publication number
- JP2009010312A JP2009010312A JP2007286726A JP2007286726A JP2009010312A JP 2009010312 A JP2009010312 A JP 2009010312A JP 2007286726 A JP2007286726 A JP 2007286726A JP 2007286726 A JP2007286726 A JP 2007286726A JP 2009010312 A JP2009010312 A JP 2009010312A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- package
- stack package
- wafer
- rewiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/05611—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 スタックパッケージは、ボンディングパッド形成面が向かい合うように配置された第1及び第2半導体チップと、前記第1半導体チップ及び第2半導体チップ内にそれぞれ形成された多数のスルーシリコンビアと、前記第1半導体チップと第2半導体チップの各ボンディングパッド形成面上に、対応するスルーシリコンビアとボンディングパッドとを連結するようにそれぞれ形成されて、互いにコンタクトされた多数の再配線と、を含む。
【選択図】 図5
Description
図1に示すように、金属ワイヤを利用したスタックパッケージ100は、少なくとも2個以上の半導体チップ110が基板120上に接着剤114を介してスタックされ、前記各チップ110と基板120が金属ワイヤ116を通じて電気的に連結される。
前記スルーシリコンビア及び再配線は、スズ(Sn)、ニッケル(Ni)、銅(Cu)、金(Au)及びアルミニウム(Al)のうちのいずれか一つ、またはこれらのうちの少なくとも一つ以上で作製された合金で形成される。
上方に配置される第1半導体チップまたは第2半導体チップ上に形成されたキャッピング膜をさらに含む。
前記スルーシリコンビア及び再配線は、スズ(Sn)、ニッケル(Ni)、銅(Cu)、金(Au)及びアルミニウム(Al)のうちのいずれか一つ、またはこれらのうちの少なくとも一つ以上で作製された合金で形成される。
前記スタックされたパッケージユニットのうちの、最上部のパッケージユニットの上部半導体チップ上に形成されたキャッピング膜をさらに含む。
図3に示すように、ボンディングパッド312の形成面が向かい合うように、第1及び第2半導体チップ310a、310bが配置されている。前記第1及び第2半導体チップ310a、310b内にはそれぞれスルーシリコンビア320が形成され、前記スルーシリコンビア320とボンディングパッド312との間には再配線322が形成される。前記第1及び第2半導体チップ310a、310bは、前記再配線322の間に形成された半田ペースト(図示せず)、及び第1及び第2半導体チップ310a、310bの間の空間に設けられた非導電性ペースト(non conductive paste)などの第1充填材324aを介して、電気的及び物理的にスタックされる。
300b 第2ウェハー
310a 第1半導体チップ
310b 第2半導体チップ
312 ボンディングパッド
314 マスクパターン
316 絶縁膜
318 金属シード膜
320,420 スルーシリコンビア
320a 金属膜
322 再配線
324a 第1充填材
324b 第2充填材
326 グラインディングラミネートテープ
340,440 基板
342,442 接続パッド
344,444 ソルダボール
T 溝
424c 第3充填材
430 パッケージユニット
450 キャッピング膜
Claims (23)
- ボンディングパッド形成面が向かい合うように配置された第1及び第2半導体チップと、
前記第1半導体チップ及び第2半導体チップ内にそれぞれ形成された多数のスルーシリコンビアと、
前記第1半導体チップ及び第2半導体チップの各ボンディングパッド形成面上に、対応するスルーシリコンビアとボンディングパッドとを連結するようにそれぞれ形成されて、互いにコンタクトされた多数の再配線と、
を含むことを特徴とするスタックパッケージ。 - 前記スルーシリコンビアと再配線は、一体に形成されることを特徴とする請求項1に記載のスタックパッケージ。
- 前記スルーシリコンビア及び再配線はスズ(Sn)、ニッケル(Ni)、銅(Cu)、金(Au)及びアルミニウム(Al)のうちのいずれか一つ、またはこれらのうちの少なくとも一つ以上で作製された合金で形成されることを特徴とする請求項1に記載のスタックパッケージ。
- 前記第1半導体チップの再配線と第2半導体チップの再配線は、異方性導電フィルムまたは半田ペーストによって互いにコンタクトされることを特徴とする請求項1に記載のスタックパッケージ。
- 前記第1半導体チップと第2半導体チップとの間の空間に充填された充填材をさらに含むことを特徴とする請求項1に記載のスタックパッケージ。
- 前記スタックされた第1及び第2半導体チップが付着する基板をさらに含むことを特徴とする請求項1に記載のスタックパッケージ。
- 上方に配置される第1半導体チップまたは第2半導体チップ上に形成されたキャッピング膜をさらに含むことを特徴とする請求項6に記載のスタックパッケージ。
- 少なくとも二つ以上がスタックされたパッケージユニットを含み、
前記パッケージユニットは、
ボンディングパッド形成面が向かい合うように配置された第1及び第2半導体チップと、
前記第1半導体チップ及び第2半導体チップ内にそれぞれ形成された多数のスルーシリコンビアと、
前記第1半導体チップ及び第2半導体チップの各ボンディングパッドの形成面上に、対応するスルーシリコンビアとボンディングパッドとを連結するようにそれぞれ形成されて、互いにコンタクトされた多数の再配線と、を含み、
前記パッケージユニットは前記スルーシリコンビアが互いにコンタクトされるようにスタックされることを特徴とするスタックパッケージ。 - 前記スルーシリコンビアと再配線は、一体に形成されることを特徴とする請求項8に記載のスタックパッケージ。
- 前記スルーシリコンビア及び再配線は、スズ(Sn)、ニッケル(Ni)、銅(Cu)、金(Au)及びアルミニウム(Al)のうちのいずれか一つ、またはこれらのうちの少なくとも一つ以上で作製された合金で形成されることを特徴とする請求項8に記載のスタックパッケージ。
- 前記パッケージユニット内の再配線及び前記スタックされたパッケージユニット内のスルーシリコンビアは、異方性導電フィルムまたは半田ペーストによって互いにコンタクトされることを特徴とする請求項8に記載のスタックパッケージ。
- 前記パッケージユニット内の第1半導体チップと第2半導体チップとの間の空間、及び前記スタックされたパッケージユニットの間の空間に充填された充填材をさらに含むことを特徴とする請求項8に記載のスタックパッケージ。
- 前記スタックされたパッケージユニットが付着する基板をさらに含むことを特徴とする請求項8に記載のスタックパッケージ。
- 前記スタックされたパッケージユニットのうちの、最上部のパッケージユニットの上部半導体チップ上に形成されたキャッピング膜をさらに含むことを特徴とする請求項11に記載のスタックパッケージ。
- 多数のボンディングパッドを具備した半導体チップを含む第1及び第2ウェハーそれぞれに、前記各第1及び第2ウェハーを貫通しない深さで多数の溝を形成する工程と、
前記第1及び第2ウェハーの各溝内にスルーシリコンビアを形成すると共に、前記各スルーシリコンビアとこれに対応するボンディングパッドとを連結する再配線を形成する工程と、
前記第1及び第2ウェハーを、対応する再配線が互いにコンタクトされるように付着する工程と、
前記第1及び第2ウェハーに形成されたスルーシリコンビアが露出するように前記第1及び第2ウェハーの下面をそれぞれグラインディングする工程と、
前記付着した第1及び第2ウェハーをチップレベルで切断して多数のパッケージユニットを形成する工程と、
を含むことを特徴とするスタックパッケージの製造方法。 - 前記スルーシリコンビア及び再配線を形成する工程は、
前記第1及び第2ウェハーに形成された各溝の側壁に絶縁膜を形成する工程と、
前記絶縁膜を含む各ウェハー上に金属シード膜を形成する工程と、
前記各溝の内部が充填されるように前記金属シード膜上に金属膜を形成する工程と、
前記金属膜及び金属シード膜をパターニングする工程と、
を含むことを特徴とする請求項15に記載のスタックパッケージの製造方法。 - 前記スルーシリコンビア及び再配線は、スズ(Sn)、ニッケル(Ni)、銅(Cu)、金(Au)及びアルミニウム(Al)のうちのいずれか一つ、またはこれらのうちの少なくとも一つ以上で作製された合金で形成することを特徴とする請求項16に記載のスタックパッケージの製造方法。
- 前記第1ウェハーの再配線と前記第2ウェハーの再配線とのコンタクトは、異方性導電フィルムまたは半田ペーストを利用して行うことを特徴とする請求項16に記載のスタックパッケージの製造方法。
- 前記第1及び第2ウェハーを付着する工程と前記第1及び第2ウェハーの下面をグラインディングする工程との間に、
前記付着した第1ウェハーと第2ウェハーとの間の空間に充填材を充填する工程、をさらに含むことを特徴とする請求項15に記載のスタックパッケージの製造方法。 - 前記第1ウェハーと第2ウェハーとの下面をグラインディングする工程は、
前記第1ウェハーの下面に第1テープを付着する工程と、
前記第2ウェハーの下面をグラインディングする工程と、
前記第1ウェハーの下面に付着した第1テープを除去する工程と、
前記グラインディングされた第2ウェハーの下面に第2テープを付着する工程と、
前記第1ウェハーの下面をグラインディングする工程と、
前記第2ウェハーの下面に付着した第2テープを除去する工程と、
を含むことを特徴とする請求項15に記載のスタックパッケージの製造方法。 - 前記多数のパッケージユニットを形成する工程後、
前記形成されたパッケージユニットを基板上に付着させる工程と、
前記パッケージユニットの上部半導体チップ上にキャッピング膜を形成する工程と、をさらに含むことを特徴とする請求項15に記載のスタックパッケージの製造方法。 - 前記多数のパッケージユニットを形成する工程後、
前記少なくとも二つ以上のパッケージユニットを、スルーシリコンビアが互いにコンタクトされるようにスタックする工程と、
前記少なくとも二つ以上がスタックされたパッケージユニットを基板上に付着させる工程と、
前記スタックされたパッケージユニットらのうちの最上部のパッケージユニットの上部半導体チップ上に、キャッピング膜を形成する工程と、
をさらに含むことを特徴とする請求項15に記載のスタックパッケージ。 - 前記スルーシリコンビア間のコンタクトは、異方性導電フィルムまたは半田ペーストを利用して行うことを特徴とする請求項22に記載のスタックパッケージの製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070063181A KR100945504B1 (ko) | 2007-06-26 | 2007-06-26 | 스택 패키지 및 그의 제조 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009010312A true JP2009010312A (ja) | 2009-01-15 |
Family
ID=40159428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007286726A Pending JP2009010312A (ja) | 2007-06-26 | 2007-11-02 | スタックパッケージ及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20090001602A1 (ja) |
JP (1) | JP2009010312A (ja) |
KR (1) | KR100945504B1 (ja) |
CN (1) | CN101335262B (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010198869A (ja) * | 2009-02-24 | 2010-09-09 | Advanced Systems Japan Inc | スルーシリコンビア構造を有するウエハーレベルコネクタ |
US8871640B2 (en) | 2009-04-06 | 2014-10-28 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor chip |
JP2015176958A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2015188052A (ja) * | 2014-03-14 | 2015-10-29 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2018037687A (ja) * | 2017-11-28 | 2018-03-08 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
WO2018168198A1 (ja) * | 2017-03-15 | 2018-09-20 | 東芝メモリ株式会社 | 半導体記憶装置 |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8334599B2 (en) * | 2008-08-21 | 2012-12-18 | Qimonda Ag | Electronic device having a chip stack |
KR20100048610A (ko) | 2008-10-31 | 2010-05-11 | 삼성전자주식회사 | 반도체 패키지 및 그 형성 방법 |
KR20100056247A (ko) * | 2008-11-19 | 2010-05-27 | 삼성전자주식회사 | 접착층을 구비하는 반도체 패키지 |
US8168470B2 (en) * | 2008-12-08 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound |
US20100206737A1 (en) * | 2009-02-17 | 2010-08-19 | Preisser Robert F | Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) |
KR101046385B1 (ko) * | 2009-03-31 | 2011-07-05 | 주식회사 하이닉스반도체 | 반도체 패키지 |
US8216912B2 (en) | 2009-08-26 | 2012-07-10 | International Business Machines Corporation | Method, structure, and design structure for a through-silicon-via Wilkinson power divider |
KR20110061404A (ko) | 2009-12-01 | 2011-06-09 | 삼성전자주식회사 | 칩 실리콘 관통 비아와 패키지간 연결부를 포함하는 반도체 패키지들의 적층 구조 및 그 제조 방법 |
CN102097335B (zh) * | 2009-12-10 | 2013-03-20 | 日月光半导体制造股份有限公司 | 封装结构及其封装工艺 |
TWI427753B (zh) * | 2010-05-20 | 2014-02-21 | Advanced Semiconductor Eng | 封裝結構以及封裝製程 |
JP2012054395A (ja) * | 2010-09-01 | 2012-03-15 | Nec Corp | 半導体パッケージ |
US8742535B2 (en) | 2010-12-16 | 2014-06-03 | Lsi Corporation | Integration of shallow trench isolation and through-substrate vias into integrated circuit designs |
US8987137B2 (en) | 2010-12-16 | 2015-03-24 | Lsi Corporation | Method of fabrication of through-substrate vias |
CN102157402B (zh) * | 2011-03-23 | 2013-02-13 | 南通富士通微电子股份有限公司 | 系统级封装方法 |
KR101649055B1 (ko) * | 2011-09-30 | 2016-08-17 | 인텔 코포레이션 | 실리콘 관통 비아 프로세싱 동안 장치 웨이퍼를 처리하기 위한 구조체 및 방법, 및 3d 패키징 구조체 |
US8796822B2 (en) | 2011-10-07 | 2014-08-05 | Freescale Semiconductor, Inc. | Stacked semiconductor devices |
US9076664B2 (en) * | 2011-10-07 | 2015-07-07 | Freescale Semiconductor, Inc. | Stacked semiconductor die with continuous conductive vias |
US9620430B2 (en) | 2012-01-23 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sawing underfill in packaging processes |
US8895360B2 (en) | 2012-07-31 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated semiconductor device and wafer level method of fabricating the same |
US9136213B2 (en) * | 2012-08-02 | 2015-09-15 | Infineon Technologies Ag | Integrated system and method of making the integrated system |
KR102007259B1 (ko) | 2012-09-27 | 2019-08-06 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
KR101994930B1 (ko) * | 2012-11-05 | 2019-07-01 | 삼성전자주식회사 | 일체형 단위 반도체 칩들을 갖는 반도체 패키지 |
KR102094924B1 (ko) * | 2013-06-27 | 2020-03-30 | 삼성전자주식회사 | 관통전극을 갖는 반도체 패키지 및 그 제조방법 |
KR102033789B1 (ko) * | 2013-07-25 | 2019-10-17 | 에스케이하이닉스 주식회사 | 적층형 패키지 및 그 제조방법 |
CN103413798B (zh) * | 2013-08-02 | 2016-03-09 | 南通富士通微电子股份有限公司 | 芯片结构、芯片封装结构 |
KR102036919B1 (ko) * | 2013-08-29 | 2019-11-26 | 에스케이하이닉스 주식회사 | 적층 패키지 및 제조 방법 |
US20150069609A1 (en) * | 2013-09-12 | 2015-03-12 | International Business Machines Corporation | 3d chip crackstop |
US9082757B2 (en) * | 2013-10-31 | 2015-07-14 | Freescale Semiconductor, Inc. | Stacked semiconductor devices |
US9356009B2 (en) * | 2014-05-27 | 2016-05-31 | Micron Technology, Inc. | Interconnect structure with redundant electrical connectors and associated systems and methods |
US10002653B2 (en) | 2014-10-28 | 2018-06-19 | Nxp Usa, Inc. | Die stack address bus having a programmable width |
JP6335099B2 (ja) | 2014-11-04 | 2018-05-30 | 東芝メモリ株式会社 | 半導体装置および半導体装置の製造方法 |
TWI721960B (zh) * | 2014-12-18 | 2021-03-21 | 日商新力股份有限公司 | 半導體裝置、製造方法及電子機器 |
US10074594B2 (en) * | 2015-04-17 | 2018-09-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
CN105161451B (zh) * | 2015-07-30 | 2017-11-07 | 通富微电子股份有限公司 | 半导体叠层封装方法 |
JP6443362B2 (ja) | 2016-03-03 | 2018-12-26 | 株式会社デンソー | 半導体装置 |
KR102570582B1 (ko) | 2016-06-30 | 2023-08-24 | 삼성전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
JP6981800B2 (ja) * | 2017-07-28 | 2021-12-17 | 浜松ホトニクス株式会社 | 積層型素子の製造方法 |
KR102464066B1 (ko) * | 2018-04-30 | 2022-11-07 | 에스케이하이닉스 주식회사 | 쓰루 몰드 비아를 포함하는 스택 패키지 |
KR102508552B1 (ko) * | 2018-04-30 | 2023-03-10 | 에스케이하이닉스 주식회사 | 쓰루 몰드 비아를 포함하는 스택 패키지 |
KR102534734B1 (ko) | 2018-09-03 | 2023-05-19 | 삼성전자 주식회사 | 반도체 패키지 |
JP7502478B2 (ja) * | 2021-02-05 | 2024-06-18 | 長江存儲科技有限責任公司 | フリップチップスタッキング構造体およびそれを形成するための方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003142647A (ja) * | 2001-11-01 | 2003-05-16 | Rohm Co Ltd | 半導体装置 |
JP2003249620A (ja) * | 2002-02-22 | 2003-09-05 | Toray Eng Co Ltd | 半導体の接合方法およびその方法により作成された積層半導体 |
JP2004228142A (ja) * | 2003-01-20 | 2004-08-12 | Fujitsu Ltd | 半導体素子およびマルチチップパッケージ |
JP2008135553A (ja) * | 2006-11-28 | 2008-06-12 | Fujitsu Ltd | 基板積層方法及び基板が積層された半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100364635B1 (ko) * | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
US6642081B1 (en) * | 2002-04-11 | 2003-11-04 | Robert Patti | Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
KR100537892B1 (ko) * | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | 칩 스택 패키지와 그 제조 방법 |
US20060284298A1 (en) * | 2005-06-15 | 2006-12-21 | Jae Myun Kim | Chip stack package having same length bonding leads |
JP4551321B2 (ja) * | 2005-07-21 | 2010-09-29 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
KR20070063748A (ko) * | 2005-12-15 | 2007-06-20 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 이의 제조 방법 |
KR100743648B1 (ko) * | 2006-03-17 | 2007-07-27 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 시스템 인 패키지의 제조방법 |
US7288835B2 (en) * | 2006-03-17 | 2007-10-30 | Stats Chippac Ltd. | Integrated circuit package-in-package system |
-
2007
- 2007-06-26 KR KR1020070063181A patent/KR100945504B1/ko not_active IP Right Cessation
- 2007-10-09 US US11/869,024 patent/US20090001602A1/en not_active Abandoned
- 2007-11-02 JP JP2007286726A patent/JP2009010312A/ja active Pending
- 2007-11-30 CN CN2007101962460A patent/CN101335262B/zh not_active Expired - Fee Related
-
2010
- 2010-10-20 US US12/908,340 patent/US20110033980A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003142647A (ja) * | 2001-11-01 | 2003-05-16 | Rohm Co Ltd | 半導体装置 |
JP2003249620A (ja) * | 2002-02-22 | 2003-09-05 | Toray Eng Co Ltd | 半導体の接合方法およびその方法により作成された積層半導体 |
JP2004228142A (ja) * | 2003-01-20 | 2004-08-12 | Fujitsu Ltd | 半導体素子およびマルチチップパッケージ |
JP2008135553A (ja) * | 2006-11-28 | 2008-06-12 | Fujitsu Ltd | 基板積層方法及び基板が積層された半導体装置 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010198869A (ja) * | 2009-02-24 | 2010-09-09 | Advanced Systems Japan Inc | スルーシリコンビア構造を有するウエハーレベルコネクタ |
US8871640B2 (en) | 2009-04-06 | 2014-10-28 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor chip |
JP2015176958A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2015188052A (ja) * | 2014-03-14 | 2015-10-29 | 株式会社東芝 | 半導体装置及びその製造方法 |
US9721935B2 (en) | 2014-03-14 | 2017-08-01 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US10128223B2 (en) | 2014-03-14 | 2018-11-13 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
WO2018168198A1 (ja) * | 2017-03-15 | 2018-09-20 | 東芝メモリ株式会社 | 半導体記憶装置 |
US11145625B2 (en) | 2017-03-15 | 2021-10-12 | Toshiba Memory Corporation | Semiconductor memory device |
US11594523B2 (en) | 2017-03-15 | 2023-02-28 | Kioxia Corporation | Semiconductor memory device |
JP2018037687A (ja) * | 2017-11-28 | 2018-03-08 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100945504B1 (ko) | 2010-03-09 |
CN101335262A (zh) | 2008-12-31 |
CN101335262B (zh) | 2012-05-30 |
US20110033980A1 (en) | 2011-02-10 |
KR20080114030A (ko) | 2008-12-31 |
US20090001602A1 (en) | 2009-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2009010312A (ja) | スタックパッケージ及びその製造方法 | |
JP5118942B2 (ja) | スルーシリコンビアスタックパッケージ及びその製造方法 | |
KR102593085B1 (ko) | 반도체 장치, 반도체 패키지 및 이의 제조 방법 | |
JP5179796B2 (ja) | 半導体パッケージの製造方法 | |
KR100914977B1 (ko) | 스택 패키지의 제조 방법 | |
JP3845403B2 (ja) | 半導体デバイス | |
US20140363922A1 (en) | Method for creating a 3d stacked multichip module | |
JP2008182224A (ja) | スタック・パッケージ及びスタック・パッケージの製造方法 | |
US20240055390A1 (en) | Manufacturing method of semiconductor device | |
KR100914987B1 (ko) | 몰드 재형상 웨이퍼 및 이를 이용한 스택 패키지 | |
KR100959606B1 (ko) | 스택 패키지 및 그의 제조 방법 | |
TWI544555B (zh) | 半導體封裝結構及其製造方法 | |
TW201931545A (zh) | 堆疊式封裝結構及其製造方法 | |
JP4334397B2 (ja) | 半導体装置及びその製造方法 | |
KR20090084645A (ko) | 스택 패키지의 제조방법 | |
KR20080036444A (ko) | 적층 칩 패키지 및 그 제조 방법 | |
JP2006041512A (ja) | マルチチップパッケージ用集積回路チップの製造方法及びその方法により形成されたウエハ及びチップ | |
KR101013548B1 (ko) | 스택 패키지 | |
US20240153919A1 (en) | Semiconductor package | |
KR20120022142A (ko) | 반도체칩 및 이의 제조방법 | |
KR101052867B1 (ko) | 스택 패키지 및 그의 제조 방법 | |
CN116825740A (zh) | 一种晶圆级封装结构及方法 | |
KR20110030088A (ko) | 반도체 패키지 및 그 제조방법 | |
US20110304027A1 (en) | Semiconductor chip with through electrodes and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20101014 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120125 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120131 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20120227 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20120418 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120427 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20121002 |