JP2012054395A - 半導体パッケージ - Google Patents

半導体パッケージ Download PDF

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Publication number
JP2012054395A
JP2012054395A JP2010195557A JP2010195557A JP2012054395A JP 2012054395 A JP2012054395 A JP 2012054395A JP 2010195557 A JP2010195557 A JP 2010195557A JP 2010195557 A JP2010195557 A JP 2010195557A JP 2012054395 A JP2012054395 A JP 2012054395A
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Japan
Prior art keywords
substrate
silicon
package
silicon substrate
semiconductor package
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Application number
JP2010195557A
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English (en)
Inventor
Shinji Tanaka
田中　　慎二
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NEC Corp
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NEC Corp
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Priority to JP2010195557A priority Critical patent/JP2012054395A/ja
Priority to US13/197,189 priority patent/US20120049368A1/en
Publication of JP2012054395A publication Critical patent/JP2012054395A/ja
Pending legal-status Critical Current

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Abstract

【課題】複数のシリコン基板同士の電気接続長を短くして、寄生容量を最小にするとともに、パッケージ基板全体の反りを抑制して接続信頼性を有する半導体パッケージを提供する。
【解決手段】半導体パッケージ９は、半導体素子を備えた複数のシリコン基板１を内蔵する半導体パッケージにおいて、第１のシリコン基板にシリコン貫通ヴィア２を備え、パッケージ基板を形成するコア基板１０の基材の線膨張係数が、３〜８ｐｐｍ／℃である。
【選択図】図１

Description

本発明は、半導体素子を備えた複数のシリコン基板を内蔵する半導体パッケージに関する。
集積回路（ＩＣ）の発明以来、半導体産業は、さまざまな電子部品（例えば、トランジスタ、ダイオード、抵抗器、コンデンサ等）の集積密度の連続的な改良により、急成長を遂げてきた。これら集積密度の改良は、より多くの構成要素が所定の領域に統合されるように、最小加工寸法（ｍｉｎｉｍｕｍ ｆｅａｔｕｒｅ ｓｉｚｅ）の縮小により、もたらされたものである。
これらの集積密度の改良は、二次元（２Ｄ）であり、集積された構成要素によって占められる体積ボリュームは、半導体ウエハの表面にある。リソグラフィーの向上は、２Ｄ集積回路の形成に大きな改良をもたらしたが、２次元で達成することができる密度には、物理的な制限がある。これらの制限の1つは、これらの構成要素を作製するのに必要な最小サイズである。また、1つのチップに入れるデバイスが多ければ多いほど、複雑な設計が必要となる。
複数のシリコン基板を一つのパッケージ基板に実装する方法として、ワイヤボンディングやシリコン貫通ヴィア（ＴＳＶｓ）を採用した、種々のスタックパッケージが提案されている。
従来における複数のシリコン基板を内蔵する半導体パッケージを図１９および図２０に示す。図１９は、シリコン基板がワイヤボンディングで接続された半導体パッケージを示している。図２０は、シリコン基板がシリコン貫通ヴィアを介して高さ方向へ積層される半導体パッケージを示している。
しかしながら、上記の複数のシリコン基板を内蔵する半導体パッケージにおいては、次のような問題点がある。
図１９の半導体パッケージは、ワイヤボンディング実装のため、高速伝送に適しておらず、また、パッケージ厚みや面積も大きくなるという問題点があった。
例えば、特許文献１には、パッケージ基板上に一つ以上の半導体チップが積層されたスタック・パッケージが記載されている。
しかしながら、特許文献１に記載のスタック・パッケージは、ワイヤボンディングによる実装であり、ワイヤ自身のインダクタンスのため、高速動作に向いていないという問題がある。また、ワイヤボンディングによる実装は、パッケージの厚みが厚くなるという問題点があった。
これを改良してシリコン貫通ヴィア（ＴＳＶｓ）を採用したパッケージを図２０に示す。図２０は、シリコン基板がシリコン貫通ヴィアを介して高さ方向へ積層される半導体パッケージであるが、シリコン基板を高さ方向へ積層するため、電気接続長が長くなるという問題点があった。
例えば、特許文献２には、チップ選択が容易な貫通シリコンビアチップスタックパッケージが記載されている。特許文献２に係る構造においては、複数のシリコン基板を実装するためには高さ方向に積み上げる必要があり、パッケージの厚みが厚くなるという問題がある。また、上に積み重ねたシリコン基板と、パッケージの基板の距離が長くなるため給電等の課題も生じる。
さらに、特許文献３には、シリコンウェハの両面を電極として用い厚み方向に通電する縦型の電力用半導体チップの製造方法が記載されている。特許文献３に記載の半導体チップは、特許文献２と同様の構造であるが、埋設した第１のシリコン基板とパッケージ基板の基材の熱膨張係数差により、第２のシリコン基板をパッケージ基板に接続する熱プロセスを通すと、パッケージ基板が凸方向に反ることが予想される。これによって、第２のシリコン基板接続面の平坦性（コプラナリティ）に影響が出るため、ハンダ接続信頼性が低下するという問題が生じる。特に、埋設するシリコン基板のサイズが大きくなると、パッケージ基板の反りも大きくなるため深刻な事態となる。
シリコン基板とパッケージ基板との熱膨張係数差により、パッケージ基板に反りが生じ、パンダ接続信頼性が低下するという問題があった。一般的にパッケージ基板を構成するコア基板の基材の線膨張係数は、１２〜１５ｐｐｍ／℃である。
特開２００９−１１１３９２号公報 特表２００９−４７２３号公報 特開２００４−１８６４４２号公報
上述のように、背景技術にかかるスタックパッケージは、高速動作に適しておらず、パッケージの厚みも厚くなるとともに、シリコン基板とパッケージ基板との熱膨張係数差により、パッケージ基板に反りが生じ、パンダ接続信頼性が低下するという問題があった。
本発明は、このような問題を解決するためになされたものであり、複数のシリコン基板同士の電気接続長を短くして、寄生容量を最小にするとともに、パッケージ基板全体の反りを抑制して接続信頼性を有する半導体パッケージを提供することを目的とする。
本発明に係る半導体パッケージは、半導体素子を備えた複数のシリコン基板を内蔵する半導体パッケージにおいて、第１のシリコン基板にシリコン貫通ヴィアを有し、前記パッケージ基板を形成するコア基板の基材の線膨張係数が３〜８ｐｐｍ／℃である。
本発明に係る半導体パッケージは、前記第１のシリコン基板は、シリコン貫通ヴィアと電気的に接続されたパッドを備えることが好ましい。
本発明に係る半導体パッケージは、前記パッドは銅パッドであることが好ましい。
本発明に係る半導体パッケージは、前記パッケージ基板のマイクロヴィアを介して第２のシリコン基板と電気的に接続されることが好ましい。
本発明によれば、シリコン貫通ヴィアを備えたシリコン基板をパッケージ基板内に内蔵することで、パッケージ基板あるいは第２のシリコン基板との電気的接続長を短くし、伝送路の持つ寄生容量を小さくするとともに、パッケージ基板を構成する基材の線膨張係数を特定し、シリコン基板に近い材料を選択することにより、パッケージ基板全体の反りを抑制して第２のシリコン基板の接続信頼性を確保することができる。
本発明の実施の形態１における半導体パッケージの断面図である。 図１の一部拡大断面図である。 図１の一部拡大断面図である。 本発明の実施の形態１に係る半導体パッケージの一部工程図である。 本発明の実施の形態１に係る半導体パッケージの一部工程図である。 本発明の実施の形態１に係る半導体パッケージの一部工程図である。 本発明の実施の形態１に係る半導体パッケージの一部工程図である。 本発明の実施の形態１に係る半導体パッケージの一部工程図である。 本発明の実施の形態１に係る半導体パッケージの一部工程図である。 本発明の実施の形態２に係る半導体パッケージの一部工程図である。 本発明の実施の形態２に係る半導体パッケージの一部工程図である。 本発明の実施の形態２に係る半導体パッケージの一部工程図である。 本発明の実施の形態１に係るセラミック材を採用した半導体パッケージの一部工程図である。 本発明の実施の形態１に係るセラミック材を採用した半導体パッケージの一部工程図である。 本発明の実施の形態１に係るセラミック材を採用した半導体パッケージの一部工程図である。 本発明の実施の形態１に係るセラミック材を採用した半導体パッケージの一部工程図である。 本発明の実施の形態１に係るセラミック材を採用した半導体パッケージの一部工程図である。 本発明の実施の形態１に係るセラミック材を採用した半導体パッケージの一部工程図である。 関連する技術に係る半導体パッケージである。 関連する技術に係る半導体パッケージである。
（実施の形態１）
図１を参照して、本発明の実施の形態に係る半導体パッケージの概要について説明する。図１は、本実施の形態における半導体パッケージの断面図である。
図1において、基板に内蔵されたシリコン基板１は、シリコン貫通ヴィア２を備えており、パッケージ基板のマイクロヴィア７を介して、第２のシリコン基板２０と電気的に接続している。また、コア基板１０を構成する基材の線膨張係数は３〜８ｐｐｍ／℃である。
ここで、基材の線膨張率が３ｐｐｍ／℃未満であると、本パッケージ基板を一般プリント配線板に実装する二次実装の接続信頼性で、一般プリント配線板の熱膨張係数（１２〜１６ｐｐｍ／℃）と差が大きくなり、この信頼性低下の点で好ましくなく、８ｐｐｍ／℃を超えると、シリコン基板とパッケージ基板との熱膨張係数差により、パッケージ基板に反りが大きくなる点で好ましくない。
図１において、シリコン基板１に背面パッド３が配置され、第１のシリコン基板のアンダーフィル５に第２のシリコン基板のハンダボール２１が埋め込まれている。また、シリコン基板下に第２のシリコン基板のアンダーフィル６が配置され、マイクロヴィア７の下方にＢＧＡボールが設置されている。
図２は、コア基板１０の拡大断面図である。図２により、内層に電源またはグランドのプレーン層１１と、接続用の貫通スルーホール１２を備えるコア基板１０が示される。ビルドアップ基板９は、コア基板１０とビルドアップ層から構成される。
コア基板１０を構成する基材は、線膨張係数３〜８ｐｐｍ／℃の材料を使用する。ここで、基材の線膨張係数が３〜８ｐｐｍ／℃であると、パッケージ基板内にシリコン基板を内蔵することにより生じるパッケージ基板の反りを抑制して第２のシリコン基板の接続信頼性を確保することができる。
具体的には、アラミド繊維不織布にエポキシなどの熱硬化性樹脂を含浸させたアラミド基板等の材料を用いるのが好ましい。
一般的に、コア基板１０の基材には１２〜１５ｐｐｍ／℃の材料を使用するが、線膨張係数が低い材料を採用しても、半導体パッケージの製造方法は変わらない。その製造方法は当業者に知られており、また本発明とは直接関係しないので、詳細な製造方法はここでは省略する。
図３は、第１のシリコン基板１の詳細図である。第1のシリコン基板１には、所定の機能を実現するための能動素子または受動素子が回路面２３に形成され、回路パターンを介して外部電極１９に接続されている。この外部電極１９は接続用ハンダボール４を備える。図３においては、素子や回路パターンは省略している。
また、ハンダボール４面と逆面になる背面１３側には、シリコン貫通ヴィア２を介して銅パッド３が設けられている。ハンダボール４は、錫-銀-銅合金、錫-鉛の共晶ハンダ、金-錫等のいずれでもよい。
次に、シリコン貫通ヴィア２の一般的な製造方法を簡単に説明する。シリコン基板の所定の位置に垂直の孔をエッチングにより形成し、上記の垂直孔の表面に絶縁膜を形成する。上記の絶縁膜上にシード金属層を形成した後、電解メッキによりシリコン貫通ヴィア２を形成する。なお、シリコン基板の背面側を化学研磨して前記シリコン貫通ヴィア２を露出させ、背面にも外部接続用の銅パッド３を形成する方法が一般的である。
図４は、コア基板１０に、シリコン貫通ヴィア２を備える第1のシリコン基板１を搭載する状態図である。コア基板１０と第1のシリコン基板１の間の線膨張係数の差が大きいと、凸方向にコア基板１０が反ってしまうが、コア基板１０の基材に線膨張係数が３〜８ｐｐｍ／℃である材料を使用することにより、この反りを抑制することができる。
図５は、コア基板１０と第1のシリコン基板１の間に接続信頼性向上や保持用を目的としたアンダーフィル樹脂６を充填して所定の温度でキュアして硬化させる状態図である。
図６は、第1の絶縁層１４を形成するために、フィルム状のビルドアップ樹脂を積層する状態図である。ビルドアップ樹脂はあらかじめ、第1のシリコン基板１が搭載される位置の樹脂を第1のシリコン基板１のサイズより、１ｍｍ程度大きく切り抜いておく。
図７は、第1の絶縁層１４にマイクロヴィア７を形成した図である。マイクロヴィア７はレーザーによる穴あけ、無電解銅メッキで下地金属を形成した後、メッキレジストでパターン形成し、パターンメッキでパターン回路と同時にマイクロヴィア形成を行う。
図８は、図７に重ねて、第２の絶縁層１５、マイクロヴィア７を形成する状態図である。このとき、第1のシリコン基板１の背面に露出しているシリコン貫通ヴィア２上の背面銅パッド３と同位置にレーザーで穴あけを行い、同様の方法でマイクロヴィア７を形成することによって、電気接続が可能である。ビルドアップ基板９表面には、マイクロヴィア７のランドが露出しており、実装用パッドとして機能させるためパッド表面はハンダが濡れ易いように無電解ニッケル-金メッキ処理、または無電解ニッケルーパラジウムー金メッキ処理、または水溶性プリフラックス（Ｏｒｇａｎｉｃ Ｓｕｒｆａｃｅ ｐｒｅｓｅｒｖａｔｉｖｅ）処理を行う。
図９は、ビルドアップ基板９に第２のシリコン基板２０をフェースダウンで実装する状態図である。第２のシリコン基板２０にはフリップチップ接続用のハンダボール２１を有している。
以上述べたように、パッケージ基板としてのビルドアップ基板は、当業者に知られており、また、本発明とは直接関係しないので、詳細な構成の説明は省略する。
第１のシリコン基板１には、キャパシタ、レジスタ、インダクタなど受動素子を形成し、第２のシリコン基板２０はメモリ、ＣＰＵなどの大規模集積回路としてもよい。
（実施の形態２）
本発明に係る実施の形態２は、その基本的構成については実施の形態１と同様であるが、パッケージ基板であるビルドアップ基板の製造容易性について更に向上することが可能である。
本実施の形態における構成を、図１２〜図１４に示す。
図１２において、第1のシリコン基板１を実装する位置は、ビルドアップ基板９のコア基板１０に内蔵している。その際、コア基板１０の内層に第1のシリコン基板実装用のパッド１７を形成しておき、コア基板１０完成後に、第1のシリコン基板実装用のキャビティ１６を設け、上記のパッド１７を露出させる。上記のパッド１７に第1のシリコン基板１を実装する。ビルドアップ層以降の形成は、図８に示す製造方法と同様である。
本実施の形態の基本的構成は、上述した通りであるが、パッケージ基板であるビルドアップ基板の代わりに、セラミック基板を採用することも可能である。
その構成を図１５〜図１８に示す。ここで、セラミック材料の線膨張係数は３〜８ｐｐｍ／℃である。
セラミック基板１８は、マイクロヴィア７とパターン回路を形成した０．１ｍｍ〜０．２ｍｍ厚のグリーンシート２２を所定の層数分を積層した後、一括焼成してセラミック配線板１８とする。
本実施の形態においては、表層の第1のシリコン基板を実装するエリアに、キャビティ１６を設け、内層に設けた第1のシリコン基板実装用パッド１７を露出させておく。
図１７は、第1のシリコン基板１を実装した後、アンダーフィル樹脂５で埋め込んだ状態図である。
次に研磨によって、セラミック基板の表面パッドと第1のシリコン基板１の背面に形成した背面銅パッド３の高さ方向の位置を揃えた後、第２のシリコン基板２０をフェースダウンで実装する（図１８）。
セラミック材料はアルミナの他、低温で一括焼成が可能なガラスセラミック材でもよい。
上記の実施の形態においては、コア基板１０と接続する外部端子はハンダボール４としたが、その他、金バンプによる圧着や導電性樹脂（ＡＣＦ）を採用してもよい。本接続方法は、絶縁層のキュア温度や第２のシリコン基板の接続温度を考慮して選択する。また、同様に第2のシリコン基板２０の外部端子も、ハンダボールでなく金バンプによる圧着や導電性樹脂（ＡＣＦ）を採用してもよい。
上記の実施の形態においては、半導体パッケージの外部端子は、ＢＧＡボール８にしているが、ＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）ソケット実装用のパッドに代替可能である。
以上説明したように、本実施の形態においては、内蔵されるシリコン基板に貫通ヴィアが設けられているので、第２のシリコン基板との電気的接続長を最短にでき、伝送路の持つ寄生容量を小さくできる。また、パッケージ基板を構成するコア基板の基材の線膨張係数を３〜８ｐｐｍ／℃とシリコン基板に近い材料を選択することにより、パッケージ基板内にシリコン基板を内蔵することで生じるパッケージ基板全体の反りを抑制し、第２のシリコン基板の接続信頼性を確保することができる。
具体的には、コア基板の線膨張係数は埋設する第1のシリコン基板の線膨張係数に近い材料を採用するので、第２のシリコン基板の接続信頼性を高めることができる。
また、第１のシリコン基板はシリコン貫通ヴィアを備えているので、パッケージ基板並びに第２のシリコン基板と最短の経路で電気的に接続できる。
さらに、第１のシリコン基板はシリコン貫通ヴィアを備え、基板内に内蔵されるので 実装面積が小さく薄い半導体パッケージが実現できる。
なお、本発明は上記実施の形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。
１ シリコン貫通ヴィアを備える第１のシリコン基板
２ シリコン貫通ヴィア
３ 背面銅パッド
４ 第１のシリコン基板のハンダボール
５ 第１のシリコン基板のアンダーフィル
６ 第２のシリコン基板のアンダーフィル
７ マイクロヴィア
８ ＢＧＡボール
９ ビルドアップ基板
１０ コア基板
１１ 内層プレーン
１２ 貫通スルーホール
１３ 背面
１４ 第１の絶縁層
１５ 第２の絶縁層
１６ セラミック基板のキャビティ
１７ 第１のシリコン基板搭載用パッド
１８ セラミック基板
１９ 外部電極
２０ 第２のシリコン基板
２１ 第２のシリコン基板のハンダボール
２２ グリーンシート
２３ 回路面

Claims (4)

  1. 半導体素子を備えた複数のシリコン基板を内蔵する半導体パッケージにおいて、
    第１のシリコン基板にシリコン貫通ヴィアを備え、
    パッケージ基板を形成するコア基板の基材の線膨張係数が、３〜８ｐｐｍ／℃である半導体パッケージ。
  2. 前記第１のシリコン基板は、シリコン貫通ヴィアと電気的に接続されたパッドを備えることを特徴とする請求項１に記載の半導体パッケージ。
  3. 前記パッドは銅パッドであることを特徴とする請求項２に記載の半導体パッケージ。
  4. 前記第１のシリコン基板は、前記パッケージ基板に形成されたマイクロヴィアを介して第２のシリコン基板と電気的に接続されることを特徴とする請求項１乃至３のいずれか１項に記載の半導体パッケージ。
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