JP5970071B2 - デバイス構造の製造方法および構造 - Google Patents

デバイス構造の製造方法および構造 Download PDF

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JP5970071B2
JP5970071B2 JP2014533278A JP2014533278A JP5970071B2 JP 5970071 B2 JP5970071 B2 JP 5970071B2 JP 2014533278 A JP2014533278 A JP 2014533278A JP 2014533278 A JP2014533278 A JP 2014533278A JP 5970071 B2 JP5970071 B2 JP 5970071B2
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support substrate
manufacturing
flat
device wafer
thermosetting material
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JP2014528644A (ja
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ジェイ． リー、ケビン
ジェイ． リー、ケビン
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Intel Corp
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Description

本発明は、３次元（３Ｄ）パッケージ化に関し、より詳細には、シリコン貫通電極（through-silicon vias：ＴＳＶ）に関する。
３Ｄパッケージ化は、システムオンチップ（ＳＯＣ）およびシステムインパッケージ（ＳＩＰ）に向けたマイクロエレクトロニクス開発の解決策として、出現した。特に、ＴＳＶを有する３Ｄフリップチップ構造は、広く適用される可能性がある。ＴＳＶ ３Ｄパッケージは、一般的に、垂直方向に積層された２つ以上のチップを含み、各チップ上の回路間の電気的接続を形成するエッジ配線に代えて、シリコン基板を貫通するビアを有する。
ＴＳＶ処理の間に、デバイスウェハは、薄くなるように加工され、典型的には、５０μｍから１００μｍの厚みになる。このように薄いウェハを安全に扱うためには、ウェハを平らに保持し、薄く壊れやすいウェハを、欠け、ひび等の機械的な損傷から保護するためのある種のサポートシステムが必要である。
現在のＴＳＶプロセスは、典型的には、デバイスウェハを仮接着剤を使用して仮支持ウェハに取り付けた後、プロセスフローの順番の最後において、薄く加工されたデバイスウェハを支持ウェハから取り外す工程を含む。薄く加工されたデバイスウェハを支持ウェハから取り外すのに、幾つかの実装形態を使用してもよい。
第１実装形態では、熱による取り外しが利用される。この実装形態では、デバイスウェハを仮支持ウェハに仮に接着するために、熱可塑性樹脂接着剤が使用される。ＴＳＶ処理が完了した後、熱を使用して接着剤を軟らかくして、薄く加工されたデバイスウェハを、仮支持ウェハから機械的に取り外す。
第２の実装形態では、紫外線（ＵＶ）による取り外しが利用される。この実装形態では、光−熱変換（light-to-heat conversion（ＬＴＨＣ））剥離コーティングと共にＵＶ硬化仮接着剤を使用して、デバイスウェハが、仮にガラス搬送ウェハに取り付けられる。ＴＳＶ処理が完了した後、ガラス搬送ウェハを貫通させたＬＴＨＣ層に対するレーザー照射が適用されて、ＬＴＨＣ層を弱くする。そして、ガラス搬送ウェハを薄く加工されたデバイスウェハからリフトオフして、薄く加工されたデバイスウェハからＵＶ硬化接着剤をはがす。
第３の実装形態では、溶媒による取り外しが利用される。この実装形態では、孔の開いた仮搬送ウェハに、仮接着剤を使用してデバイスウェハを取り付ける。ＴＳＶ処理が完了した後、仮搬送ウェハの孔を通じて溶媒を塗布して、仮接着剤を溶解し除去する。
上記の３つの実装形態のそれぞれにおいて、仮接着剤は、機械的に軟質であり、ＴＳＶ処理の間の、壊れやすいデバイスウェハに対する機械的損傷に対する最低限の保護を提供している。
本発明の実施形態に係る支持基板に対して接合を行う前の、反転させた状態のデバイスウェハを示した垂直断面図である。
本発明の実施形態に係る支持基板に対して接合された状態での、反転したデバイスウェハを示した垂直断面図である。
本発明の実施形態に係る支持基板に対して接合された状態での、反転したデバイスウェハのビア最終処理を示した垂直断面図である。
本発明の実施形態に係る支持基板を取り除いた後の、加工済みデバイスウェハを示した垂直断面図である。
本発明の実施形態に係るＴＳＶを実装する３Ｄパッケージの側面図である。
本発明の実施形態に係るシステムを示した図である。
様々な実施形態において、ＴＳＶ処理の間にデバイスウェハを扱う構造および方法について、図面を参照して説明する。しかしながら、ある実施形態では、これらの詳細事項の一以上が存在しなくとも実施可能であり、その他の周知の方法および材料の組み合わせを使用して実施されてもよい。以下の詳細な説明では、本発明の完全な理解を提供するべく、特定の材料およびプロセス等、数多くの詳細事項が記載される。また、本発明を不必要に不明瞭にするのを避けるべく、周知のパッケージ化プロセスおよび製造技術については、詳細に記載していない本明細書全体にわたって使用されている"一実施形態"または"ある実施形態"との言葉は、実施形態に関連する特定の特徴、構造、材料または特性が、少なくとも本発明の実施形態の一つに含まれていることを意味する。したがって、本明細書中の様々な箇所で使用されている"一実施形態"または"ある実施形態"というフレーズは、必ずしも本発明の同一の実施形態を示していない。また、本発明の１以上の実施形態において、特定の特徴、構造、材料または特性を好適に組み合わせてもよい。
"の上に（over）"、"〜まで（to）"、"〜の間（between）"、"〜上に（on）"という言葉は、一の層の、別の層に対する相対的な位置を指す場合がある。一の層が、別の層"の上に（over）"位置する、または、別の層に"接合される"という言葉は、一の層が直接、別の層に接触している場合、および、１以上の介在層を有する場合を含む。複数の層の"間に"存在する一の層という言葉は、一の層が直接、複数の層に接触している場合、および、１以上の介在層を有する場合を含む。一方、"第１の層が第２の層上に（on）存在する"という言葉は、第１の層が第２の層に接触することを意味する。
本発明の実施形態では、基板支持、および、デバイスウェハのＴＳＶ処理を機械的に維持するべく、機械的剛性および堅牢性を提供可能な、硬化された熱硬化性材料のような恒久的な接着剤を使用して、デバイスウェアを一時的に支持するための構造およびプロセスについて説明する。このようなプロセスは、恒久的な接着材料を使用して仮支持基板にデバイスウェハを取り付けること、および、ＴＳＶ処理が完了した後に、仮支持基板を取り外すこと、を伴う。"ビア最後"ＴＳＶ処理（金属配線構造の後にビアが形成される）について以下に詳細に例示および説明されるが、本発明の実施形態はこれに限定されず、本発明の実施形態は、"ビア最初"ＴＳＶ処理（マイクロ電子デバイスが形成される前に、ビアが形成される）および"ビア中間"ＴＳＶ処理（マイクロ電子デバイスの形成と金属配線構造の形成との間に、ビアが形成される）についても同様に利用可能である。更に、実施形態がＴＳＶ処理を参照して説明されるが、実施形態は、化合物ＩＩＩ−ＶウェハまたはＩＩ−ＶＩウェハのようなシリコン以外のウェハの基板にも適用可能である。
一実施形態において、前面、背面、マイクロ電子デバイス、および、背面と全面との間で半導体基板を貫通して延在するビア（例えば、ＴＳＶ）を有する半導体基板を含む構造について説明がなされる。半田リフローによる１以上のバンプが前面上に形成され、硬化済み熱硬化性材料が、前面上および１以上のリフローされた半田バンプの周辺に形成される。硬化済み熱硬化性材料および１以上のリフローされた半田バンプは共に、平坦な前側接合面を形成する。平坦な前側接合面は露出してよい。平坦な前側接合面は研磨面を有しないでよい。ある実施形態では、半導体基板は、上記のような構造を複数有するＴＳＶ加工デバイスウェハであってもよい。これに代えて、ＴＳＶ加工デバイスウェハは、複数の半導体基板を形成するべく個々に分割されてもよく、複数の半導体基板は複数のチップを形成するべく更に処理が施されても、施されなくてもよく、更に３Ｄパッケージ構造に組み込まれてもよい。したがって、一実施形態では、構造は、チップである。
一実施形態では３Ｄパッケージ構造は、基板、および、基板に平坦な前側接合面が取り付けられる上記の構造を有するチップを備えるとして説明される。このような実施形態では、１以上のチップが、互いに積層されていてもよい。
一実施形態では、デバイスウェハを、熱および圧力の下で、支持基板に接合する段階を含む方法が記載される。デバイスウェハは、前面、および、前面上に形成された１以上の半田バンプを有してもよい。支持基板は、平坦な濡れ面を有してもよい。熱硬化性材料の層が、平坦な濡れ面上に形成されてもよい。熱および圧力の下での接合の間、半田バンプは熱硬化性材料の層を貫通して、リフローの間に平坦な濡れ面にわたって拡がるまたは平坦な濡れ面を濡らして、熱硬化性材料を少なくとも部分的に硬化させる。平坦な濡れ面を半田バンプで濡らす段階と、熱硬化性材料を少なくとも部分的に硬化させる段階とを同時に行ってよい。支持基板は、一の面全体にわたって平坦な濡れ面を有してよい。そして、支持基板が除去されて、リフローされた半田バンプおよび少なくとも部分的に硬化された熱硬化性材料を有する平坦な前側接合面が露出される。ビア最後プロセスフローでは、接合の後であって、支持基板の除去の前に、１以上のビアを、デバイスウェハの前面および背面の間に延在するように形成してもよい。ビアを形成する前に、デバイスウェハの厚みを低減させるべく、デバイスウェハの背面に対して、研削または化学機械研磨（ＣＭＰ）処理を行ってもよい。ビア最初またはビア中間プロセスフローでは、接合の前に、１以上のビアが、デバイスウェハの前面と背面との間に延在するように形成されてもよい。
図１から５を参照して、製造方法について説明する。図１には、支持基板２００の上に反転した状態のデバイスウェハ１００が示されている。デバイスウェハ１００は、前面１０２および背面１０４を有してもよい。デバイスウェハ１００は、様々な形態を有してもよい。例えば、デバイスウェハは、バルク半導体であってもよく、バルク半導体上に形成されたエピタキシャル層を有してもよい、またはsemiconductor-on-insulator（ＳＯＩ）構造を有してもよく、その他の構造が使用されてもよい。図示された特定の実施形態では、デバイスウェハ１００は、絶縁層１１４に積層された半導体層１１６およびバルク基板１１８を含む（ＳＯＩ）構造を有してもよい。デバイスウェハ１００は更に、金属−絶縁体−半導体電界効果トランジスタ（ＭＯＳＦＥＴ）、キャパシタ、インダクタ、抵抗器、ダイオード、micro-electro-mechanical system（ＭＥＭＳ）、その他の能動または受動素子およびこれらの組み合わせのような様々なマイクロ電子デバイスを形成するべく、ドープ領域またはその他のドープ構造を有してもよい。
基板１００の前面１０２上に、金属配線構造１１２が形成されてもよい。図に示すように、金属配線構造１１２は、銅、アルミニウム等の導電金属で形成された複数の配線層、および、酸化シリコン、炭素ドープ酸化物、シリコン窒化物等の層間絶縁材料を含む。物理的および化学的保護を提供するべく、金属配線構造１１２の上に、パッシベ―ション層１１３が形成されてもよい。パッシベ―ション層１１３に形成された開口上に、１以上の導電パッド１０８（例えば、銅、アルミニウム等）が設けられてもよく、導電パッド１０８上に１以上の半田バンプ１０６が形成されてもよい。
支持基板２００は、リフローの間に半田バンプ１０６材料に対して許容される接着力を有する材料から形成された平坦な濡れ面２０２を有してもよく、半田バンプ１０６が、リフローの間に平坦な濡れ面２０２にわたって拡がり、濡れ面を濡らす。ある実施形態では、半田バンプ１０６は、スズを基本とする材料、鉛スズを基本とする材料、インジウムを基本とする材料または鉛を基本とする材料から形成されてもよい。このような実施形態では、平坦な濡れ面２０２は、ニッケル、金、プラチナ、パラジウム、コバルト、銅、鉄および鋼のような半田濡れ性を有する金属から形成されてもよい。また、平坦な濡れ面２０２を、リフローの間に半田バンプ１０６に対して十分な接着性を有するものとして利用することができる。
平坦な濡れ面２０２は、支持基板２００と一体的に形成されてもよい。例えば、支持基板２００は、例えば、滑らかな平坦な濡れ面２０２を有する、銅のようなバルク金属で形成されてもよい。平坦な濡れ面２０２はまた、バルク基板２０６の上に、別の層２０４として形成されてもよい。層２０４は、濡れ性または研磨に適した望ましい特性を有してもよい。バルク基板２０６および層２０４を形成するための材料は、コスト、エッチング特性、および、デバイスウェハを支持基板に接合した後での取り外しの容易さ等に基づいて、選択されてもよい。
図１を再び参照し、熱硬化性材料２０８の層が、平坦な濡れ面２０２上に形成される。熱硬化性材料２０８の層は、これに限定されないが、エポキシ樹脂、フェノール樹脂、ポリイミドおよびポリベンゾオキサゾール（ＰＢＯ）のような、好適なアンダーフィルタイプまたはバッファコーティングタイプの材料で形成されてもよい。熱硬化性材料２０８の層を、スピンコーティングおよびシート積層のような様々な態様で塗布してもよい。また、平坦な濡れ面２０２に塗布される前または塗布された後に、熱硬化性材料２０８の層が、Ｂステージ硬化されてもよい。
図２には、熱および圧力の下で、デバイスウェハ１００が支持基板２００に接合される様子が示されている。図に示されるように、複数の半田バンプ１０６が、リフローの間に、熱硬化性材料２０８の層を貫通して、平坦な濡れ面２０２に拡がるまたは濡れ面を濡らしている。同時に、熱硬化性材料２０８の層は、少なくとも部分的に硬化されている。
本発明の実施形態によれば、接合は、ウェハのスケールで実行され、ボンドヘッドが、デバイスウェハ１００の背面１０４を持ち上げ、デバイスウェハ１００を支持基板２００上に配置して、支持基板２００は台座によって支持される。特定の熱接合プロファイルは、半田バンプ１０６および熱硬化性材料２０８の種類に依存すると考えられる。熱圧着（ＴＣＢ）プロセスの一例では、支持基板２００が、例えば、ステージ化温度１００℃に保持される。デバイスウェハ１００は、例えば、ステージ化温度１００℃で、ボンドヘッドを使用してピックアップされてもよい。そして、デバイスウェハ１００が、支持基板２００の上に配置された後で、ボンドヘッド温度が、半田バンプ１０６の液相温度を上回る温度（例えば、２５０℃から３００℃）へと上昇させる。ボンドヘッド温度を、半田の液相温度を上回る温度（ＴＡＬ）に一定期間維持した後、ボンドヘッド温度を半田バンプ１０６の液相温度を下回る温度（例えば、１８０℃）へと下げる。この時点で、接合された構造がオフライン硬化のために台座から取り除かれてもよいし、熱硬化性材料２０８を実質的に完全に硬化させるべく、インラインの態様で上昇させた温度で台座上に保持してもよい。
図３には、デバイスウェハ１００に処理が行われて、ウェハの前面１０２と背面１０４との間に延在する少なくとも１つのビア１２０（例えば、ＴＳＶ）を形成する"ビア最後処理"が例示されている。図３には、ビア１２０が１つのみ示されているが、これは図示の目的のためであり、本発明の実施形態に係るデバイスウェハには、複数のビアが形成されてもよい。また、"ビア最後処理"が図示されているが、本発明の実施形態は、デバイスウェハ１００が支持基板２００に接合される前に、ビア１２０が形成される"ビア最初"処理および"ビア中間"処理にも適用可能である。
ビア１２０の形成の前に、背面１０４を研削および／または化学機械研磨（ＣＭＰ）することにより、デバイスウェハ１００を薄くしてもよい。例えば、一実施形態では、デバイスウェハ１００を、約５０μｍから１００μｍにまで薄くしてもよい。デバイスウェハ１００を薄く加工した後、パッシベーション膜または積層膜１３０を、背面１０４の上に形成して、気密バリアを提供してもよい。図示されていないが、デバイスウェハ１００に更に処理を行い、再分配線（redistribution lines：ＲＤＬ）およびその他のビルドアップ構造を、ビア１２０の処理の前後または間に形成してもよい。
ビア１２０を形成するために、フォトレジスト材料を、薄く加工されたデバイスウェハ１００の背面１０４の上に形成した後、フォトレジスト材料を、露光および現像してもよい。現像の後には、レジストコーティングのビア１２０を設けることを望む位置に、開口が存在する。シリコンデバイスウェハの場合、パッシベーション膜または積層膜１３０を貫通しバルクシリコン１１８を貫通するようにプラズマエッチングし、薄く加工されたデバイスウェハ１００の前面１０２（デバイス側）上の銅のランディングパッドでエッチングを止めることにより、シリコン貫通電極（ＴＳＶ）開口を形成する。そして、フォトレジストを除去し、残りのエッチングポリマーまたは残留物を、デバイスウェハ１００から取り除く。そして、絶縁層１２４をウェハ表面に堆積させて、シリコン貫通電極（ＴＳＶ）１２０の底面および側壁をライニング（lining）する。好適な材料としては、これに限定されないが、二酸化シリコン、シリコン窒化物、炭化ケイ素および様々なポリマーが挙げられる。これらの材料を、化学気相堆積（ＣＶＤ）法、原子層堆積（ＡＬＤ）法またはスピンコーティング法により、堆積させることができる。
そして、異方性エッチングプロセスを使用して、ＴＳＶ１２０の底面およびパッシベーション膜または積層膜１３０上から絶縁層１２４を除去すると同時に、ＴＳＶ１２０の側壁においては、ある程度の厚みの絶縁層を残す。次いで、バリア層１２６およびシード層を、デバイスウェハの表面に堆積してもよい。例えば、バリア層１２６は、タンタル、チタンまたはコバルトを含む。シード層は、例えば、銅であってもよい。そして、デバイスウェハの表面に、銅のブランケット層を電気めっきで形成して、ＴＳＶを完全に銅１２２で満たす。図３に示すように、銅およびバリア層の表に出た余計な部分は、ＣＭＰにより取り除く。
図４に示すように、薄く加工されたデバイスウェハ１００の処理が完了すると、支持基板２００が選択的に取り除かれる。一実施形態では、支持基板２００は銅であり、例えば、Ｔｒａｎｓｃｅｎｅ社の銅エッチング液４９−１のようなウェットエッチング液を使用して支持基板を選択的にエッチングするが、実質的に影響を受けないリフローされた半田バンプ１０６および硬化済み熱硬化性材料２０８は残すようにして、支持基板を取り除く。別の実施形態では、支持基板２００は、薄層２０４を有する金属またはプラスチック材料のようなバルク基板２０６で形成される。バルク基板２０６がプラスチック材料である場合、溶媒を使用して、バルク基板２０６を除去した後、薄層２０４を除去するべく、ウェットエッチングを行ってもよい。いずれの態様において、支持基板２００を取り除くことにより、リフローされた半田バンプ１０６および少なくとも部分的に硬化された熱硬化性材料２０８を含む平坦な前側接合面１４０が露出される。多くの実施形態において、熱硬化性材料２０８は、支持基板２００が除去される前に、すでに完全に硬化されている。
支持基板２００の除去の後、基板１００上に形成された得られた複数の構造を、個々に分離してもよく、チップ５００を形成するべく更に処理を行ってもよいし、行わなくてもよく、得られたチップは、３Ｄパッケージ構造に組み込まれてもよい。例えば、得られた構造に更に処理を施して、平坦な前側接合面１４０または背面１０４の上に、ビルドアップ構造を含めてもよい。３Ｄパッケージ構造の一例が図５に示されており、本発明の実施形態に従って形成されたＴＳＶを含む１以上のチップ５００が、基板６００の上に積み重ねられており、半田要素５０２と接続されている。基板６００は、例えば、プリント回路基板または積層基板である。
図６には、本発明の一実施形態に係るコンピュータシステムが示されている。システム６９０は、プロセッサ６１０、メモリデバイス６２０、メモリコントローラ６３０、グラフィックスコントローラ６４０、入出力（Ｉ／Ｏ）コントローラ６５０、ディスプレイ６５２、キーボード６５４、ポインティングデバイス６５６および周辺機器６５８を含み、これらは、ある実施形態では、バス６６０を介して互いに通信可能に結合されていてもよい。プロセッサ６１０は、汎用プロセッサまたは特定用途向け集積回路（ＡＳＩＣ）であってもよい。Ｉ／Ｏコントローラ６５０は、有線通信または無線通信のための、通信モジュールを含んでもよい。メモリデバイス６２０は、ダイナミックランダムアクセスメモリ（ＤＲＡＭ）デバイス、スタティックランダムアクセスメモリ（ＳＲＡＭ）デバイス、フラッシュメモリデバイス、または、これらメモリデバイスの組み合わせであってもよい。したがって、ある実施形態では、システム６９０内のメモリデバイス６２０は、ＤＲＡＭデバイスを含む必要がない。
システム６９０に示される構成要素の１以上は、例えば、図５のチップ５００または３Ｄパッケージ構造のような１以上の集積回路パッケージに含まれてもよい、および／または、含んでもよい。例えば、プロセッサ６１０、メモリデバイス６２０、Ｉ／Ｏコントローラ６５０の少なくとも一部、または、これら構成要素の組み合わせが、上記の様々な実施形態で説明された構造の少なくとも１つの実施形態を含む集積回路パッケージに含まれてもよい。
これら要素は、当技術分野でよく知られた従来の機能を有する。詳細には、メモリデバイス６２０は、ある場合には、本発明の実施形態に係るパッケージ構造を形成する方法のための実行可能命令を長期的に格納する場所として使用されてもよい。その他の実施形態では、メモリデバイス６２０は、プロセッサ６１０によって実行される間、本発明の実施形態に係るパッケージ構造を形成するための方法の実行命令を、短期間格納するのに使用されてもよい。加えて、命令は、格納されてもよいし、システムと通信可能に接続された機械アクセス可能媒体と関連付けられてもよく、そのような媒体の例としては、コンパクトディスクリードオンリーメモリ（ＣＤ−ＲＯＭ）、ＤＶＤ（digital versatile disk）、フロッピー（登録商標）ディスク、搬送波、および／または、その他の伝播信号が挙げられる。一実施形態において、メモリデバイス６２０は、プロセッサ６１０に、実行のために実行可能命令を供給してもよい。
システム６９０は、コンピュータ（例えば、デスクトップ、ラップトップ、ハンドヘルドサーバ、ウェブアプリケーション、ルータ等）、無線通信デバイス（例えば、携帯電話、コードレス電話、ポケットベル（登録商標）、パーソナルデジタルアシスタンス（ＰＤＡ）等）、コンピュータ周辺機器（例えば、プリンタ、スキャナ、モニタ等）、エンターテイメントデバイス（例えば、テレビ、ラジオ、ステレオ、テープおよびコンパクトディスクプレーヤ、ビデオカセットレコーダ、ビデオカメラ、ＭＰ３（Motion Picture Experts Group, Audio Layer 3）プレーヤ、ビデオゲーム、腕時計等）を含んでもよい。
本発明が、構造的特徴および／または方法の動作として具体的に説明されたが、添付の特許請求の範囲に規定される発明は、必ずしも、説明された特定の特徴または動作に限定されない。開示された特定の特徴および動作は、本発明を例示すために有用な、特許請求される発明の正常な実装形態として理解されるべきである。

Claims (21)

  1. 前面、背面、マイクロ電子デバイス、および、前記背面と前記前面との間に半導体基板を貫通して延在するビア、を有する前記半導体基板と、
    前記前面の上に形成された半田バンプと、
    前記前面の上および前記半田バンプの周辺に形成された硬化済み熱硬化性材料と、を備え、
    前記硬化済み熱硬化性材料と前記半田バンプとが、露出した平坦な前側接合面を形成する、構造。
  2. 前記平坦な前側接合面は、研磨面を有さない、請求項１に記載の構造。
  3. 前記ビアが、銅を含む、請求項１または２に記載の構造。
  4. 前記硬化済み熱硬化性材料が、硬化済みエポキシ樹脂、硬化済みフェノール樹脂、硬化済みポリイミドおよび硬化済みポリベンゾオキサゾール（ＰＢＯ）からなる一群から選択される、請求項１から３の何れか一項に記載の構造。
  5. 基板と、
    チップと、を備える３Ｄパッケージ構造であって、
    前記チップは、
    前面、背面、マイクロ電子デバイス、および、前記背面と前記前面との間に半導体基板を貫通して延在するビア、を含む前記半導体基板と、
    前記前面の上に形成された半田バンプと、
    前記前面の上および前記半田バンプの周辺に形成された硬化済み熱硬化性材料と、を有し、
    前記硬化済み熱硬化性材料と前記半田バンプとが、露出した平坦な前側接合面を形成し、
    前記平坦な前側接合面は、前記基板に取り付けられる、３Ｄパッケージ構造。
  6. 前記チップに積層された第２のチップを更に備える、請求項５に記載の３Ｄパッケージ構造。
  7. 前記３Ｄパッケージ構造に通信可能に接続されたバスを有するシステムを更に備える、請求項６に記載の３Ｄパッケージ構造。
  8. 前面および前記前面の上に形成された半田バンプを有するデバイスウェハを準備する段階と、
    上に熱硬化性材料の層が形成される平坦な濡れ面を有する支持基板を準備する段階と、
    熱および圧力の下で、前記デバイスウェハを前記支持基板に接合する段階と、
    前記支持基板を取り除いて、リフローされた前記半田バンプおよび少なくとも部分的に硬化された前記熱硬化性材料とを有する平坦な前側接合面を露出させる段階と、を備え、
    前記接合する段階は、
    前記半田バンプを、前記熱硬化性材料の層に貫通させる段階と、
    前記半田バンプのリフローの間に、前記平坦な濡れ面を前記半田バンプで濡らす段階と、
    前記熱硬化性材料を少なくとも部分的に硬化させる段階とを有する、デバイス構造の製造方法。
  9. 前記平坦な濡れ面を前記半田バンプで濡らす段階と、前記熱硬化性材料を少なくとも部分的に硬化させる段階とを同時に行う、請求項８に記載のデバイス構造の製造方法。
  10. 前記支持基板は、一の面全体にわたって前記平坦な濡れ面を有する、請求項８または９に記載のデバイス構造の製造方法。
  11. 前記デバイスウェハを前記支持基板に接合する段階の後に、前記デバイスウェハの前記前面と背面との間に延在するビアを形成する段階を更に備える、請求項８から１０の何れか一項に記載のデバイス構造の製造方法。
  12. 前記支持基板を取り除く段階の前に、前記ビアを形成する段階を備える、請求項１１に記載のデバイス構造の製造方法。
  13. 前記デバイスウェハを前記支持基板に接合する段階の後であって、前記ビアを形成する段階の前に、前記デバイスウェハの厚みを低減させるべく、前記デバイスウェハの背面を研削または研磨する段階を備える、請求項１１または１２に記載のデバイス構造の製造方法。
  14. 前記デバイスウェハを前記支持基板に接合する段階の前に、前記デバイスウェハの前記前面および背面の間に延在するビアを形成する段階を更に備える、請求項８から１０の何れか一項に記載のデバイス構造の製造方法。
  15. 前記平坦な濡れ面は、ニッケル、金、プラチナ、パラジウム、コバルト、銅、鉄および鋼からなる一群から選択される材料を含む、請求項８から１４の何れか一項に記載のデバイス構造の製造方法。
  16. 前記支持基板は、バルク基板である、請求項８から１５の何れか一項に記載のデバイス構造の製造方法。
  17. 前記バルク基板は、銅である、請求項１６に記載のデバイス構造の製造方法。
  18. 前記支持基板は、バルク基板、および、前記平坦な濡れ面を含むコーティング層を有する、請求項８から１５の何れか一項に記載のデバイス構造の製造方法。
  19. 前記支持基板の前記平坦な濡れ面上に、前記熱硬化性材料の層を、スピンコーティングまたは積層する段階を更に備える、請求項８から１８の何れか一項に記載のデバイス構造の製造方法。
  20. 前記デバイスウェハを前記支持基板に接合させる段階の前に、前記熱硬化性材料の層がＢステージ硬化される、請求項１９に記載のデバイス構造の製造方法。
  21. 第１のダイを、前記平坦な前側接合面に取り付ける段階と、
    第２のダイを、前記デバイスウェハの背面に取り付ける段階と、を更に備える請求項８から２０の何れか一項に記載のデバイス構造の製造方法。
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