CN103988299B - 用于操纵极薄器件晶片的方法 - Google Patents

用于操纵极薄器件晶片的方法 Download PDF

Info

Publication number
CN103988299B
CN103988299B CN201180075117.0A CN201180075117A CN103988299B CN 103988299 B CN103988299 B CN 103988299B CN 201180075117 A CN201180075117 A CN 201180075117A CN 103988299 B CN103988299 B CN 103988299B
Authority
CN
China
Prior art keywords
device wafer
support substrate
plane
moistening
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201180075117.0A
Other languages
English (en)
Other versions
CN103988299A (zh
Inventor
K·J·李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN103988299A publication Critical patent/CN103988299A/zh
Application granted granted Critical
Publication of CN103988299B publication Critical patent/CN103988299B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/271—Manufacture and pre-treatment of the layer connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01026—Iron [Fe]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Abstract

描述了在穿硅过孔(TSV)处理期间操纵器件晶片的结构和方法，其中使用永久热固性材料来将器件晶片接合到临时支撑衬底。当移除临时支撑衬底后，暴露出包括回流焊料凸起和永久热固性材料的平面前侧接合表面。

Description

用于操纵极薄器件晶片的方法
技术领域
本发明涉及三维(3D)封装，且更具体地涉及穿硅过孔(TSV)的集成。
背景技术
3D封装作为对朝着片上系统(SOC)和封装中系统(SIP)的微电子发展的解决方案而出现。特别是，具有TSV的3D倒装芯片结构有可能被广泛采用。TSV3D封装通常包含垂直地叠置的两个或多个芯片，其中穿硅衬底过孔代替边缘布线以产生在每个芯片上的电路元件之间的电连接。
在TSV处理期间，器件晶片一般在厚度上被减薄回到50-100μm。在没有某种类型的支撑系统保持晶片平坦并保护易碎的减薄的晶片使其免受机械损坏(例如切削、破裂等)的情况下，这样薄的晶片不能被成功地操纵(handle)。
当前TSV工艺一般包括使用临时粘合剂将器件晶片附着到临时支撑晶片并接着在工艺流程序列结束时将减薄的器件晶片从支撑晶片分离。有几种实现方式可用于将减薄的器件晶片从支撑晶片分离。
在第一实现方式中，使用热释放。在这个实现方式中，热塑性粘合剂用于将器件晶片临时接合到临时支撑晶片。一旦完成TSV处理，就使用热来软化粘合剂，且接着将减薄的晶片从临时支撑晶片机械地分离。
在第二实现方式中，使用紫外(UV)释放。在这个实现方式中，器件晶片使用UV可固化的临时粘合剂结合光到热转换(LTHC)释放涂层附着到临时玻璃载体晶片。在完成TSV处理之后，将激光辐射穿过玻璃载体晶片应用于LTHC层，因而使它变弱。玻璃载体接着从减薄的器件晶片剥离，且然后UV可固化粘合剂从减薄的器件晶片剥离。
在第三实现方式中，使用溶剂释放。在这个实现方式中，使用临时粘合剂将器件晶片附着到穿孔的临时载体晶片。一旦完成TSV处理，就通过临时载体晶片中的穿孔来涂覆溶剂以溶解掉临时粘合剂。
在这三个实现方式的每个中，临时粘合剂在机械方面都是软的，并且向易碎的器件晶片提供针对TSV处理期间的机械损坏的最低的保护。
附图说明
图1是根据本发明的实施例的在接合到支撑衬底之前的倒置器件晶片的截面侧视图。
图2是根据本发明的实施例的接合到支撑衬底的倒置器件晶片的截面侧视图。
图3是根据本发明的实施例的接合到支撑衬底的倒置器件晶片的后过孔处理的截面侧视图。
图4是根据本发明的实施例的在移除支撑衬底之后的经处理的器件晶片的截面侧视图。
图5是根据本发明的实施例的实现TSV的3D封装的侧视图。
图6表示根据本发明的实施例的系统。
具体实施方式
在各种实施例中，参考附图描述了在TSV处理期间操纵器件晶片的结构和方法。然而，某些实施例可在没有这些特定细节中的一个或多个的情况下或结合其它已知的方法和材料来实施。在下面的描述中，阐述了很多特定的细节，例如特定的材料和工艺等，以便提供对本发明的彻底理解。在其它例子中，没有特别详细地描述公知的封装工艺和制造技术，以便不没有必要地使本发明难以理解。在整个本说明书中对“实施例”或“一个实施例”的提及意指关于该实施例描述的特定的特征、结构、材料或特性包括在本发明的至少一个实施例中。因此，短语“在实施例中”或“在一个实施例中”在整个本说明书中的不同地方的出现并不一定指本发明的同一实施例。此外，特定的特征、结构、材料或特性可在一个或多个实施例中以任何适当的方式组合。
本文使用的术语“在…之上”、“到”、“在…之间”和“在…上”可以指一层相对于其它层的相对位置。在另一层“之上”或接合“到”另一层的一层可直接与另一层接触或可具有一个或多个中间层。在层“之间”的一层可直接与层接触或可具有一个或多个中间层。相反，在第二层“上”的第一层与该第二层接触。
根据本发明的实施例，描述了用于使用衬底支撑物和永久粘合材料(例如固化的热固性材料)来临时支撑器件晶片的结构和过程，固化热固性材料可提供机械刚度和硬度来机械地支持器件晶片的TSV处理。这样的过程可涉及使用永久粘合材料将器件晶片附着到临时支撑结构，以及一旦完成TSV处理就接着使临时支撑结构分离。应认识到，虽然详细描述和示出了“后过孔”TSV处理(在金属化结构之后制造过孔)，本发明的实施例并不受限限于此，并且本发明的实施例也与“先过孔”TSV处理(在形成微电子器件之前制造过孔)和“中间过孔”TSV处理(在形成微电子器件和金属化结构之间制造过孔)兼容。此外，虽然参考TSV处理描述了实施例，实施例也可应用于除了硅晶片以外的衬底，例如化合物III-V晶片或II-VI晶片。
在实施例中，描述了包括半导体衬底的结构，半导体衬底具有前表面、后表面、微电子器件和穿过半导体衬底在后表面和前表面之间延伸的过孔(TSV)。一个或多个回流焊料凸起形成在前表面之上，且固化的热固性材料形成在前表面之上和一个或多个回流焊料凸起周围。固化的热固性材料和一个或多个回流焊料凸起一起形成平面前侧接合表面。在一些实施例中，半导体衬底可以是包括多个所述结构的经TSV处理的器件晶片。或者，经TSV处理的器件晶片被分割以形成可以或可以不被进一步处理以形成多个芯片的多个半导体衬底，所述多个芯片随后可集成到3D封装结构中。因此，在实施例中，所述结构是芯片。
在实施例中，描述了包括衬底和芯片的3D封装结构，所述芯片包括前面描述的结构，其中平面前侧接合表面附着到衬底。在这样的实施例中，一个或多个额外的芯片可接着叠置在芯片之上。
在实施例中，描述了一种方法，其包括在热和压力之下将器件晶片接合到支撑衬底。器件晶片可包括前表面和在前表面之上形成的一个或多个焊料凸起。支撑衬底可包括平面润湿表面。热固性材料层可形成在平面润湿表面上。在热和压力之下接合期间，焊料凸起穿透该热固性材料层并在回流期间散布在整个平面润湿表面上或润湿平面润湿表面，且热固性材料至少部分地被固化。衬底支撑物可接着被移除以暴露包括回流焊料凸起和至少部分地固化的热固性材料的平面前侧接合表面。在后过孔工艺流程中，可形成一个或多个过孔以在接合支撑衬底之后和移除支撑衬底之前在器件晶片的前表面和后表面之间延伸。应认识到，可在器件晶片的后表面上执行研磨或化学机械抛光(CMP)操作，以在形成过孔之前减小器件晶片的厚度。在先过孔或中间过孔工艺流程中，在接合之前可能已经形成在器件晶片的前表面和后表面之间延伸的一个或多个过孔。
现在参考图1-5，参考附图描述了制造方法。如在图1中示出的，倒置器件晶片100被示为在支撑衬底200之上。器件晶片100可包括前表面102和后表面104。器件晶片100可具有各种形成物。例如，器件晶片可以是体半导体，包括覆在体半导体上面的外延层，或包括绝缘体上半导体(SOI)结构，虽然也可使用其它结构。在所示的特定实施例中，器件晶片100包括(SOI)结构，其包括覆在绝缘体层114上面的半导体层116以及体衬底118。器件晶片100可此外包括掺杂区或其它掺杂特征以形成各种微电子器件，例如金属-绝缘体-半导体场效应晶体管(MOSFET)、电容器、电感器、电阻器、二极管、微机电系统(MEMS)、其他适当的有源或无源器件，以及它们的组合。
金属化结构112可形成在衬底100的前表面102之上。如图所示，金属化结构112包括由导电材料(例如铜、铝等)和层间电介质材料(例如氧化硅、掺碳氧化物、氮化硅等)形成的多个互连层。钝化层113可在金属化结构112的上部分上形成以提供物理和化学保护。一个或多个导电焊盘108(例如铜、铝等)可设置在钝化层113中的开口之上，且一个或多个焊料凸起106可形成在导电焊盘108上。
支撑衬底200可包括平面润湿表面202，其在回流期间由具有与焊料凸起106的材料的可接受的粘合力的材料形成，使得焊料凸起106在回流期间散布在整个平面润湿表面202上或润湿平面润湿表面202。在一些实施例中，焊料凸起106可以是基于锡的、基于铅-锡的、基于铟的或基于铅的材料。在这样的实施例中，平面润湿表面202可由焊料可润湿金属(例如镍、金、铂、钯、钴、铜、铁和钢)形成。还设想可利用在回流期间具有对焊料凸起106的足够的粘合性的非金属平面润湿表面202。
平面润湿表面202可与体支撑衬底200一体地形成。例如，支撑衬底200可以是例如具有平滑的平面润湿表面202的体金属，例如铜。平面润湿表面202也可被形成为在体衬底206之上的单独层204。层204可具有用于湿润或抛光的优选特性。用于形成体衬底206和层204的材料也可基于其成本、蚀刻特性和在将器件晶片接合到衬底支撑物之后移除的容易性来选择。
仍然参考图1，热固性材料层208形成在平面润湿表面202上。该热固性材料层208可由适当的底层填料型或缓冲涂层型材料(例如但不限于环氧树脂、酚醛树脂、聚酰亚胺和聚苯并恶唑(PBO))形成。该热固性材料层208可以用各种方式——包括旋涂和薄片层合——进行涂覆。该热固性材料层208也可以在被涂覆到平面润湿表面202之前或之后被B级固化。
现在参考图2，器件晶片100在热和压力下接合到支撑衬底200。如图所示，多个焊料凸起106穿透该热固性材料层208并在回流期间散布在整个平面润湿表面202上或润湿平面润湿表面202。同时，该热固性材料层208至少部分地被固化。
根据本发明的实施例，在晶片表面上执行接合，其中接合头在后侧面104上拾起器件晶片100并将器件晶片100放置在衬底支撑物200上，衬底支撑物200又被支撑在基座上。特定的热接合轮廓(profile)可取决于焊料凸起106和热固性材料208的类型。在示例性热压缩接合(TCB)工艺中，支撑衬底200被保持在例如100℃的分级温度(staging temperature)下。可使用接合头在例如100℃的分级温度下拾起器件晶片100。接着将器件晶片100放置在支撑衬底200上，且接着将接合头温度斜升到高于焊料凸起106的液线温度的温度(例如250℃-300℃)。接合头温度然后被维持在焊料的液线温度(TAL)之上一段时间，且接合头温度接着减小到低于焊料凸起106的液线温度的温度(例如180℃)。此时，接合的结构可从基座移除以用于离线固化或在升高的温度下以在线方式保持在基座上以实现热固性材料208的实质上完全的固化。
现在参考图3，示出“后过孔”处理，其中器件晶片100被处理以形成在晶片的前表面102和后表面104之间延伸的至少一个过孔120(例如TSV)。虽然在图3中只示出一个过孔120，应认识到，这仅为了说明性目的，并且多个过孔可根据本发明的实施例形成在器件晶片中。此外，虽然示出“后过孔”处理，应理解，本发明的实施例也与“先过孔”和“中间过孔”处理兼容，其中过孔120在将器件晶片100接合到支撑衬底200之前形成。
在形成过孔120之前，可通过研磨和/或化学机械抛光(CMP)后表面104而将器件晶片100减薄回来。例如，在实施例中可将器件晶片100减薄回到大约50-100μm。在将器件晶片100减薄之后，可将钝化膜或膜叠置体130形成在后表面104之上以提供密封阻挡层。虽然没有示出，应认识到，此外还可以对器件晶片100进行处理以在过孔120的处理之前、期间或之后形成再分布线(RDL)和其它内建结构。
为了形成过孔120，可在减薄的器件晶片100的后表面104之上形成光致抗蚀剂材料，并接着对其进行曝光和显影。在显影之后，在抗蚀剂涂层中在期望有过孔120的那些位置处存在开口。在硅器件晶片的情况下，利用等离子体蚀刻，穿过钝化膜或膜叠置体130并穿过体硅118，并且停止在减薄的器件晶片100的前表面102(器件侧)上的铜接合焊盘上来形成穿硅过孔(TSV)开口。接着去除光致抗蚀剂，并从器件晶片100清除任何剩余的蚀刻聚合物或残留物。接着将绝缘层124沉积在器件表面上，给穿硅过孔(TSV)120的底部和侧壁加衬里。适当的材料包括但不限于二氧化硅、氮化硅、碳化硅和各种聚合物。这些材料可通过化学气相沉积(CVD)、原子层沉积(ALD)或旋涂方法来沉积。
各相异性蚀刻工艺可接着用于从TSV120的底表面和在钝化膜或膜叠置体130上移除绝缘层124，同时保持在TSV120的侧壁上的相当大的厚度。可接着将阻挡层126和种子层沉积在器件晶片表面上。例如，阻挡层126可包括钽、钛或钴。种子层可以是例如铜。接着将铜的均厚层电镀到器件晶片表面上，用铜122完全填充TSV。接着通过CMP将铜层和阻挡层覆盖层移除，如图3所示。
现在参考图4，当完成对减薄的器件晶片100的处理之后，接着将支撑衬底200选择性地移除。在一个实施例中，支撑衬底200是铜，并使用例如来自Transcene Co.,Inc.的铜蚀刻剂49-1的湿蚀刻剂将支撑衬底200移除，其中铜蚀刻剂49-1选择性地蚀刻掉铜，同时保持回流焊料凸起106和固化的热固性材料208实质上不受影响。在另一实施例中，支撑衬底200由具有薄层204的体衬底206(例如金属或塑料材料)形成。在体衬底206是塑料材料的情况下，溶剂可用于移除体衬底206，后面进行湿蚀刻以移除薄层204。在任一方式中，支撑衬底200的移除都暴露包括回流焊料凸起106和至少部分地固化的热固性材料208的平面前侧接合表面140。在很多实施例中，热固性材料208将在移除支撑衬底200之前已经被完全固化。
在移除支撑衬底200之后，在衬底100上形成的所得到的多个结构可被分割，并接着可以或可以不被进一步处理以形成芯片500，芯片500可接着集成到3D封装结构中。例如，结构可进一步被处理以包括在平面前侧接合表面140或后表面104之上的内建结构。示例性的3D封装结构在图5中示出，其中包括根据本发明的实施例形成的TSV的一个或多个芯片500可叠置在衬底600(例如印刷电路板或层合衬底)之上，并与焊接元件502连接。
图6示出根据本发明的实施例的计算机系统。系统690包括处理器610、存储器设备620、存储器控制器630、图形控制器640、输入和输出(I/O)控制器650、显示器652、键盘654、指点设备656和外围设备658，其中在一些实施例中所有这些设备可通过总线660通信地彼此耦合。处理器610可以是通用处理器或专用集成电路(ASIC)。I/O控制器650可包括用于有线或无线通信的通信模块。存储器设备620可以是动态随机存取存储器(DRAM)设备、静态随机存取存储器(SRAM)设备、闪速存储器设备或这些存储器设备的组合。因此，在一些实施例中，系统690中的存储器设备620不必包括DRAM设备。
例如，在系统690中示出的一个或多个部件可包括在一个或多个集成电路封装(例如图5的芯片500或3D封装结构)中和/或可包括一个或多个集成电路封装(例如图5的芯片500或3D封装结构)。例如，处理器610或存储器设备620或I/O控制器650的至少一部分或这些部件的组合可包括在集成电路封装中，集成电路封装包括在各种实施例中描述的结构的至少一个实施例。
这些元件执行它们在本领域中公知的常规功能。特别是，存储器设备620可在一些情况中用于提供对根据本发明的实施例的用于形成封装结构的方法的可执行指令的长期存储，且在其它实施例中可用于在较短期基础上在通过处理器610执行期间存储根据本发明的实施例的用于形成封装结构的方法的可执行指令。此外，例如，指令可被存储或以另外方式与通信地耦合于系统的机器可访问介质(例如光盘只读存储器(CD-ROM)、数字通用盘(DVD)和软盘)、载波和/或其它传播信号相关联。在一个实施例中，存储器设备620可给处理器610提供用于执行的可执行指令。
系统690可包括计算机(例如桌上型计算机、膝上型计算机、手持设备、服务器、网络装置、路由器等)、无线通信设备(例如蜂窝电话、无绳电话、寻呼机、个人数字助理等)、计算机相关外围设备(例如打印机、扫描仪、监视器等)、娱乐设备(例如电视机、收音机、立体声系统、磁带和光盘播放器、盒式录像机、摄像放像机、数字照相机、MP3(运动图片专家组、音频层3)播放器、视频游戏机、手表等)，等等。
虽然以专用于结构特征和/或方法操作的语言描述了本发明，应理解，在所附权利要求中限定的本发明不一定限于所描述的特定特征或行动。所公开的特定特征和操作相反应被理解为对说明本发明有用的所要求保护的发明的特别得体的实现方式。

Claims (14)

1.一种用于接合器件晶片的方法，包括：
提供包括前表面和形成在所述前表面之上的焊料凸起的所述器件晶片；
提供包括平面润湿表面的支撑衬底，其中热固性材料层形成在所述平面润湿表面上；
在热和压力之下将所述器件晶片接合到所述支撑衬底，其中所述接合包括：
利用焊料凸起穿透所述热固性材料层；
在使所述焊料凸起回流期间利用所述焊料凸起润湿所述平面润湿表面；以及
至少部分地固化热固性材料；以及
移除所述支撑衬底以暴露平面前侧接合表面，所述平面前侧接合表面包括所述回流的焊料凸起和至少部分地固化的所述热固性材料。
2.如权利要求1所述的方法，还包括在将所述器件晶片接合到所述支撑衬底之后形成过孔，所述过孔在所述器件晶片的所述前表面和后表面之间延伸。
3.如权利要求2所述的方法，包括在移除所述支撑衬底之前形成所述过孔。
4.如权利要求2所述的方法，包括在将所述器件晶片接合到所述支撑衬底之后和在形成所述过孔之前研磨或抛光所述器件晶片的后表面，以减小所述器件晶片的厚度。
5.如权利要求2所述的方法，其中所述平面润湿表面包括选自于由镍、金、铂、钯、钴、铜、铁和钢组成的组的材料。
6.如权利要求2所述的方法，其中所述支撑衬底包括体衬底和涂层，所述涂层包括所述平面润湿表面。
7.如权利要求1所述的方法，还包括在将所述器件晶片接合到所述支撑衬底之前形成过孔，所述过孔在所述器件晶片的所述前表面和后表面之间延伸。
8.如权利要求1所述的方法，其中所述平面润湿表面包括选自于由镍、金、铂、钯、钴、铜、铁和钢组成的组的材料。
9.如权利要求8所述的方法，其中所述支撑衬底是体衬底。
10.如权利要求9所述的方法，其中所述体衬底是铜。
11.如权利要求8所述的方法，其中所述支撑衬底包括体衬底和涂层，所述涂层包括所述平面润湿表面。
12.如权利要求1所述的方法，还包括在所述支撑衬底的所述平面润湿表面上旋涂或层合所述热固性材料层。
13.如权利要求12所述的方法，其中在将所述器件晶片接合到所述支撑衬底之前对所述热固性材料层进行b级固化。
14.如权利要求1所述的方法，还包括：
将第一管芯附着到所述平面前侧接合表面；以及
将第二管芯附着到所述器件晶片的后表面。
CN201180075117.0A 2011-09-30 2011-09-30 用于操纵极薄器件晶片的方法 Expired - Fee Related CN103988299B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/054428 WO2013048496A1 (en) 2011-09-30 2011-09-30 Method for handling very thin device wafers

Publications (2)

Publication Number Publication Date
CN103988299A CN103988299A (zh) 2014-08-13
CN103988299B true CN103988299B (zh) 2016-10-26

Family

ID=47996227

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180075117.0A Expired - Fee Related CN103988299B (zh) 2011-09-30 2011-09-30 用于操纵极薄器件晶片的方法

Country Status (7)

Country Link
US (2) US8994174B2 (zh)
EP (1) EP2761651B1 (zh)
JP (1) JP5970071B2 (zh)
KR (1) KR101649055B1 (zh)
CN (1) CN103988299B (zh)
TW (2) TWI550796B (zh)
WO (1) WO2013048496A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123789B2 (en) * 2013-01-23 2015-09-01 United Microelectronics Corp. Chip with through silicon via electrode and method of forming the same
DE102013221788B4 (de) * 2013-10-28 2021-05-27 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines Kontaktelements und eines optoelektronischen Bauelements
MY184096A (en) 2014-08-07 2021-03-17 Intel Corp Method and apparatus for forming backside die planar devices and saw filter
US10490483B2 (en) * 2016-03-07 2019-11-26 Micron Technology, Inc. Low capacitance through substrate via structures
US10388516B1 (en) * 2018-01-10 2019-08-20 Facebook Technologies, Llc Method for polymer-assisted chip transfer
CN109037258A (zh) * 2018-08-03 2018-12-18 德淮半导体有限公司 半导体装置及其制造方法
EP3780094A4 (en) * 2019-01-29 2022-03-30 Lg Chem, Ltd. SEMICONDUCTOR PACKAGE MANUFACTURING METHOD
KR102480379B1 (ko) 2019-01-29 2022-12-23 주식회사 엘지화학 반도체 패키지의 제조방법
KR20210135052A (ko) 2020-05-04 2021-11-12 삼성전자주식회사 반도체 패키지

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023034A (ja) * 2001-07-06 2003-01-24 Matsushita Electric Works Ltd フリップチップ実装方法
WO2006049853A2 (en) * 2004-11-01 2006-05-11 3M Innovative Properties Company Method of connecting a semiconductor package to a printed wiring board

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2701589B2 (ja) * 1991-06-26 1998-01-21 日本電気株式会社 半導体装置及びその製造方法
US6410415B1 (en) * 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
JP3450236B2 (ja) * 1999-09-22 2003-09-22 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP3296344B2 (ja) * 1999-10-28 2002-06-24 日本電気株式会社 半導体装置およびその製造方法
US6402013B2 (en) * 1999-12-03 2002-06-11 Senju Metal Industry Co., Ltd Thermosetting soldering flux and soldering process
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001257239A (ja) * 2000-03-13 2001-09-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP3552660B2 (ja) 2000-10-16 2004-08-11 松下電器産業株式会社 半導体装置の製造方法
US6794751B2 (en) * 2001-06-29 2004-09-21 Intel Corporation Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US20060142424A1 (en) * 2003-05-23 2006-06-29 Jayesh Shah Foamable underfill encapsulant
US7047633B2 (en) * 2003-05-23 2006-05-23 National Starch And Chemical Investment Holding, Corporation Method of using pre-applied underfill encapsulant
WO2005024912A2 (en) 2003-09-09 2005-03-17 Intel Corporation Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow
US6977435B2 (en) 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
JP2005089660A (ja) 2003-09-18 2005-04-07 Nitto Denko Corp 半導体封止用樹脂組成物
US20050110131A1 (en) 2003-11-24 2005-05-26 Lee Kevin J. Vertical wafer stacking using an interposer
US7088005B2 (en) 2003-12-31 2006-08-08 Intel Corporation Wafer stacking with anisotropic conductive adhesive
US7064446B2 (en) 2004-03-29 2006-06-20 Intel Corporation Under bump metallization layer to enable use of high tin content solder bumps
JP4353845B2 (ja) * 2004-03-31 2009-10-28 富士通株式会社 半導体装置の製造方法
US7442634B2 (en) 2004-12-21 2008-10-28 Intel Corporation Method for constructing contact formations
JP2006332354A (ja) * 2005-05-26 2006-12-07 Toshiba Corp プリント回路基板の製造方法、プリント回路基板
US7391112B2 (en) 2005-06-01 2008-06-24 Intel Corporation Capping copper bumps
JP5175003B2 (ja) * 2005-09-07 2013-04-03 光正 小柳 三次元積層構造を持つ集積回路装置の製造方法
JP5185622B2 (ja) * 2005-10-11 2013-04-17 富士通株式会社 多層配線基板
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
JP2007317822A (ja) * 2006-05-25 2007-12-06 Sony Corp 基板処理方法及び半導体装置の製造方法
DE102006036728B4 (de) * 2006-08-05 2017-01-19 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur elektrischen Kontaktierung mikroelektronischer Bauelemente auf einer Leiterplatte
JP2008112835A (ja) * 2006-10-30 2008-05-15 Sony Corp Ｗｌｐ（ウェハレベルパッケージ）およびその製造方法、ｗｌｐを内蔵した電子機器、ならびに気密封止方法
US20080122078A1 (en) 2006-11-08 2008-05-29 Jun He Systems and methods to passivate on-die redistribution interconnects
US8586465B2 (en) * 2007-06-07 2013-11-19 United Test And Assembly Center Ltd Through silicon via dies and packages
KR100945504B1 (ko) * 2007-06-26 2010-03-09 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
JP5656341B2 (ja) * 2007-10-29 2015-01-21 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置およびその製造方法
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US7683459B2 (en) 2008-06-02 2010-03-23 Hong Kong Applied Science and Technology Research Institute Company, Ltd. Bonding method for through-silicon-via based 3D wafer stacking
US7989318B2 (en) * 2008-12-08 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking semiconductor dies
CN102047404B (zh) * 2008-12-16 2013-07-10 松下电器产业株式会社 半导体装置和倒装芯片安装方法及倒装芯片安装装置
TWI501359B (zh) * 2009-03-13 2015-09-21 Xintec Inc 電子元件封裝體及其形成方法
KR20100109241A (ko) * 2009-03-31 2010-10-08 삼성전자주식회사 칩 적층 패키지 및 그 제조방법
TWI401753B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
JP2011151259A (ja) * 2010-01-22 2011-08-04 Sony Chemical & Information Device Corp 実装体の製造方法および実装装置
US7883991B1 (en) 2010-02-18 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Temporary carrier bonding and detaching processes
JP5412316B2 (ja) * 2010-02-23 2014-02-12 パナソニック株式会社 半導体装置、積層型半導体装置及び半導体装置の製造方法
JP4875185B2 (ja) * 2010-06-07 2012-02-15 株式会社東芝 光半導体装置
US8580683B2 (en) * 2011-09-27 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for molding die on wafer interposers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023034A (ja) * 2001-07-06 2003-01-24 Matsushita Electric Works Ltd フリップチップ実装方法
WO2006049853A2 (en) * 2004-11-01 2006-05-11 3M Innovative Properties Company Method of connecting a semiconductor package to a printed wiring board

Also Published As

Publication number Publication date
US9252111B2 (en) 2016-02-02
TW201316468A (zh) 2013-04-16
WO2013048496A1 (en) 2013-04-04
KR101649055B1 (ko) 2016-08-17
TW201537708A (zh) 2015-10-01
TWI499019B (zh) 2015-09-01
EP2761651A1 (en) 2014-08-06
EP2761651A4 (en) 2015-07-29
CN103988299A (zh) 2014-08-13
JP5970071B2 (ja) 2016-08-17
US20150162290A1 (en) 2015-06-11
TWI550796B (zh) 2016-09-21
KR20140054405A (ko) 2014-05-08
US20130264707A1 (en) 2013-10-10
JP2014528644A (ja) 2014-10-27
EP2761651B1 (en) 2019-05-29
US8994174B2 (en) 2015-03-31

Similar Documents

Publication Publication Date Title
CN103988299B (zh) 用于操纵极薄器件晶片的方法
US10515875B2 (en) Interconnect structure for package-on-package devices
US9761477B2 (en) Pre-package and methods of manufacturing semiconductor package and electronic device using the same
KR101594270B1 (ko) 듀얼 다마신 유형 접근법을 이용하여 제조된 미세 피치 백사이드 금속 재배선 라인들과 결합된 스루-실리콘 비아들을 포함하는 ３ｄ 상호연결 구조체
KR20230095110A (ko) 직접 접합 방법 및 구조체
US9449913B2 (en) 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
US7038316B2 (en) Bumpless die and heat spreader lid module bonded to bumped die carrier
KR101245928B1 (ko) 극박 적층 칩 패키징
WO2015171288A1 (en) Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US20210280519A1 (en) Package structure and semiconductor pacakge
KR20110106915A (ko) 쓰루-실리콘 비아들을 노출 및 접촉시키는 고-수율 방법
TW202109820A (zh) 晶粒堆疊結構
US8652939B2 (en) Method and apparatus for die assembly
CN108074823A (zh) 一种半导体器件及其制作方法和电子装置
US20220328456A1 (en) Semiconductor assemblies with hybrid fanouts and associated methods and systems
JP2004343088A (ja) 半導体装置及びその製造方法
CN115132672A (zh) 半导体封装件及其形成方法
EP4338198A1 (en) Method of manufacturing active reconstructed wafers

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20161026

Termination date: 20190930