CN115132672A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN115132672A
CN115132672A CN202210114082.7A CN202210114082A CN115132672A CN 115132672 A CN115132672 A CN 115132672A CN 202210114082 A CN202210114082 A CN 202210114082A CN 115132672 A CN115132672 A CN 115132672A
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China
Prior art keywords
insulating layer
integrated circuit
circuit die
encapsulant
facet
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Pending
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CN202210114082.7A
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English (en)
Inventor
曾庭箴
廖思豪
胡毓祥
郭宏瑞
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN115132672A publication Critical patent/CN115132672A/zh
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Abstract

提供了一种封装件及其形成方法。封装件包括集成电路管芯。集成电路管芯的侧壁具有第一刻面和第二刻面。第一刻面和第二刻面具有不同的倾斜度。封装件包括围绕集成电路管芯并与第一刻面和第二刻面物理接触的密封剂以及位于集成电路管芯和密封剂上方的绝缘层。集成电路管芯的上表面低于密封剂的上表面。绝缘层的侧壁与第一刻面基本共面。

Description

半导体封装件及其形成方法
技术领域
本申请的实施例涉及半导体封装件及其形成方法。
背景技术
由于许多电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断提高，半导体工业经历了快速发展。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。随着对缩小电子器件的需求的增长，已经出现了对更小且更具创造性的半导体管芯封装技术的需求。这种封装系统的示例是堆叠封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部，以提供高水平的集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上生产功能增强且占地面积小的半导体器件。
发明内容
根据实施例，一种封装件包括集成电路管芯。集成电路管芯的侧壁具有第一刻面和第二刻面。第一刻面和第二刻面具有不同的倾斜度。封装件包括围绕集成电路管芯并与第一刻面和第二刻面物理接触的密封剂以及位于集成电路管芯和密封剂上方的绝缘层。集成电路管芯的上表面低于密封剂的上表面。绝缘层的侧壁与第一刻面基本共面。
根据另一实施例，一种封装件包括集成电路管芯、与集成电路管芯的侧壁物理接触的密封剂以及位于集成电路管芯和密封剂上方的第一再分布结构。密封剂和集成电路管芯之间的第一界面包括具有第一倾斜度的第一部分和具有不同于第一倾斜度的第二倾斜度的第二部分。第一再分布结构包括绝缘层，该绝缘层具有沿密封剂的上表面延伸的第一部分和从密封剂的上表面向集成电路管芯延伸的第二部分。绝缘层的第二部分和密封剂之间的第二界面与第一界面的第一部分基本共面。
根据又一实施例，一种方法包括将集成电路管芯附接至第一绝缘层。集成电路管芯包括衬底、位于衬底上方的焊盘以及位于焊盘和衬底上方的第二绝缘层。衬底的侧壁具有第一刻面与第二刻面。第一刻面和第二刻面具有不同的倾斜度。第二绝缘层的侧壁与第一刻面基本共面。方法还包括在集成电路管芯周围形成密封剂，并且去除第二绝缘层以在密封剂中形成第一开口。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1、图2、图3、图4A和图4B示出根据一些实施例的用于形成集成电路管芯的工艺期间的中间步骤的截面图。
图5、图6、图7、图8、图9、图10、图11A、图12、图13、图14、图15、图16、图17A和图17B示出根据一些实施例的在形成封装组件的工艺期间的中间步骤的截面图。
图11B和图11C示出根据一些实施例的在形成封装组件的工艺期间的中间步骤的可能化学机制。
图18示出根据一些实施例的半导体封装件的形成的截面图。
具体实施方式
以下公开内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
各种实施例提供用于形成包括多个封装组件的半导体封装件的方法。集成电路管芯(例如，传感器管芯)可以包括具有期望强度、耐久性和柔韧性的绝缘层，同时还具有可以在后续步骤中快速且有效地去除的化学成分。集成电路管芯可以附接至包括后侧再分布结构和贯通孔的衬底，并且可以围绕集成电路管芯和贯通孔形成密封剂。然后可以去除介电层以形成电耦合至集成电路管芯和贯通孔的前侧再分布结构。然后可以将该封装组件附接至另一封装组件以形成半导体封装件。
图1、图2、图3、图4A和图4B示出根据一些实施例的用于形成集成电路管芯50的工艺期间的中间步骤的截面图。集成电路管芯50将在后续处理中被封装以形成集成电路封装件。集成电路管芯50可以是传感器管芯(例如，超声波传感器)、逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或其组合。如图所示，根据一些实施例，集成电路管芯50是传感器管芯，诸如超声波传感器(例如，超声波指纹传感器)。在其他实施例中，集成电路管芯50可以是光传感器、图像传感器或根据需要的任何合适类型的传感器。
在图1中，集成电路管芯50包括衬底52。在一些实施例中，衬底52可以是晶圆级结构，这样的晶圆可以包括不同的器件区域，这些器件区域在后续步骤中被分割以形成多个集成电路管芯50。在一些实施例中，衬底52包括半导体衬底52A，诸如掺杂或未掺杂的硅，或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底52A也可以包括：诸如锗的其他半导体材料；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP的合金半导体；或它们的组合。也可以使用诸如多层或梯度衬底的其他衬底。半导体衬底52A具有有源表面(例如，图1中面向上的表面)，有时被称为前侧；以及无源表面(例如，图1中面向下的表面)，有时被称为后侧。半导体衬底52A可以具有在约130μm和约150μm之间的厚度。衬底52可以具有在约170μm和约190μm之间的厚度。
在一些实施例中，衬底52还包括在半导体衬底52A的有源侧中和/或上形成的器件52B，以及设置在器件52B上方并与之电耦合的、包括多个金属化图案(未示出)的互连结构52C。器件52B可以是有源器件(例如，晶体管、二极管等)、无源器件(例如，电容器、电阻器等)、其组合等。器件52B可以使用适合于形成器件的任何方法形成。互连结构52C将器件52B互连以形成集成电路。互连结构52C的金属化图案包括形成在一个或多个低k介电层(未示出)中的金属线和通孔(未示出)，并且可以通过任何合适的工艺(例如沉积、镶嵌、双镶嵌等)形成。
互连结构52C电耦合至设置在衬底52的上表面上或沿其上表面设置的部件。如图所示，在集成电路管芯50是诸如超声波传感器的传感器的实施例中，集成电路管芯50可以包括位于衬底52的上表面上或沿其上表面的感测元件54和/或伪元件56(例如，伪焊盘)。每个感测元件54可以是适合于基于所需的传感器类型产生、传输和/或制造例如信号或脉冲的任何元件。例如，在传感器是超声波传感器的实施例中，每个感测元件54可以包括响应于超声波力的压电换能器，其电耦合至形成在衬底52内的集成电路。
集成电路管芯50还包括焊盘62，诸如铝焊盘，诸如实现外部连接的输入/输出(I/O)区域。焊盘62位于集成电路管芯50的衬底52的有源侧上，诸如位于互连结构52C的上侧上。焊盘62可以通过隔离区域58与感测元件54和伪元件56分离，以减少焊盘62可能对感测元件54具有的任何不期望的电效应。一个或多个钝化膜64位于集成电路管芯50上，诸如位于焊盘62、感测元件54和伪元件56的部分上。如图所示，开口延伸穿过钝化膜64至焊盘62。钝化膜64可以包括氧化硅、氮化硅、氮氧化硅等或其组合，并且可以使用原子层沉积(ALD)、化学气相沉积(CVD)等或其组合形成。
在图2中，绝缘层68可以形成在图1的结构上方。绝缘层68可以针对稳定性、拉伸强度和柔韧性进行选择，以便在随后的处理步骤中、在储存或运输过程中和/或当封装到半导体器件中时保持稳定。在一些实施例中，绝缘层68的材料被选择为具有高玻璃化转变温度Tg、高分解温度Td以及高拉伸强度和高杨氏模量。如下文更详细地描述，绝缘层68在随后的处理步骤中被去除。因此，绝缘层68也可以称为牺牲层。
绝缘层68可以是聚合物，诸如聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)等；等或其组合。绝缘层68可以例如通过旋涂、层压、ALD、CVD等形成。例如，绝缘层68可以通过将聚合物混合物施加到结构上来形成，诸如使用旋涂工艺。聚合物混合物可以包括聚合物基料和溶剂。
在一些实施例中，聚合物基料包括聚酰亚胺重复单元。聚酰亚胺重复单元还可以包括能够吸引分子中较大部分电子云的吸电子官能团FG。因此，吸电子官能团FG可以从酰亚胺基团处或附近的重复单元的一部分吸引电子。吸电子官能团FG可以与酰亚胺基团串联连接，如下面的示例性化学结构所示。
Figure BDA0003495690450000051
吸电子官能团FG的示例性化学结构可以包括强电负性原子(例如，氧原子)，诸如包括酯基的羰基，如下所示。以下化学结构的变体可以包括碳链(包括一个或多个碳)代替链的每一部分中的一个或两个氧原子。替代地，吸电子官能团FG可以包括酸酐等或与酰亚胺基团串联的其他合适的官能团。
Figure BDA0003495690450000061
溶剂可以是有机溶剂，并且可以包括任何合适的溶剂，诸如酮、醇、多元醇、醚、二醇醚、环醚、芳烃、酯、丙酸酯、乳酸酯、乳酸酯、亚烷基二醇单烷基醚、乳酸烷基酯、烷氧基丙酸烷基酯、环内酯、含环的单酮化合物、碳酸亚烷基酯、烷氧基乙酸烷基酯、丙酮酸烷基酯、乙二醇烷基醚乙酸酯、二甘醇、丙二醇烷基醚乙酸酯、亚烷基二醇烷基醚酯、亚烷基二醇单烷基酯等。
在施加聚合物混合物之后，可以进行预烘烤工艺以蒸发一些或全部溶剂。预烘烤工艺可以在约90℃和约100℃之间的温度下进行并且持续时间在约3分钟和约10分钟之间。在预烘烤工艺之后，交联聚合物基料的固化工艺可以在约225℃和约230℃之间的温度下进行，并且持续时间在约60分钟和约65分钟之间。例如，绝缘层68可以形成为在约15μm和约30μm之间的厚度。
上述聚合物基料和用于形成绝缘层68的工艺实现了若干优点。首先，由于具有介于约243℃和约255℃之间的玻璃化转变温度Tg和介于约340℃和约370℃之间的分解温度Td，绝缘层68将在后续步骤中在可能需要的升高的处理温度下保持稳定。其次，因为具有介于约120MPa和约150MPa之间的拉伸强度和介于约3.0GPa和约4.5GPa之间的杨氏模量，绝缘层68在后续处理期间额外可靠。第三，绝缘层68可以在随后的处理步骤中有效地去除，诸如通过包括碱的湿蚀刻剂，如下文更详细描述的。特别地，吸电子官能团促进与聚合物结构的其他部分的快速和高产率反应，诸如在酰亚胺基团附近具有更强正电荷的部分。
在图3中，可以执行开槽工艺，诸如激光开槽工艺，以准备每个集成电路管芯50，用于从晶圆分割。在实施例中，绝缘层68、钝化膜64和衬底52的部分(例如，衬底52的互连结构52C的介电层的部分)可以使用例如激光开槽或激光钻孔方法来图案化，由此将激光导向绝缘层68的那些需要去除以暴露下面的衬底52的部分。绝缘层68的益处包括在开槽工艺期间保持对衬底52和钝化膜64的强粘附。例如，绝缘层68的分子的聚酰亚胺(例如，环状酰亚胺)部分可以与钝化膜64形成多个氢键以提供层之间的强粘附。
在激光开槽工艺期间，钻孔能量可以在约500mJ和约1000mJ之间的范围内，并且钻孔角度可以在约0度(垂直于绝缘层68的主表面)和与绝缘层68的主表面(即，上表面)的法线成约90度之间的范围内。可以执行开槽工艺以在衬底52上方形成开口70，以指示衬底52的在随后的分割过程中被切割的划线区域。在一些实施例中，开口70延伸到衬底52中，诸如延伸到衬底52的互连结构52C中。在其他实施例中，开口70可以延伸穿过衬底52的互连结构52C并且延伸到衬底52的半导体衬底衬底52A中。
在一些实施例中，开口70的宽度随着开口70从绝缘层68的上表面向衬底52延伸而减小。开口70可以在开口70的底部处或附近具有介于约50μm和约60μm之间的宽度Wl，并且在绝缘层68的上表面处或附近具有介于约70μm和约100μm之间的宽度W2。在一些实施例中，宽度W1可以是宽度W2的约65％。在一些实施例中，被开口70暴露的绝缘层68、钝化膜64和衬底52的侧壁具有非竖直斜面，其与衬底52的主表面(即，上表面)的法线形成非零角度。非竖直斜面的角度可以与在激光开槽工艺中使用的钻孔角度基本相同。在示出的实施例中，开口70的底面是平面。在其他实施例中，开口70的底面可以为具有一个或多个凸部、一或多个凹部或其组合的曲面。
在图4A中，将集成电路管芯50从晶圆分割。在实施例中，可以通过使用锯条(未单独示出)执行分割工艺以切割绝缘层68的相邻部分之间和开口70处的衬底52的划线区域(参见图3)。然而，本领域的普通技术人员将认识到，将锯片用于分割工艺仅是一个说明性实施例，而不是限制性的。可以利用用于执行分割工艺的任何方法，诸如利用一个或多个蚀刻。可以利用这些方法和任何其他合适的方法来分割结构。在一些实施例中，集成电路管芯50具有介于约198mm与约202mm之间的宽度。
在一些实施例中，集成电路管芯50的衬底52的侧壁具有包括第一刻面72A和第二刻面72B的刻面结构。在上面参考图3描述的激光开槽工艺期间形成第一刻面72A。第一刻面72A具有非竖直斜面，其与衬底52的主表面(即，上表面)的法线形成非零角度。在上述分割工艺期间形成第二刻面72B。在其中分割工艺包括锯切工艺的一些实施例中，第二刻面72B具有在锯切工艺的工艺变化内与衬底52的主表面(即，上表面)的法线形成基本上为零的角度的基本上竖直的斜面。在一些实施例中，刻面72A形成在衬底52的互连结构52C中而不是在衬底52的半导体衬底52A中。在其他实施例中，刻面72A可以形成在衬底52的互连结构52C和半导体衬底52A两者中。
图4B示出根据一些实施例的集成电路管芯50(参见图4A)的区域74的放大截面图。在一些实施例中，衬底52的刻面72A、钝化膜64的侧壁和绝缘层68的侧壁在以上参考图3描述的激光开槽工艺的工艺变化中基本共面。在图4B中，沿着刻面72A延伸的假想平面76(由图4B中的虚线表示)与衬底52的主表面(即，上表面)形成角度θ。在一些实施例中，角度θ介于约50°和约70°之间。如下文更详细地描述，绝缘层68在随后的处理步骤中被去除。通过形成具有在上述范围内的角度θ的刻面侧壁的集成电路管芯50，减小了绝缘层68的体积。通过减小绝缘层68的体积，可以在后续的去除工艺中提高绝缘层68的去除速率。
图5、图6、图7、图8、图9、图10、图11A、图12、图13、图14、图15、图16、图17A和图17B示出根据一些实施例的在形成第一封装组件100的工艺期间的中间步骤的截面图。示出了第一封装区域100A和第二封装区域100B，并且封装一个或多个集成电路芯片50，以在每个封装区域100A和100B中形成集成电路封装件。集成电路封装件也可以被称为集成扇出(InFO)封装件。
在图5中，提供载体衬底102，并且在载体衬底102上形成释放层104。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底102可以是晶圆，从而使得多个封装件可以同时形成在载体衬底102上。
释放层104可以由聚合物基材料形成，释放层可以与载体衬底102一起稍后被从在随后步骤中将要形成的上面的结构中去除。在一些实施例中，释放层104是诸如光热转换(LTHC)释放涂层的环氧树脂基热释放材料，该材料在被加热时失去其粘性。在其他实施例中，释放层104可为紫外线(UV)胶，其在暴露于UV光时丧失它的粘合性能。释放层104可以以液体形式进行分配并且被固化，可以是层压在载体衬底102上的层压膜，或者可以是类似物。可以使释放层104的顶面齐平并且顶面可以具有高度的平面性。
在图6中，可以在释放层104上形成再分布结构106。再分布结构106也可以被称为后侧再分布结构。在所示实施例中，再分布结构106包括绝缘层108、位于绝缘层108上方的金属化图案110(有时称为再分布层或再分布线)以及位于金属化图案110和绝缘层108上方的绝缘层112。再分布结构106是可选的并且在一些实施例中可以省略。在一些实施例中，在释放层104上形成没有金属化图案的绝缘层来代替再分布结构106。
绝缘层108可以形成在释放层104上。绝缘层108的底面可以与释放层104的上表面接触。在一些实施例中，绝缘层108由聚合物形成，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他的实施例中，绝缘层108由以下材料形成：氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等；等。可以通过诸如旋涂、ALD、CVD、层压等或其组合的任何可接受的沉积工艺形成绝缘层108。
金属化图案110可以形成在绝缘层108上。作为形成金属化图案110的示例，在绝缘层108上方形成种子层(未具体示出)。在一些实施例中，种子层为金属层，其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，种子层包括钛层和钛层上方的铜层。例如，可以使用物理汽相沉积(PVD)等形成种子层。然后在种子层上形成并图案化光刻胶(未具体示出)。可以通过旋涂等形成光刻胶并且可以将光刻胶暴露于光用于图案化。光刻胶的图案对应于金属化图案110。图案化形成穿过光刻胶的开口以暴露种子层。在光刻胶的开口中和种子层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀敷来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。然后，去除光刻胶和种子层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除种子层的暴露部分。种子层的剩余部分和导电材料形成金属化图案110。
绝缘层112可以形成在金属化图案110和绝缘层108上。在一些实施例中，绝缘层112可以使用与绝缘层108类似的材料和方法形成，这里不再重复描述。在一些实施例中，绝缘层108和绝缘层112包括相同的材料。在其他实施例中，绝缘层108和绝缘层112包括不同的材料。然后图案化绝缘层112以形成暴露金属化图案110的部分的开口114。图案化可以通过可接受的工艺形成，诸如当绝缘层112是光敏材料时通过将绝缘层112暴露于光或者当绝缘层112是非光敏材料时通过使用例如各向异性蚀刻的蚀刻。若绝缘层112为光敏材料，则可以在曝光后显影绝缘层112。
图6为了说明的目的示出具有单个金属化图案110的再分布结构106。在一些实施例中，再分布结构106可以包括任意数量的绝缘层和金属化图案。如果将要形成更多的绝缘层和金属化图案，那么可以重复以上所讨论的步骤和工艺。金属化图案可以包括一个或多个导电元件。导电元件可以在金属化图案的形成过程中通过在下面的绝缘层的表面上方和下面的绝缘层的开口中形成种子层和金属化图案的导电材料来形成，从而互连和电耦合各种导线。
在图7中，贯通孔116形成在开口114(参见图6)中并远离再分布结构106的最顶部绝缘层(例如，绝缘层112)延伸。作为形成贯通孔116的示例，在再分布结构106上方，例如在绝缘层112和由开口114暴露的金属化图案110的部分上，形成种子层(未具体示出)。在一些实施例中，种子层为金属层，其可为单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，种子层包括钛层和位于钛层上方的铜层。例如，可以使用PVD等形成种子层。在种子层上形成并图案化光刻胶(未具体示出)。可通过旋涂等形成光刻胶并且可以将光刻胶暴露于光用于图案化。光刻胶的图案对应于贯通孔116的布局。图案化形成穿过光刻胶的开口以暴露种子层。在光刻胶的开口中和种子层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀敷来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。去除光刻胶和种子层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除种子层的暴露部分。种子层的剩余部分和导电材料形成贯通孔116。贯通孔116中的每一个可以具有在约245μm和约255μm之间的高度以及在约270μm和约290μm之间的宽度。
在图8中，集成电路管芯50(图4A)通过粘合剂118粘附至绝缘层112。在所示实施例中，单个集成电路管芯50粘附在封装区域100A和100B中的每一个中。在其他实施例中，多个集成电路管芯50可以在封装区域100A和100B中的每一个中彼此相邻地粘合。粘合剂118位于集成电路管芯50的后侧上并且将集成电路管芯50粘附至再分布结构106，诸如至绝缘层112。粘合剂118可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂118可以施加到集成电路管芯50的后侧，如果没有使用再分布结构106，可以施加到载体衬底102的表面上方，或者可以施加到再分布结构106(如果适用)的上表面。例如，粘合剂118可以在上面参考图4A讨论的分割以分离集成电路管芯50之前施加到集成电路管芯50的后侧。
在图9中，密封剂120形成在各个组件上和周围。在形成之后，密封剂120封装贯通孔116和集成电路管芯50。密封剂120可以是模塑料，诸如环氧树脂、树脂、可模制聚合物、其组合等，其中分散有填料。填料可以包括绝缘纤维、绝缘颗粒(例如，二氧化硅颗粒、玻璃颗粒、泥晶颗粒等)、其他合适的元素、其组合等。密封剂120可以通过压缩成型、传递成型等施加，并且可以形成在载体衬底102上方，使得贯通孔116和/或集成电路管芯50被掩埋或覆盖。密封剂120进一步形成在集成电路管芯50之间的间隙区域中并且遵循绝缘层68的侧壁的轮廓。密封剂120可以以液体或半液体形式施加，然后被固化。通过将绝缘层68选择为包括酯基并如上文参考图2所述形成的聚酰亚胺聚合物，可以获得若干优点或益处。例如，可以在不使绝缘层68变形的情况下执行用于形成密封剂120的模制工艺。因此，避免集成电路管芯50的变形和损坏。
在图10中，在密封剂120上执行平坦化工艺以暴露贯通孔116和集成电路管芯50(例如，绝缘层68)。平坦化工艺还可以去除贯通孔116和绝缘层68的材料，直到暴露所有的贯通孔116和绝缘层68。在工艺变化范围内的平坦化工艺之后，贯通孔116、绝缘层68和密封剂120的顶面基本共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果贯通孔116和/或绝缘层68已经暴露，则可以省略平坦化工艺。通过将绝缘层68选择为包括酯基并如上文参考图2所述形成的聚酰亚胺聚合物，可以获得若干优点或益处。例如，绝缘层68的益处包括具有期望的硬度和在平坦化工艺期间保持到衬底52和钝化膜64的强粘附，以避免损坏绝缘层68并且避免绝缘层68从钝化膜64分层。因此，避免损坏集成电路管芯50。
在图11A中，从每个集成电路管芯50去除绝缘层68(参见图10)以形成暴露焊盘62和钝化膜64的开口121。例如，可以通过使用湿蚀刻剂或干蚀刻剂的各向同性蚀刻或各向异性蚀刻来去除绝缘层68。如图所示，在去除绝缘层68之后，由于绝缘层68的倾斜侧壁，密封剂120可以基本保持其形状，包括悬垂集成电路管芯50。开口121可以在接近衬底52处具有在约30.5mm和约30.7mm之间的宽度W3，并且在密封剂120的上表面处或附近具有在约30.49mm和约30.5mm之间的宽度W4。在一些实施例中，宽度W4可以比宽度W3小约0.7％至约0.13％(或分别为其约99.93％和约99.87％之间)。结果，密封剂120可以以约10μm和约20μm之间的距离D1伸出开口121。
根据使用湿蚀刻工艺的实施例，湿蚀刻剂包括剥离剂，诸如SPR920等。在一些实施例中，SPR920是包括碱的溶液，诸如四甲基氢氧化铵(TMAH)、二甲亚砜(DMSO)和水，其中TMAH的重量浓度为在约1％和约2％之间，DMSO的重量浓度在约96％和约98％之间，水的重量浓度在约1％和约2％之间。湿蚀刻工艺可以在约48℃和约52℃之间的温度下进行并且持续时间在约3分钟和约10分钟之间。
图11B示出可能的通用机制，图11C示出湿蚀刻剂的主要成分(例如，SPR920中的TMAH)如何与绝缘层68相互作用并将其去除的可能的具体机制。蚀刻剂(例如，碱的带负电部分，诸如TMAH中的羟基)可以吸引绝缘层68的带正电的区域。吸电子官能团FG将绝缘层68的分子的电子从分子的其他部分吸收。例如，环状酰亚胺基团中的碳原子可能由于电子被吸引到吸电子官能团FG而具有轻微的正电荷。如此，TMAH可以分裂绝缘层68的分子以在湿蚀刻工艺中被去除。
参考图11C，其中绝缘层68的分子可以包括酯基作为吸电子官能团FG，分子的附加位点可以吸引湿蚀刻剂。例如，除了环状酰亚胺基团的碳原子外，酯基中的碳原子也可以带有轻微的正电荷，因为电子被吸引到酯基的氧原子上。因此，包括具有酯化学结构的聚酰亚胺的绝缘层68的分子可以为碱(例如，TMAH)的带负电荷部分提供附加位点以有效地分解绝缘层68。
替代地，在使用干蚀刻工艺的实施例中，干蚀刻剂可以包括氧(O2)、氮(N2)等或其任何组合。干蚀刻工艺可以在约23℃和约26℃之间的温度、约45Pa和约55Pa之间的压力下进行，并且持续时间在约24分钟和约30分钟之间。
将绝缘层68选择为包含酯基并如上文参考图2所述形成的聚酰亚胺聚合物的优点是，在上述各向同性湿蚀刻工艺中使用例如包括TMAH的SPR920实现改进的效率和产率。结果，与每小时可以处理约9个晶圆的上述干蚀刻工艺相比，湿蚀刻工艺每小时可以处理多于约9个晶圆，诸如高达每小时约167个晶圆。此外，湿蚀刻工艺可以比干蚀刻工艺便宜约三或四倍。
返回参考图11A，在一些实施例中，用于去除绝缘层68(参见图10)的工艺使密封剂120的上表面变得粗糙并形成密封剂120的粗糙上表面120t。在一些实施例中，在进行如上所述的湿蚀刻工艺之后，密封剂120的上表面的粗糙度大于在进行如上所述的干蚀刻工艺之后的密封剂120的上表面的粗糙度。在如上所述使用湿蚀刻工艺的实施例中，密封剂120的粗糙上表面120t具有介于约0.5μm和约0.7μm之间的粗糙度。在如上所述使用干蚀刻工艺的实施例中，密封剂120的粗糙上表面120t具有介于约0.1μm和约0.2μm之间的粗糙度。
在一些实施例中，用于去除绝缘层68(参见图10)的工艺进一步使贯通孔116的上表面变得粗糙并形成贯通孔116的粗糙上表面116t。在一些实施例中，由于湿蚀刻工艺中贯通孔116的导电材料(例如，铜)的腐蚀，所以在进行上述湿蚀刻工艺之后的贯通孔116的上表面的粗糙度大于在进行上述干蚀刻工艺之后的贯通孔116的上表面的粗糙度。在如上所述使用湿蚀刻工艺的实施例中，贯通孔116的粗糙上表面116t具有介于约0.02μm和约0.2μm之间的粗糙度。在如上所述使用干蚀刻工艺的实施例中，贯通孔116的粗糙上表面116t具有介于约0.01μm和约0.05μm之间的粗糙度。
在图12、图13、图14和图15中，再分布结构122(参见图15)形成在密封剂120、贯通孔116和集成电路管芯50上方。再分布结构122也可以被称为前侧再分布结构。再分布结构122包括绝缘层124和128以及金属化图案126。可以在再分布结构122中形成更多的绝缘层和金属化图案。金属化图案也可以称为再分布层或再分布线。再分布结构122被示为具有一个金属化图案的示例。如果将要形成更多的绝缘层和金属化图案，那么可以重复下面所讨论的步骤和工艺。
在图12中，绝缘层124沉积在密封剂120、贯通孔116上以及集成电路管芯50的衬底52上方的开口121(参见图11A)中。如图所示，绝缘层124可以基本上填充开口121。在一些实施例中，可以使用与以上关于图6所述的绝缘层108类似的材料和方法来形成绝缘层124，并且本文不再重复描述。在一些实施例中，执行平坦化工艺以赋予绝缘层124基本平坦的上表面。在一些实施例中，直接设置在集成电路管芯50上方和密封剂120的上表面下方的绝缘层124的部分具有与图10中所示的绝缘层68基本相同的轮廓，因为绝缘层124的这些部分填充在去除绝缘层68之后形成的开口121(图11A)。绝缘层124可以在密封剂120正上方具有在约9μm和约11μm之间的厚度。
在一些实施例中，密封剂120的粗糙上表面120t提高了密封剂120和绝缘层124之间的粘附力。与使用如上文参考图11A所述的干蚀刻工艺的实施例相比，在使用如上文参考图11A所述的湿蚀刻工艺的实施例中，密封剂120的粗糙上表面120t的增加的粗糙度增加了密封剂120与绝缘层124之间的粘附力。
在一些实施例中，贯通孔116的粗糙上表面116t提高了贯通孔116和绝缘层124之间的粘附力。与使用如上文参考图11A所述的干蚀刻工艺的实施例相比，在使用如上文参考图11A所述的湿蚀刻工艺的实施例中，贯通孔116的粗糙上表面116t的增加的粗糙度增加了贯通孔116与绝缘层124之间的粘附力。
然后，在图13中，图案化绝缘层124。图案化形成暴露贯通孔116的部分的开口130、暴露焊盘62的部分的开口132以及暴露直接位于感测元件54上方的钝化膜64的开口134。图案化可以通过可接受的工艺进行，诸如当绝缘层124为光敏材料时，通过暴露和显影绝缘层124。在其他实施例中，当绝缘层124为非感光材料时，可以在绝缘层124上方形成并图案化掩模层(未具体示出)，并且可以通过例如蚀刻来去除绝缘层124的暴露部分。开口134可以具有介于约29.3mm与约29.4mm之间的宽度W5。
然后，在图14中，形成金属化图案126。金属化图案126包括沿着绝缘层124的主表面延伸并且延伸穿过绝缘层124以物理和电耦合至集成电路管芯50的贯通孔116和焊盘62的导电元件。作为示例，为了形成金属化图案126，在绝缘层124上方和在延伸穿过绝缘层124的开口(例如，图13中所示的开口130、开口132和开口134)中形成种子层(未具体示出)。在一些实施例中，种子层为金属层，其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，种子层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成种子层。然后在种子层上形成并图案化光刻胶(未具体示出)。可通过旋涂等形成光刻胶并且可将所述光刻胶暴露于光用于图案化。光刻胶的图案对应于金属化图案126。图案化形成穿过光刻胶的开口以暴露种子层(包括位于贯通孔116上方的开口130和位于焊盘62上方的开口132内的种子层的部分)。然后，在光刻胶的开口中和种子层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀敷来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。导电材料和种子层下面的部分的组合形成金属化图案126。去除光刻胶和种子层的其上未形成的导电材料的部分(包括位于感测元件54上方的开口134内的光刻胶和种子层的部分)。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除种子层的暴露部分。金属化图案52可以具有在约4μm和约5μm之间的厚度。
在图15中，在金属化图案126和绝缘层124上沉积绝缘层128。在一些实施例中，可以使用与以上关于图6所述的绝缘层108类似的材料和方法来形成绝缘层128，并且本文不再重复描述。在一些实施例中，绝缘层124和绝缘层128包括相同的材料。在其他实施例中，绝缘层124和绝缘层128包括不同的材料。绝缘层128可以与绝缘层124类似地图案化以形成开口136。例如，图案化可以通过可接受的工艺进行，诸如当绝缘层128是光敏材料时通过将绝缘层128暴露于光并显影或者当绝缘层128是非光敏材料时通过使用例如各向异性蚀刻的蚀刻。开口136在绝缘层124中具有宽度W6并且在绝缘层128中具有宽度W7。在一些实施例中，开口136的宽度W6可以与开口134的宽度W5基本相同(参见图14)，开口136的宽度W7可以大于开口136的宽度W6。例如，宽度W6可以介于约29.25mm与约29.35mm之间，宽度W7可介于约29.35mm与约29.39mm之间。在其他实施例中，在如上文参考图13所述的绝缘层124的图案化期间可以不形成开口134。在这样的实施例中，可以通过同时图案化绝缘层124和绝缘层128来形成开口136。绝缘层128可以在密封剂120正上方具有在约8.5μm和约11μm之间的厚度。
尽管未具体说明，在其中集成电路管芯50期望穿过绝缘层128连接的实施例中，可形成凸块下金属化(UBM)以用于外部连接到再分布结构122，例如，对于作为逻辑器件或存储器件的一些集成电路管芯50。在一些实施例中并且如下所述，作为逻辑器件或存储器件的集成电路管芯50可以具有通过金属化图案126、贯通孔116和再分布结构106的外部连接。在一些实施例中，包括作为传感器管芯的集成电路管芯50的封装区域(例如，第一封装区域100A和/或第二封装区域100B)可以保持没有UBM。
在图16中，执行载体衬底去接合以从再分布结构106(例如，绝缘层108)分离(或“去接合”)载体衬底102(参见图15)。在一些实施例中，去接合包括将诸如激光或UV光的光投射到释放层104上，从而使得释放层104在光的热量下分解，并且载体衬底102可以被去除。然后将结构翻转并放置在胶带(未示出)上以形成附加结构，诸如下面描述的导电连接件152。
进一步在图16中，形成延伸穿过绝缘层108以接触金属化图案110的导电连接件152。形成穿过绝缘层108的开口以暴露金属化图案110的一部分。例如，使用激光钻孔、蚀刻等形成开口。导电连接件152形成在开口中。在一些实施例中，导电连接件152包括焊剂并且在焊剂浸渍工艺中形成。在一些实施例中，导电连接件152包括诸如焊膏、银膏等的导电膏，并且在印刷工艺中分配。导电连接件152可以是球珊阵列(BGA)连结件、焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件152可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，可以通过首先通过蒸发、电镀、印刷、焊料转印、球植等形成焊料层来形成导电连接件152。一旦在结构上形成焊料层，就可以执行回流，以将材料成形为期望的凸块形状。在另一个实施例中，导电连接件152包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以没有焊料并且具有基本上竖直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括通过电镀工艺形成的镍、锡、锡-铅、金、银、钯、铟、镍钯金、镍金等或它们组合。
在图17A中，通过沿着例如第一封装区域100A和第二封装区域100B(参见图16)之间的划线区域(未具体示出)锯切来执行分割工艺。锯切将第一封装区域100A与第二封装区域100B分割以形成单独的第一封装组件100。示出的单独的第一封装组件100是第一封装区域100A或第二封装区域100B中的一个。
在一些实施例中，在第一封装组件100内部的密封剂120的倾斜侧壁处的密封剂120的粗糙上表面120t的第一部分的第一粗糙度不同于第一封装组件100的边缘处的密封剂120的粗糙上表面120t的第二部分第二粗糙度。在一些实施例中，密封剂120的粗糙上表面120t的第一粗糙度大于密封剂120的粗糙上表面120t的第二粗糙度。密封剂120的粗糙上表面120t的第一粗糙度与密封剂120的粗糙上表面120t的第二粗糙度之间的差异也可以称为密封剂120的粗糙上表面120t的均匀度。在使用如上文参考图11A所述的湿蚀刻工艺的实施例中，密封剂120的粗糙上表面120t具有小于约0.1μm的均匀度。在使用如上文参考图11A所述的干蚀刻工艺的实施例中，密封剂120的粗糙上表面120t具有大于约0.5μm的均匀性。
图17B示出根据一些实施例的第一封装组件100(参见图17A)的区域138的放大截面图。在一些实施例中，衬底52的刻面72A、钝化膜64的侧壁和绝缘层124的侧壁基本共面。在图17B中，沿着刻面72A延伸的假想平面140(由图4B中的虚线表示)与衬底52的主表面(诸如上表面)形成角度θ。在一些实施例中，角度θ介于约50°和约70°之间。在一些实施例中，密封剂120和集成电路管芯50之间的界面包括具有第一倾斜度的第一部分(密封剂120和刻面72A之间的界面)和具有不同于第一倾斜度的第二倾斜度的第二部分(密封剂120和刻面72B之间的界面)。第一倾斜度与刻面72A的倾斜度相同。第二倾斜度与刻面72B的倾斜度相同。
图18示出根据一些实施例的器件堆叠件的形成和实施方式。器件堆叠件由形成在第一封装组件100中的集成电路封装件形成。器件堆叠件还可以被称为封装件上封装件(PoP)结构。第一封装组件100使用导电连接件152耦合至第二封装组件200。在一些未示出的实施例中，第一封装组件100中的一个以上可以使用导电连接件152耦合至第二封装组件200。
在一些实施例中，第二封装组件200可以包括插入件或封装衬底并且可以包括衬底202、上部再分布结构204和下部再分布结构206，使得衬底202插入上部再分布结构202和下部再分布结构206之间。衬底202可以包括贯通孔208以将上部再分布结构204电耦合至下部再分布结构206。衬底202可以基本上没有有源和无源器件。
衬底202可以通过任何合适的方法形成并且可以例如包括诸如硅、锗、金刚石等的半导体材料。在一些实施例中，也可以使用化合物材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷镓、磷化镓铟、它们的组合等。附加地，衬底202可以包括绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延生长的硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个替代实施例中，衬底202基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代材料包括双马来酰亚胺-三嗪(BT)树脂，或者其他印刷电路板(PCB)材料或膜。诸如味之素(Ajinomoto)堆积膜(ABF)的堆积膜或其他叠层可以用于形成衬底202。
在另一实施例中，第二封装组件200可以是工艺控制器，诸如数字处理芯片(例如，多层数字处理芯片或控制器(ML-DPC))。在这样的实施例中，第二封装组件200形成在晶圆上，然后晶圆被分割成单独的组件。工艺控制器监视第一封装组件100的感测元件54的输出并且与构成整个感测设备的其他器件协调地控制感测元件54的功能。在一些实施例中，虽然没有具体示出，但是衬底202(例如，硅衬底)可以包括有源和无源器件。可以使用诸如晶体管、电容器、电阻器、其组合等的各种各样的器件来生成第二封装组件200的设计的结构和功能要求。可以使用任何合适的方法来形成器件。
尽管没有具体示出，但是衬底202还可以包括位于有源和无源器件上方的互连结构并且被设计为连接有源和无源器件以形成功能电路。互连结构可以由介电材料(例如，低k介电材料)和导电材料(例如铜)的交替层形成，具有将导电材料层互连的通孔，并且可以通过任何合适的工艺(例如沉积、镶嵌、双镶嵌等)形成。另外，贯通孔208可以延伸穿过衬底202以将上部再分布结构204的一部分电耦合至下部再分布结构206的一部分。
第二封装组件200还可以在上部再分布结构204的上侧具有接合焊盘210以电和机械耦合至第一封装组件100的导电连接件152。在一些实施例中，接合焊盘210是通过在上部再分布结构204的上侧的介电层中形成凹槽(未示出)来形成的。可以形成凹槽以允许接合焊盘210嵌入介电层中。在其他实施例中，由于接合焊盘210可以形成在介电层上，所以省略凹槽。
在形成第二封装组件200之后，第一封装组件100通过第一封装组件100的导电连接件152和第二封装组件100的上部再分布结构204机械和电接合至第二封装组件200。
在一些实施例中，在上部再分布结构204上形成阻焊剂(未示出)。导电连接件152可以设置在阻焊剂中的开口中以电和机械耦合至第二封装组件200中的导电部件(例如，接合焊盘210)。阻焊剂可以用于保护第二封装组件200的区域(例如，上部再分布结构204)免受外部损坏。在一些实施例中，导电连接件152在其回流之前在其上形成环氧树脂助焊剂(未示出)，而在将第一封装组件100附接到第二封装组件200之后，剩余环氧树脂助焊剂的至少一些环氧树脂部分。
在一些实施例中，在第一封装组件100和第二封装组件200之间形成底部填充物(未示出)，围绕导电连接件152。底部填充物可以减少应力并保护由导电连接件152的回流引起的接头。底部填充物可以在第一封装组件100附接至第二封装组件200之后通过毛细管流动工艺形成，或者可以在第一封装组件100附接至第二封装组件200之前通过适当的沉积方法形成。在形成环氧树脂助焊剂的实施例中，它可以用作底部填充物。
在一些实施例中，诸如一个或多个表面安装器件(SMD)212(例如，电容器、电阻器、电感器等)和互连结构214(例如，连接件)的附加功能组件电和机械耦合至第二封装组件200。在一些实施例中，当第二封装组件200是工艺控制器时，第二封装组件200形成在晶圆上，然后晶圆被分割成单独的组件。一个或多个SMD 212和互连结构214可以在分割工艺之前或之后附接至下部再分布结构206以形成第二封装组件200。在一些实施例中，一个或多个SMD 212和互连结构214在第一封装组件100附接至上部再分布结构204之后附接至下部再分布结构206。在所示实施例中，一个或多个SMD 212和互连结构214附接至下部再分布结构206。在其他实施例中，一个或多个SMD 212和互连结构214中的一些或全部可以附接至上部再分布结构204。虽然没有具体示出，但是互连结构214可以附加地耦合至其他封装件或器件。
第一封装组件100可以在其他器件中实现。例如，示出PoP结构，但是第一封装组件100也可以在倒装芯片球栅阵列(FCBGA)封装件中实现。还可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘(其允许对3D封装或3DIC进行测试)、使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上执行。附加地，本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法结合使用，以增加产量并降低成本。
实施例可以获得优点。如上所述的绝缘层68的形成可以提高整个制造工艺的效率和产率。特别地，绝缘层68形成为在后续处理期间稳定。例如，绝缘层68具有高玻璃化转变温度和分解温度，这允许绝缘层68保持基本相同的成分，对衬底52和钝化膜64的牢固粘附，并避免在后续步骤中变形，例如，可以使用升高的温度(例如，密封剂120的形成)。良好的拉伸强度和高杨氏模量在密封剂120的后续平坦化(例如，研磨)期间提供附加的耐久性和对衬底52和钝化膜64的粘附。另外，绝缘层68(例如，带有酯基的聚酰亚胺)有助于使用湿蚀刻工艺快速有效地去除。
根据实施例，一种封装件包括集成电路管芯。集成电路管芯的侧壁具有第一刻面和第二刻面。第一刻面和第二刻面具有不同的倾斜度。封装件包括围绕集成电路管芯并与第一刻面和第二刻面物理接触的密封剂以及位于集成电路管芯和密封剂上方的绝缘层。集成电路管芯的上表面低于密封剂的上表面。绝缘层的侧壁与第一刻面基本共面。
实施例可以包括以下特征中的一个或多个。封装件还包括与集成电路管芯相邻地延伸穿过密封剂的贯通孔。在封装件中，绝缘层的宽度随着绝缘层从密封剂的上表面向集成电路管芯的上表面延伸而增加。封装件还包括位于绝缘层上方的再分布层，其中，再分布层的一部分延伸穿过绝缘层并且电耦合至集成电路管芯。在封装件中，密封剂的上表面的粗糙度介于约0.5μm和约0.7μm之间。在封装件中，集成电路管芯的第一刻面和上表面形成第一角度，其中，第一角度在约50°和约70°之间。在封装件中，第二刻面基本垂直于集成电路管芯的上表面。
根据另一实施例，一种封装件包括集成电路管芯、与集成电路管芯的侧壁物理接触的密封剂以及位于集成电路管芯和密封剂上方的第一再分布结构。密封剂和集成电路管芯之间的第一界面包括具有第一倾斜度的第一部分和具有不同于第一倾斜度的第二倾斜度的第二部分。第一再分布结构包括绝缘层，该绝缘层具有沿密封剂的上表面延伸的第一部分和从密封剂的上表面向集成电路管芯延伸的第二部分。绝缘层的第二部分和密封剂之间的第二界面与第一界面的第一部分基本共面。
实施例可以包括以下特征中的一个或多个。封装件还包括第二再分布结构，其中，集成电路管芯介于第一再分布结构和第二再分布结构之间。封装件还包括与集成电路管芯相邻地延伸穿过密封剂的贯通孔，其中，贯通孔将第一再分布结构电耦合至第二再分布结构。在封装件中，贯通孔的上表面的粗糙度介于约0.02μm和约0.2μm之间。在封装件中，绝缘层的第一部分与密封剂之间的第三界面的粗糙度介于约0.5μm和约0.7μm之间。在封装件中，第一界面的第一部分与集成电路管芯的上表面形成第一角度，其中，第一角度介于约50°和约70°之间。在封装件中，第一界面的第二部分基本垂直于集成电路管芯的上表面。
根据又一实施例，一种方法包括将集成电路管芯附接至第一绝缘层。集成电路管芯包括衬底、位于衬底上方的焊盘以及位于焊盘和衬底上方的第二绝缘层。衬底的侧壁具有第一刻面与第二刻面。第一刻面和第二刻面具有不同的倾斜度。第二绝缘层的侧壁与第一刻面基本共面。方法还包括在集成电路管芯周围形成密封剂，并且去除第二绝缘层以在密封剂中形成第一开口。
实施例可以包括以下特征中的一个或多个。在该方法中，第二绝缘层包括带有酯基的聚酰亚胺。在该方法中，去除第二绝缘层包括执行湿蚀刻工艺。在该方法中，使用包括四甲基氢氧化铵(TMAH)、二甲亚砜(DMSO)和水的溶液执行湿蚀刻工艺。方法还包括在集成电路管芯和密封剂上方形成再分布结构，其中，再分布结构的第三绝缘层填充第一开口。方法还包括在再分布结构中形成第二开口，其中，第二开口暴露集成电路管芯。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体封装件，包括：
集成电路管芯，所述集成电路管芯的侧壁具有第一刻面和第二刻面，所述第一刻面和所述第二刻面具有不同的倾斜度；
密封剂，围绕所述集成电路管芯并与所述第一刻面和所述第二刻面物理接触，所述集成电路管芯的上表面低于所述密封剂的上表面；以及
绝缘层，位于所述集成电路管芯和所述密封剂上方，所述绝缘层的侧壁与所述第一刻面基本共面。
2.根据权利要求1所述的半导体封装件，还包括与所述集成电路管芯相邻地延伸穿过所述密封剂的贯通孔。
3.根据权利要求1所述的半导体封装件，其中，随着所述绝缘层从所述密封剂的上表面向所述集成电路管芯的上表面延伸，所述绝缘层的宽度增加。
4.根据权利要求1所述的半导体封装件，还包括位于所述绝缘层上方的再分布层，其中，所述再分布层的一部分延伸穿过所述绝缘层并电耦合至所述集成电路管芯。
5.根据权利要求1所述的半导体封装件，其中，所述密封剂的上表面的粗糙度介于约0.5μm和约0.7μm之间。
6.根据权利要求1所述的半导体封装件，其中，所述第一刻面和所述集成电路管芯的上表面形成第一角度，并且其中，所述第一角度介于约50°和约70°之间。
7.根据权利要求1所述的半导体封装件，其中，所述第二刻面基本垂直于所述集成电路管芯的上表面。
8.一种半导体封装件，包括：
集成电路管芯；
密封剂，与所述集成电路管芯的侧壁物理接触，所述密封剂和所述集成电路管芯之间的第一界面包括具有第一倾斜度的第一部分和具有不同于所述第一倾斜度的第二倾斜度的第二部分；以及
第一再分布结构，位于所述集成电路管芯和所述密封剂上方，所述第一再分布结构包括绝缘层，所述绝缘层具有沿所述密封剂的上表面延伸的第一部分和从所述密封剂的上表面向所述集成电路管芯延伸的第二部分，所述绝缘层的第二部分和所述密封剂之间的第二界面与所述第一界面的第一部分基本共面。
9.根据权利要求8所述的半导体封装件，还包括第二再分布结构，其中，所述集成电路管芯介于所述第一再分布结构和所述第二再分布结构之间。
10.一种形成半导体封装件的方法，包括：
将集成电路管芯附接至第一绝缘层，所述集成电路管芯包括：
衬底，所述衬底的侧壁具有第一刻面和第二刻面，所述第一刻面和所述第二刻面具有不同的倾斜度；
焊盘，位于所述衬底上方；和
第二绝缘层，位于所述焊盘和所述衬底上方，所述第二绝缘层的侧壁与所述第一刻面基本共面；
在所述集成电路管芯周围形成密封剂；以及
去除所述第二绝缘层以在所述密封剂中形成第一开口。
CN202210114082.7A 2021-03-24 2022-01-30 半导体封装件及其形成方法 Pending CN115132672A (zh)

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