TWI763564B - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TWI763564B
TWI763564B TW110127140A TW110127140A TWI763564B TW I763564 B TWI763564 B TW I763564B TW 110127140 A TW110127140 A TW 110127140A TW 110127140 A TW110127140 A TW 110127140A TW I763564 B TWI763564 B TW I763564B
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Taiwan
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insulating layer
integrated circuit
circuit die
facet
package
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TW110127140A
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TW202238866A (zh
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曾庭箴
廖思豪
胡毓祥
郭宏瑞
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台灣積體電路製造股份有限公司
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Publication of TWI763564B publication Critical patent/TWI763564B/zh
Publication of TW202238866A publication Critical patent/TW202238866A/zh

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Abstract

本發明實施例提供一種封裝及其形成方法。封裝包含積體電路晶粒。積體電路晶粒的側壁具有第一小平面及第二小平面。第一小平面及第二小平面具有不同斜率。封裝包含：包封體，包圍積體電路晶粒且與第一小平面及第二小平面實體接觸；以及絕緣層，位於積體電路晶粒及包封體上方。積體電路晶粒的上部表面低於包封體的上部表面。絕緣層的側壁與第一小平面實質上共面。

Description

半導體封裝及其形成方法
本發明實施例是有關於一種半導體封裝及其形成方法。
歸因於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)的整合密度的持續改進，半導體行業已經歷快速發展。在大多數情況下，整合密度的改進源於最小特徵大小的不斷減小，此允許更多組件整合至給定區域中。隨著對縮小的電子元件的需求的增長，已出現對半導體晶粒的更小且更具創意性的封裝技術的需要。此類封裝系統的實例為疊層封裝(Package-on-Package；PoP)技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝的頂部，以提供高度的整合及組件密度。PoP技術通常使得能夠產生在印刷電路板(printed circuit board；PCB)上具有增強的功能性及小佔據面積的半導體元件。
根據本發明的一實施例，一種半導體封裝包含積體電路晶粒。積體電路晶粒的側壁具有第一小平面及第二小平面。第一 小平面及第二小平面具有不同斜率。封裝包含：包封體，包圍積體電路晶粒且與第一小平面及第二小平面實體接觸；以及絕緣層，位於積體電路晶粒及包封體上方。積體電路晶粒的上部表面低於包封體的上部表面。絕緣層的側壁與第一小平面實質上共面。
根據本發明的一實施例，一種半導體封裝包含：積體電路晶粒；包封體，與積體電路晶粒的側壁實體接觸；以及第一重佈線結構，位於積體電路晶粒及包封體上方。包封體與積體電路晶粒之間的第一界面包含具有第一斜率的第一部分及具有與第一斜率不同的第二斜率的第二部分。第一重佈線結構包含絕緣層，所述絕緣層具有沿著包封體的上部表面延伸的第一部分及自包封體的上部表面朝向積體電路晶粒延伸的第二部分。絕緣層的第二部分與包封體之間的第二界面與第一界面的第一部分實質上共面。
根據本發明的一實施例，一種半導體封裝的形成方法包含將積體電路晶粒貼合至第一絕緣層。積體電路晶粒包含基底；接墊，位於基底上方；以及第二絕緣層，位於接墊及基底上方。基底的側壁具有第一小平面及第二小平面。第一小平面及第二小平面具有不同斜率。第二絕緣層的側壁與第一小平面實質上共面。方法更包含圍繞積體電路晶粒形成包封體；以及移除第二絕緣層以在包封體中形成第一開口。
50:積體電路晶粒
52、202:基底
52A:半導體基底
52B:元件
52C:內連線結構
54:感測部件
56:虛設部件
58:隔離區
62:接墊
64:鈍化膜
68、108、112、124、128:絕緣層
70、114、121、130、132、134、136:開口
72A:第一小平面
72B:第二小平面
74、138:區
76、140:虛平面
100:第一封裝組件
100A:第一封裝區
100B:第二封裝區
102:載體基底
104:釋放層
106、122:重佈線結構
110、126:金屬化圖案
116、208:穿孔
116t、120t:粗糙化上部表面
118:黏著劑
120:包封體
152:導電連接件
200:第二封裝組件
204:上部重佈線結構
206:下部重佈線結構
210:接合墊
212:表面安裝元件
214:內連線結構
D1:距離
FG:官能基
W1、W2、W3、W4、W5、W6、W7:寬度
θ:角度
在結合隨附圖式閱讀以下詳細描述時會最佳地理解本揭 露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，可出於論述清楚起見而任意增大或減小各種特徵的尺寸。
圖1、圖2、圖3、圖4A以及圖4B示出根據一些實施例的在用於形成積體電路晶粒的製程期間的中間步驟的橫截面圖。
圖5、圖6、圖7、圖8、圖9、圖10、圖11A、圖12、圖13、圖14、圖15、圖16、圖17A以及圖17B示出根據一些實施例的在用於形成封裝組件的製程期間的中間步驟的橫截面圖。
圖11B及圖11C示出根據一些實施例的在用於形成封裝組件的製程期間的中間步驟的可能化學機制。
圖18示出根據一些實施例的形成半導體封裝的橫截面圖。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的特定實例是為了簡化本揭露。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，在第二特徵上方或第二特徵上形成第一特徵可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，在本文中可使用諸如「在......之下」、 「在......下方」、「下部」、「在......上方」、「上部」以及類似術語的空間相對術語來描述如諸圖中所示出的一個部件或特徵與另一部件或特徵的關係。除了諸圖中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或以其他定向旋轉)，且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
各種實施例提供用於形成包括多個封裝組件的半導體封裝的方法。積體電路晶粒(例如，感測器晶粒)可包含絕緣層，所述絕緣層具有期望強度、耐久性以及可撓性，同時亦具有在後續步驟中可快速且高效地移除的化學組成物。積體電路晶粒可貼合至包括背側重佈線結構及穿孔的基底，且包封體可圍繞積體電路晶粒及穿孔形成。接著可移除介電層以便形成電耦接至積體電路晶粒及穿孔的前側重佈線結構。接著可將此封裝組件附接至另一封裝組件以形成半導體封裝。
圖1、圖2、圖3、圖4A以及圖4B示出根據一些實施例的在用於形成積體電路晶粒50的製程期間的中間步驟的橫截面圖。積體電路晶粒50將在後續處理中經封裝以形成積體電路封裝。積體電路晶粒50可為感測器晶粒(例如，超音波感測器)、邏輯晶粒(例如，中央處理單元(central processing unit；CPU)、圖形處理單元(graphics processing unit；GPU)、系統晶片(system-on-chip；SoC)、應用處理器(application processor；AP)、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取存儲器(static random access memory；SRAM)晶粒等)、電力管理晶粒(例如，電力管理積體電路(power management integrated circuit；PMIC)晶粒)、射頻(radio frequency；RF)晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(digital signal processing；DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end；AFE)晶粒)、類似晶粒或其組合。如所示出，根據一些實施例，積體電路晶粒50為感測器晶粒，諸如超音波感測器(例如，超音波指紋感測器)。在其他實施例中，積體電路晶粒50可視需要為光感測器、影像感測器或任何適合類型的感測器。
在圖1中，積體電路晶粒50包含基底52。在一些實施例中，基底52可為諸如晶圓的晶圓級結構，所述晶圓級結構可包含在後續步驟中經單體化以形成多個積體電路晶粒50的不同元件區。在一些實施例中，基底52包括摻雜或未摻雜的諸如矽的半導體基底52A或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底52A亦可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層或梯度基底。半導體基底52A具有有時稱為前側的主動表面(例如，圖1中的朝向上方的表面)及有時稱為背側的非主動表面(例如，圖1中的朝向下方的表面)。半導體基底52A可具有在約130微米與約150微米之間的厚度。基底52可具 有在約170微米與約190微米之間的厚度。
在一些實施例中，基底52更包含形成於半導體基底52A的主動側中及/或主動側上的元件52B及安置於元件52B上方且電耦接至元件52B的包含多個金屬化圖案(未繪示)的內連線結構52C。元件52B可為主動元件(例如，電晶體、二極體等)、被動元件(例如，電容器、電阻器等)、其組合或類似元件。元件52B可使用適合於形成元件的任何方法來形成。內連線結構52C使元件52B內連以形成積體電路。內連線結構52C的金屬化圖案包含形成於一或多個低k介電層(未繪示)中的金屬線及通孔(未繪示)，且可經由任何適合的製程(諸如沉積、鑲嵌、雙鑲嵌或類似製程)形成。
內連線結構52C電耦接至安置於基底52的上部表面上或沿著基底52的上部表面安置的特徵。如所示出，在積體電路晶粒50為諸如超音波感測器的感測器的實施例中，積體電路晶粒50可包含位於基底52的上部表面上的或沿著基底52的上部表面的感測部件54及/或虛設部件56(例如，虛設接墊)。每一感測元件54可為適合於基於期望的感測器的類型來產生、傳輸及/或製造例如訊號或脈衝的任何感測部件。舉例而言，在感測器為超音波感測器的實施例中，每一感測部件54可包含回應於超音波力的壓電換能器，所述壓電換能器電耦接至形成於基底52內的積體電路。
積體電路晶粒50更包含接墊62，諸如鋁接墊，諸如進行外部連接的輸入/輸出(input/output；I/O)區。接墊62位於積體電路晶粒50的基底52的主動側上，諸如位於內連線結構52C的 上部側上。接墊62可藉由隔離區58與感測部件54及虛設部件56分離，以便減小接墊62可對感測部件54產生的任何非所要的電效應。一或多個鈍化膜64位於積體電路晶粒50上，諸如位於接墊62、感測部件54以及虛設部件56的部分上。如所示出，開口穿過鈍化膜64延伸至接墊62。鈍化膜64可包括氧化矽、氮化矽、氮氧化矽、類似者或其組合，且可使用原子層沉積(atomic layer deposition；ALD)、化學氣相沉積(chemical vapor deposition；CVD)、類似者或其組合形成。
在圖2中，絕緣層68可形成於圖1的結構上方。可出於穩定性、抗拉強度以及可撓性而選擇絕緣層68，以便在後續處理步驟中、在儲存或運輸期間及/或在封裝至半導體元件中時保持穩定。在一些實施例中，將絕緣層68的材料選擇為具有高玻璃轉移溫度Tg、高分解溫度Td以及高抗拉強度及高楊氏模量(Young's Modulus)。如下文更詳細地描述，在後續處理步驟中移除絕緣層68。因此，絕緣層68亦可稱為犧牲層。
絕緣層68可為聚合物，諸如聚醯亞胺、聚苯并噁唑(polybenzoxazole；PBO)、苯并環丁烷(benzocyclobutane；BCB)或類似聚合物；氮化物，諸如氮化矽或類似氮化物；氧化物，諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass；BPSG)或類似氧化物；類似者或其組合。可例如藉由旋轉塗佈、層壓、ALD、CVD或類似者來形成絕緣層68。舉例而言，可藉由諸如使用旋轉塗佈製程將聚合物混合 物塗覆至結構來形成絕緣層68。聚合物混合物可包含聚合物基材及溶劑。
在一些實施例中，聚合物基材包含聚醯亞胺重複單元。聚醯亞胺重複單元可更包含能夠吸引分子中的電子雲的較大部分的吸電子官能基FG。因此，吸電子官能基FG可將電子自醯亞胺基處或醯亞胺基附近的重複單元的一部分吸走。吸電子官能基FG可與如下文在例示性化學結構中所示出的醯亞胺基串聯附接。
Figure 110127140-A0305-02-0010-1
吸電子官能基FG的例示性化學結構可包含強負電性原子(例如，氧原子)，諸如包含酯基的羰基，如下文所示出。以下化學結構的變化可包含代替鏈的各部分中的氧原子中的一者或兩者的碳鏈(包含一或多個碳)。替代地，吸電子官能基FG可包含酸酐、類似者或與醯亞胺基串聯的其他適合官能基。
Figure 110127140-A0305-02-0010-2
溶劑可為有機溶劑，且可包括任何適合的溶劑，諸如酮、醇、多元醇、醚、二醇醚、環醚、芳族烴、酯、丙酸鹽、乳酸鹽、乳酸酯、伸烷基二醇單烷基醚、乳酸烷基酯、烷氧基丙酸烷酯、 環內酯、含有環的單酮化合物、碳酸伸烷酯、烷氧基乙酸烷酯、丙酮酸烷酯、乙二醇烷基醚乙酸酯、二伸乙甘醇、丙二醇烷基醚乙酸酯、伸烷基二醇烷基醚酯、伸烷基二醇單烷基酯或類似者。
在塗覆聚合物混合物之後，可執行預烘烤製程以使溶劑中的一些或全部蒸發。預烘烤製程可在約90℃與約100℃之間的溫度下且在約3分鐘與約10分鐘之間的持續時間內執行。在預烘烤製程之後，使聚合物基材交聯的固化製程可在約225℃與約230℃之間的溫度下且在約60分鐘與約65分鐘之間的持續時間內執行。絕緣層68可例如形成為約15微米與約30微米之間的厚度。
上述聚合物基材及用於形成絕緣層68的製程實現若干優點。首先，歸因於具有在約243℃與約255℃之間的玻璃轉移溫度Tg及在約340℃與約370℃之間的分解溫度Td，絕緣層68將在後續步驟中可能需要的升高的處理溫度下保持穩定。第二，歸因於具有在約120兆帕與約150兆帕之間的抗拉強度及在約3.0季帕與約4.5季帕之間的楊氏模量，絕緣層68在後續處理期間為特別可靠的。第三，絕緣層68可在後續處理步驟中諸如藉由包括鹼的濕蝕刻劑高效地移除，如下文更詳細地描述。特定而言，吸電子官能基促進與聚合物結構的其他部分(諸如在醯亞胺基附近具有較強正電荷的部分)的快速及高良率反應。
在圖3中，可執行諸如雷射開槽製程的開槽製程以製備用於自晶圓單體化的每一積體電路晶粒50。在實施例中，可使用例如雷射開槽或雷射鑽孔方法來使絕緣層68、鈍化膜64以及基底52的部分(諸如(例如)基底52的內連線結構52C的介電層的 部分)圖案化，藉此，將雷射導向至絕緣層68的期望被移除的彼等部分以便暴露下伏基底52。絕緣層68的益處包含在開槽製程期間維持對基底52及鈍化膜64的較強黏著性。舉例而言，絕緣層68的分子的聚醯亞胺(例如，環狀醯亞胺)部分可與鈍化膜64形成多個氫鍵以在層之間提供較強黏著性。
在雷射開槽製程期間，鑽孔能量可在約500毫焦與約1000毫焦之間的範圍內，且鑽孔角度可在與絕緣層68的主表面(亦即，上部表面)的法線成約0度(垂直於絕緣層68的主表面)與約90度之間的範圍內。可執行開槽製程以在基底52上方形成開口70來指示基底52的要在後續單體化期間切分的切割區。在一些實施例中，開口70延伸至基底52中，諸如延伸至基底52的內連線結構52C中。在其他實施例中，開口70可延伸穿過基底52的內連線結構52C且延伸至基底52的半導體基底52A中。
在一些實施例中，開口70具有隨著開口70自絕緣層68的上部表面朝向基底52延伸而減小的寬度。開口70可具有位於開口70的底部處或附近的在約50微米與約60微米之間的寬度W1及位於絕緣層68的上部表面處或附近的在約70微米與約100微米之間的寬度W2。在一些實施例中，寬度W1可為寬度W2的約65%。在一些實施例中，由開口70暴露的絕緣層68、鈍化膜64以及基底52的側壁具有非豎直斜率，所述非豎直斜率與基底52的主表面(亦即，上部表面)的法線形成非零角度。非豎直斜率的角度可與用於雷射開槽製程的鑽孔角度實質上相同。在所示出的實施例中，開口70的底部表面為平坦表面。在其他實施例中， 開口70的底部表面可為具有一或多個凸起部分、一或多個凹入部分或其組合的彎曲表面。
在圖4A中，自晶圓單體化積體電路晶粒50。在實施例中，可藉由使用鋸片(未單獨示出)在絕緣層68的相鄰部分之間及開口70處割穿基底52的切割區來執行單體化製程(參看圖3)。然而，所屬領域中具通常知識者應認識到，利用鋸片進行單體化製程僅為一個說明性實施例且並不意欲為限制性的。可利用用於執行單體化製程(諸如利用一或多種蝕刻)的任何方法。可利用此等方法及任何其他適合的方法來將結構單體化。在一些實施例中，積體電路晶粒50具有在約198毫米與約202毫米之間的寬度。
在一些實施例中，積體電路晶粒50的基底52的側壁具有包括第一小平面(facet)72A及第二小平面72B的多面體結構。在上文參考圖3所描述的雷射開槽製程期間形成第一小平面72A。第一小平面72A具有非豎直斜率，所述非豎直斜率與基底52的主表面(亦即，上部表面)的法線形成非零角度。在上文所描述的單體化製程期間形成第二小平面72B。在單體化製程包括鋸切製程的一些實施例中，第二小平面72B具有在鋸切製程的製程變化內與基底52的主表面(亦即，上部表面)的法線形成實質上為零的角度的實質上豎直的斜率。在一些實施例中，小平面72A形成於基底52的內連線結構52C中且不形成於基底52的半導體基底52A中。在其他實施例中，小平面72A可形成於基底52的內連線結構52C及半導體基底52A兩者中。
圖4B示出根據一些實施例的積體電路晶粒50(參看圖 4A)的區74的放大橫截面圖。在一些實施例中，基底52的小平面72A、鈍化膜64的側壁以及絕緣層68的側壁在上文參考圖3所描述的雷射開槽製程的製程變化內實質上共面。在一些實施例中，沿著小平面72A延伸的虛平面76(在圖4B中用虛線表示)與基底52的主表面(亦即，上部表面)形成角度θ。在一些實施例中，角度θ在約50°與約70°之間。如下文更詳細地描述，在後續處理步驟中移除絕緣層68。藉由形成具有多面體側壁(所述多面體側壁具有在如上文所描述的範圍內的角度θ)的積體電路晶粒50，絕緣層68的體積減小。藉由減小絕緣層68的體積，絕緣層68的移除速率在後續移除製程中增加。
圖5、圖6、圖7、圖8、圖9、圖10、圖11A、圖12、圖13、圖14、圖15、圖16、圖17A以及圖17B示出根據一些實施例的在用於形成第一封裝組件100的製程期間的中間步驟的橫截面圖。示出第一封裝區100A及第二封裝區100B，且封裝積體電路晶粒50中的一或多者以在封裝區100A及封裝區100B中的每一者中形成積體電路封裝。積體電路封裝亦可稱為積體扇出型(integrated fan-out；InFO)封裝。
在圖5中，設置載體基底102，且釋放層104形成於載體基底102上。載體基底102可為玻璃載體基底、陶瓷載體基底或類似基底。載體基底102可為晶圓，以使得多個封裝可同時形成於載體基底102上。
釋放層104可由聚合物類材料形成，所述釋放層104稍後可連同載體基底102一起自將在後續步驟中形成的上覆結構移 除。在一些實施例中，釋放層104為在加熱時損失其黏著特性的環氧類熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層104可為在暴露於UV光時損失其黏著特性的紫外線(ultra-violet；UV)膠。釋放層104可以液體形式分配且可固化，可為層壓至載體基底102上的層壓膜或可為類似者。釋放層104的頂部表面可為齊平的，且可具有高度的平面性。
在圖6中，重佈線結構106可形成於釋放層104上。重佈線結構106亦可稱為背側重佈線結構。在所繪示的實施例中，重佈線結構106包含絕緣層108、位於絕緣層108上方的金屬化圖案110(有時稱為重佈線層或重佈線)以及位於金屬化圖案110及絕緣層108上方的絕緣層112。重佈線結構106為視情況選用的且在一些實施例中可省略。在一些實施例中，不具有金屬化圖案的絕緣層代替重佈線結構106形成於釋放層104上。
絕緣層108可形成於釋放層104上。絕緣層108的底部表面可與釋放層104的上部表面接觸。在一些實施例中，絕緣層108由諸如聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或類似者的聚合物形成。在其他實施例中，絕緣層108由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻磷矽酸鹽玻璃(BPSG)或類似氧化物；或類似者。絕緣層108可藉由諸如旋轉塗佈、ALD、CVD、層壓、類似製程或其組合的任何可接受的沉積製程形成。
金屬化圖案110可形成於絕緣層108上。作為形成金屬 化圖案110的實例，晶種層(未特定示出)形成於絕緣層108上方。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於鈦層上方的銅層。可使用例如物理氣相沉積(physical vapor deposition；PVD)或類似者形成晶種層。接著在晶種層上形成光阻(未特定示出)且對光阻進行圖案化。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以進行圖案化。光阻的圖案與金屬化圖案110對應。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由諸如電鍍或化學鍍的鍍覆或類似者形成。導電材料可包括金屬，比如銅、鈦、鎢、鋁或類似者。接著，移除其上未形成導電材料的光阻以及晶種層的部分。可藉由可接受的灰化或剝離製程(諸如使用氧電漿或類似者)來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成金屬化圖案110。
絕緣層112可形成於金屬化圖案110及絕緣層108上。在一些實施例中，絕緣層112可使用與絕緣層108類似的材料及方法形成，且本文中不再重複描述。在一些實施例中，絕緣層108及絕緣層112包括相同材料。在其他實施例中，絕緣層108及絕緣層112包括不同材料。接著使絕緣層112圖案化以形成暴露金屬化圖案110的部分的開口114。圖案化可藉由可接受的製程(諸如在絕緣層112為感光性材料時藉由將絕緣層112暴露於光或在 絕緣層112為非感光性材料時藉由使用例如非等向性蝕刻進行蝕刻)來形成。若絕緣層112為感光性材料，則絕緣層112可在暴露之後顯影。
圖6出於說明性目的示出具有單個金屬化圖案110的重佈線結構106。在一些實施例中，重佈線結構106可包含任何數目的絕緣層及金屬化圖案。若將形成更多的絕緣層及金屬化圖案，則可重複上文所論述的步驟及製程。金屬化圖案可包含一或多個導電部件。導電部件可在金屬化圖案的形成期間藉由在下伏絕緣層的表面上方及下伏絕緣層的開口中形成金屬化圖案的晶種層及導電材料來形成，從而使各種導電線內連及電耦接。
在圖7中，穿孔116形成於開口114(參看圖6)中且遠離重佈線結構106的最頂部絕緣層(例如，絕緣層112)延伸。作為形成穿孔116的實例，晶種層(未特定示出)形成於重佈線結構106上方，例如形成於絕緣層112及金屬化圖案110的由開口114暴露的部分上。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及位於鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。在晶種層上形成且圖案化光阻(未特定示出)。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以進行圖案化。光阻的圖案與穿孔116的佈局對應。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由諸如電鍍或化學鍍的鍍覆或類似者形成。導電材料可包括金屬，比如銅、鈦、鎢、鋁或類似者。移 除其上未形成導電材料的光阻以及晶種層的部分。可藉由可接受的灰化或剝離製程(諸如使用氧電漿或類似者)來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成穿孔116。穿孔116中的每一者可具有在約245微米與約255微米之間的高度及在約270微米與約290微米之間的寬度。
在圖8中，積體電路晶粒50(圖4A)藉由黏著劑118黏著至絕緣層112。在所示出的實施例中，單個積體電路晶粒50黏著於封裝區100A及封裝區100B中的每一者中。在其他實施例中，多個積體電路晶粒50可在封裝區100A及封裝區100B中的每一者中彼此相鄰地黏著。黏著劑118位於積體電路晶粒50的背側上且將積體電路晶粒50黏著至重佈線結構106，諸如黏著至絕緣層112。黏著劑118可為任何適合的黏著劑、環氧樹脂、晶粒貼合膜(die attach film；DAF)或類似者。黏著劑118可塗覆至積體電路晶粒50的背側，可在不利用重佈線結構106的情況下塗覆於載體基底102的表面上方或可在適用時塗覆至重佈線結構106的上部表面。舉例而言，黏著劑118可在上文參考圖4A所論述的用以分離積體電路晶粒50的單體化之前塗覆至積體電路晶粒50的背側。
在圖9中，包封體120形成於各種組件上且圍繞各種組件形成。在形成之後，包封體120包封穿孔116及積體電路晶粒50。包封體120可為其中分散有填充劑的模製化合物，諸如環氧樹脂、樹脂、可模製聚合物、其組合或類似者。填充劑可包含絕 緣纖維、絕緣粒子(例如，矽石粒子、玻璃粒子、微晶石灰岩粒子或類似粒子)、其他適合的部件、其組合或類似者。包封體120可藉由壓縮模製、轉移模製或類似模製來塗覆，且可形成於載體基底102上方以使得穿孔116及/或積體電路晶粒50被掩埋或覆蓋。包封體120進一步形成於積體電路晶粒50之間的間隙區中，且沿著絕緣層68的側壁的輪廓。包封體120可以液體或半液體形式塗覆且接著隨後固化。可藉由選擇包括酯基的聚醯亞胺聚合物作為絕緣層68且以如上文參考圖2所描述的來形成絕緣層68以實現若干優勢或益處。舉例而言，可在不使絕緣層68變形的情況下執行用於形成包封體120的模製製程。因此，避免積體電路晶粒50的變形及損壞。
在圖10中，對包封體120執行平坦化製程以暴露穿孔116及積體電路晶粒50(例如，絕緣層68)。平坦化製程亦可移除穿孔116及絕緣層68的材料，直至暴露全部的穿孔116及絕緣層68為止。穿孔116、絕緣層68以及包封體120的頂部表面在製程變化內的平坦化製程之後實質上共面。平坦化製程可為例如化學機械研磨(chemical-mechanical polish；CMP)、研磨製程或類似製程。在一些實施例中，例如，若已暴露穿孔116及/或絕緣層68，則可省略平坦化製程。可藉由選擇包括酯基的聚醯亞胺聚合物作為絕緣層68且以如上文參考圖2所描述的來形成絕緣層68以實現若干優勢或益處。舉例而言，絕緣層68的益處包含具有期望硬度且在平坦化製程期間維持對基底52及鈍化膜64的較強黏著性以避免絕緣層68的損壞及避免絕緣層68與鈍化膜64的分層。因 此，避免積體電路晶粒50的損壞。
在圖11A中，自積體電路晶粒50中的每一者移除絕緣層68(參看圖10)以形成暴露接墊62及鈍化膜64的開口121。可例如經由等向性蝕刻或非等向性蝕刻使用濕蝕刻劑或乾蝕刻劑來移除絕緣層68。如所示出，在移除絕緣層68之後，包封體120可實質上保持其形狀，所述形狀包含由於絕緣層68的傾斜側壁而懸於積體電路晶粒50之上。開口121在接近於基底52處可具有在約30.5毫米與約30.7毫米之間的寬度W3及在位於包封體120的上部表面處或附近具有在約30.49毫米與約30.5毫米之間的寬度W4。在一些實施例中，寬度W4可在小於寬度W3的約0.7%與約0.13%(或分別為寬度W3的約99.93%與約99.87%)之間。因此，包封體120可以在約10微米與約20微米之間的距離D1懸於開口121之上。
根據使用濕式蝕刻製程的實施例，濕蝕刻劑包括諸如SPR920或類似者的剝離劑。在一些實施例中，SPR920為包括鹼的溶液，諸如四甲基氫氧化銨(tetramethylammonium hydroxide；TMAH)、二甲基亞碸(dimethyl sulfoxide；DMSO)以及水，其中TMAH具有在約1%與約2%之間的重量濃度，DMSO具有在約96%與約98%之間的重量濃度，且水具有在約1%與約2%之間的重量濃度。濕式蝕刻製程可在約48℃與約52℃之間的溫度下且在約3分鐘與約10分鐘之間的持續時間內執行。
圖11B示出可能的通用機制，且圖11C示出關於濕蝕刻劑的主要組分(例如，SPR920中的TMAH)可如何與絕緣層68 相互作用且移除絕緣層68的可能特定機制。濕蝕刻劑的主要組分(例如，鹼的帶負電荷部分，諸如TMAH中的羥基)可吸引絕緣層68的帶正電荷區。吸電子官能基FG將絕緣層68的分子的電子自分子的其他部分吸走。舉例而言，歸因於電子被吸引至吸電子官能基FG，環狀醯亞胺基中的碳原子可具有微量的正電荷。因此，TMAH可使將在濕式蝕刻製程中移除的絕緣層68的分子分裂。
參考圖11C，其中絕緣層68的分子可包括作為吸電子官能基FG的酯基，分子的額外位點可吸引濕蝕刻劑。舉例而言，除了環狀醯亞胺基的碳原子之外，酯基中的碳原子亦可由於電子被吸引至酯基的氧原子而具有微量的正電荷。因此，包括具有酯化學結構的聚醯亞胺的絕緣層68的分子可為鹼(例如，TMAH)的帶負電荷部分提供額外位點以高效地分解絕緣層68。
替代地，在使用乾式蝕刻製程的實施例中，乾蝕刻劑可包括氧氣(O2)、氮氣(N2)、類似者或其任何組合。可在約23℃與約26℃之間的溫度下，在約45帕與約55帕之間的壓力下以及在約24分鐘與約30分鐘之間的持續時間內執行乾式蝕刻製程。
選擇包括酯基的聚醯亞胺聚合物作為絕緣層68且以如上文參考圖2所描述的來形成絕緣層68的優勢為在使用例如包括TMAH的SPR920的上文所描述的等向性濕式蝕刻製程中實現提高的效率及良率。因此，與每小時可處理約9個晶圓的上文所描述的乾式蝕刻製程相比，濕式蝕刻製程每小時可處理多於約9個晶圓，諸如每小時處理多達約167個晶圓。另外，濕式蝕刻製程可比乾式蝕刻製程便宜約三倍或四倍。
返回參考圖11A，在一些實施例中，用於移除絕緣層68(參看圖10)的製程使包封體120的上部表面粗糙化且形成包封體120的粗糙化上部表面120t。在一些實施例中，包封體120的上部表面在執行如上文所描述的濕式蝕刻製程之後的粗糙度大於包封體120的上部表面在執行如上文所描述的乾式蝕刻製程之後的粗糙度。在使用如上文所描述的濕式蝕刻製程的實施例中，包封體120的粗糙化上部表面120t具有在約0.5微米與約0.7微米之間的粗糙度。在使用如上文所描述的乾式蝕刻製程的實施例中，包封體120的粗糙化上部表面120t具有在約0.1微米與約0.2微米之間的粗糙度。
在一些實施例中，用於移除絕緣層68(參看圖10)的製程進一步使穿孔116的上部表面粗糙化且形成穿孔116的粗糙化上部表面116t。在一些實施例中，穿孔116的上部表面在執行如上文所描述的濕式蝕刻製程之後的粗糙度大於穿孔116的上部表面在執行如上文所描述的乾式蝕刻製程之後的粗糙度，此是歸因於穿孔116的導電材料(例如，銅)在濕式蝕刻製程中的腐蝕。在使用如上文所描述的濕式蝕刻製程的實施例中，穿孔116的粗糙化上部表面116t具有在約0.02微米與約0.2微米之間的粗糙度。在使用如上文所描述的乾式蝕刻製程的實施例中，穿孔116的粗糙化上部表面116t具有在約0.01微米與約0.05微米之間的粗糙度。
在圖12、圖13、圖14以及圖15中，重佈線結構122(參看圖15)形成於包封體120、穿孔116以及積體電路晶粒50上方。 重佈線結構122亦可稱為前側重佈線結構。重佈線結構122包含絕緣層124、絕緣層128以及金屬化圖案126。更多的絕緣層及金屬化圖案可形成於重佈線結構122中。金屬化圖案亦可稱為重佈線層或重佈線。將重佈線結構122繪示為具有一個金屬化圖案的實例。若將形成更多的絕緣層及金屬化圖案，則可重複下文所論述的步驟及製程。
在圖12中，絕緣層124沉積於包封體120與穿孔116上，且沉積至位於積體電路晶粒50的基底52上方的開口121(參看圖11A)中。如所示出，絕緣層124可實質上填充開口121。在一些實施例中，絕緣層124可使用與上文參考圖6所描述的絕緣層108類似的材料及方法形成，且在本文中不再重複描述。在一些實施例中，執行平坦化製程以使絕緣層124具有實質上平坦的上部表面。在一些實施例中，絕緣層124的安置於積體電路晶粒50正上方且安置於包封體120的上部表面正下方的部分具有與圖10中所示出的絕緣層68實質上相同的輪廓，此是由於絕緣層124的此等部分填充在移除絕緣層68之後形成的開口121(圖11A)。絕緣層124可在包封體120的正上方具有在約9微米與約11微米之間的厚度。
在一些實施例中，包封體120的粗糙化上部表面120t提高包封體120與絕緣層124之間的黏著性。在使用如上文參考圖11A所描述的濕式蝕刻製程的實施例中，與使用如上文參考圖11A所描述的乾式蝕刻製程的實施例相比，包封體120的粗糙化上部表面120t的增加的粗糙度增加了包封體120與絕緣層124之間的 黏著性。
在一些實施例中，穿孔116的粗糙化上部表面116t改良穿孔116與絕緣層124之間的黏著性。在使用如上文參考圖11A所描述的濕式蝕刻製程的實施例中，與使用如上文參考圖11A所描述的乾式蝕刻製程的實施例相比，穿孔116的粗糙化上部表面116t的增加的粗糙度增加了穿孔116與絕緣層124之間的黏著性。
在圖13中，接著圖案化絕緣層124。圖案化形成暴露穿孔116的部分的開口130、暴露接墊62的部分的開口132以及暴露位於感測部件54的正上方的鈍化膜64的開口134。圖案化可藉由可接受的製程進行，諸如在絕緣層124為感光性材料時藉由暴露絕緣層124且使絕緣層124顯影。在其他實施例中，當絕緣層124為非感光性材料時，可在絕緣層124上方形成且圖案化罩幕層(未特定示出)，且可藉由例如蝕刻來移除絕緣層124的暴露部分。開口134可具有在約29.3毫米與約29.4毫米之間的寬度W5。
在圖14中，接著形成金屬化圖案126。金屬化圖案126包含沿著絕緣層124的主表面延伸且延伸穿過絕緣層124以實體耦接且電耦接至穿孔116及積體電路晶粒50的接墊62的導電部件。作為實例，為形成金屬化圖案126，晶種層(未特定示出)形成於絕緣層124上方及延伸穿過絕緣層124的開口(例如，圖13中所示出的開口130、開口132以及開口134)中。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。接著在晶種 層上形成且圖案化光阻(未特定示出)。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以進行圖案化。光阻的圖案與金屬化圖案126對應。圖案化形成穿過光阻的開口以暴露晶種層(包含位於穿孔116上方的開口130及接墊62上方的開口132內的晶種層的部分)。導電材料接著形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由諸如電鍍或化學鍍的鍍覆或類似者形成。導電材料可包括金屬，比如銅、鈦、鎢、鋁或類似者。導電材料與晶種層的下伏部分的組合形成金屬化圖案126。移除其上未形成導電材料的光阻以及晶種層的部分(包含位於感測部件54上方的開口134內的光阻及晶種層的部分)。可藉由可接受的灰化或剝離製程(諸如使用氧電漿或類似者)來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。金屬化圖案可具有在約4微米與約5微米之間的厚度。
在圖15中，絕緣層128沉積於金屬化圖案126及絕緣層124上。在一些實施例中，絕緣層128可使用與上文參考圖6所描述的絕緣層108類似的材料及方法形成，且在本文中不再重複描述。在一些實施例中，絕緣層124及絕緣層128包括相同材料。在其他實施例中，絕緣層124及絕緣層128包括不同材料。絕緣層128可以與絕緣層124類似的方式圖案化以形成開口136。舉例而言，圖案化可藉由可接受的製程進行，諸如在絕緣層128為感光性材料時藉由將絕緣層128暴露於光且使絕緣層128顯影或在絕緣層128為非感光性材料時藉由使用例如非等向性蝕刻進行蝕 刻。開口136在絕緣層124中具有寬度W6且在絕緣層128中具有寬度W7。在一些實施例中，開口136的寬度W6可與開口134(參看圖14)的寬度W5實質上相同，且開口136的寬度W7可大於開口136的寬度W6。舉例而言，寬度W6可在約29.25毫米與約29.35毫米之間，且寬度W7可在約29.35毫米與約29.39毫米之間。在其他實施例中，開口134可不在如上文參考圖13所描述的絕緣層124的圖案化期間形成。在這類實施例中，開口136可藉由同時使絕緣層124及絕緣層128圖案化來形成。絕緣層128可在包封體120正上方具有在約8.5微米與約11微米之間的厚度。
儘管未特定示出，但在期望積體電路晶粒50經由絕緣層128連接的實施例中，例如，對於作為邏輯元件或記憶體元件的一些積體電路晶粒50，可形成凸塊下金屬化物(under-bump metallization；UBM)以用於與重佈線結構122進行外部連接。在一些實施例中且如下文所論述，作為邏輯元件或記憶體元件的積體電路晶粒50可具有經由金屬化圖案126、穿孔116以及重佈線結構106進行的外部連接。在一些實施例中，包含作為感測器晶粒的積體電路晶粒50的封裝區(例如，第一封裝區100A及/或第二封裝區100B)可保持不含UBM。
在圖16中，執行載體基底剝離以將載體基底102(參看圖15)與重佈線結構106(例如，絕緣層108)脫離(或「剝離」)。在一些實施例中，剝離包含將諸如雷射光或UV光的光射於釋放層104上，使得釋放層104在光的熱量下分解且載體基底102可移除。接著翻轉結構且將結構放置在帶(未繪示)上以形成額外 結構，諸如下文所描述的導電連接件152。
另外，在圖16中，形成延伸穿過絕緣層108以接觸金屬化圖案110的導電連接件152。形成穿過絕緣層108的開口以暴露金屬化圖案110的部分。舉例而言，可使用雷射鑽孔、蝕刻或類似者來形成開口。導電連接件152形成於開口中。在一些實施例中，導電連接件152包括焊劑且形成於焊劑浸漬製程中。在一些實施例中，導電連接件152包括諸如錫膏、銀膠或類似者的導電膏，且分配於印刷製程中。導電連接件152可為球格陣列封裝(ball grid array；BGA)連接件、焊球、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection；C4)凸塊、微凸塊、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold；ENEPIG)形成的凸塊或類似者。導電連接件152可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件152藉由經由蒸發、電鍍、印刷、焊料轉移、植球或類似者初始地形成焊料層而形成。一旦焊料層已形成於結構上，則可執行回焊以便將材料塑形成期望凸塊形狀。在另一實施例中，導電連接件152包括藉由濺鍍、印刷、電鍍、化學鍍、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可無焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層形成於金屬柱的頂部。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可藉由鍍覆製程形成。
在圖17A中，藉由沿著例如在第一封裝區100A與第二 封裝區100B(參看圖16)之間的切割區(未特定示出)鋸切來執行單體化製程。鋸切將第一封裝區100A自第二封裝區100B單體化以形成個別第一封裝組件100。所示出的個別第一封裝組件100為第一封裝區100A或第二封裝區100B中的任一者。
在一些實施例中，在第一封裝組件100的內部中的包封體120的傾斜側壁處的包封體120的粗糙化上部表面120t的第一部分的第一粗糙度與在第一封裝組件100的邊緣處的包封體120的粗糙化上部表面120t的第二部分的第二粗糙度不同。在一些實施例中，包封體120的粗糙化上部表面120t的第一粗糙度大於包封體120的粗糙化上部表面120t的第二粗糙度。包封體120的粗糙化上部表面120t的第一粗糙度與包封體120的粗糙化上部表面120t的第二粗糙度之間的差異亦可稱為包封體120的粗糙化上部表面120t的均一性。在使用如上文參考圖11A所描述的濕式蝕刻製程的實施例中，包封體120的粗糙化上部表面120t具有小於約0.1微米的均一性。在使用如上文參考圖11A所描述的乾式蝕刻製程的實施例中，包封體120的粗糙化上部表面120t具有大於約0.5微米的均一性。
圖17B示出根據一些實施例的第一封裝組件100(參看圖17A)的區138的放大橫截面圖。在一些實施例中，基底52的小平面72A、鈍化膜64的側壁以及絕緣層124的側壁實質上共面。在一些實施例中，沿著小平面72A延伸的虛平面140(在圖17B中由虛線表示)與基底52的主表面(諸如上部表面)形成角度θ。在一些實施例中，角度θ在約50°與約70°之間。在一些實施例中， 包封體120與積體電路晶粒50之間的界面包括具有第一斜率的第一部分(諸如包封體120與小平面72A之間的界面)及具有與第一斜率不同的第二斜率的第二部分(諸如包封體120與小平面72B之間的界面)。第一斜率與小平面72A的斜率相同。第二斜率與小平面72B的斜率相同。
圖18示出根據一些實施例的元件堆疊的形成及實施。元件堆疊由形成於第一封裝組件100中的積體電路封裝形成。元件堆疊亦可稱為層疊封裝(PoP)結構。第一封裝組件100使用導電連接件152耦接至第二封裝組件200。在未示出的一些實施例中，第一封裝組件100中的多於一者可使用導電連接件152耦接至第二封裝組件200。
在一些實施例中，第二封裝組件200可包括插入件(interposer)或封裝基底，且可包含基底202、上部重佈線結構204以及下部重佈線結構206，使得基底202插入於上部重佈線結構204與下部重佈線結構206之間。基底202可包含穿孔208以將上部重佈線結構204電耦接至下部重佈線結構206。基底202可實質上不含主動元件及被動元件。
基底202可藉由任何適合的方法形成，且可包含例如半導體材料，諸如矽、鍺、金剛石或類似者。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷鎵、磷化鎵銦、此等的組合以及類似者。另外，基底202可包括絕緣層上矽(silicon-on-insulator；SOI)基底。通常，SOI基底包含半導體材料(諸如磊晶矽、鍺、矽鍺、 SOI、絕緣層上矽鍺(silicon germanium on insulator；SGOI)或其組合)的層。在一個替代實施例中，基底202是基於諸如玻璃纖維強化樹脂芯的絕緣芯。一種芯材料的實例為諸如FR4的玻璃纖維樹脂。芯材料的替代方案包含雙馬來醯亞胺三嗪(bismaleimide-triazine；BT)樹脂或替代地包含其他印刷電路板(PCB)材料或膜。諸如味之素增層膜(Ajinomoto build-up film；ABF)的增層膜或其他層壓板可用於形成基底202。
在另一實施例中，第二封裝組件200可為製程控制器，諸如數位處理晶片(例如，多層數位處理晶片或控制器(multilayer digital processing chip or controller；ML-DPC))。在此類實施例中，第二封裝組件200形成於晶圓上，且接著將晶圓單體化為個別組件。製程控制器監測第一封裝組件100的感測部件54的輸出且與構成整個感測設備的其他元件協調地控制感測部件54的功能。在一些實施例中，儘管未特定示出，但基底202(例如，矽基底)可包含主動元件及被動元件。可使用諸如電晶體、電容器、電阻器、此等的組合以及類似者的廣泛多種元件來產生用於第二封裝組件200的設計的結構性及功能性要求。可使用任何適合的方法來形成元件。
儘管未特定示出，但基底202亦可包含位於主動元件及被動元件上方的內連線結構，且設計成連接主動元件及被動元件以形成功能電路系統。內連線結構可由介電材料(例如，低k介電材料)與導電材料(例如，銅)的交替層形成(其中通孔使導電材料層內連)，且可經由任何適合的製程(諸如沉積、鑲嵌、雙 鑲嵌或類似者)來形成。另外，穿孔208可延伸穿過基底202以將上部重佈線結構204的部分電耦接至下部重佈線結構206的部分。
第二封裝組件200可另外具有位於上部重佈線結構204的上部側上的接合墊210以電耦接且機械耦接至第一封裝組件100的導電連接件152。在一些實施例中，接合墊210藉由於位於上部重佈線結構204的上部側上的介電層中形成凹部(未繪示)而形成。可將凹部形成為允許接合墊210嵌入於介電層中。在其他實施例中，省略了凹部，此是由於接合墊210可形成於介電層上。
在形成第二封裝組件200之後，第一封裝組件100藉助於第一封裝組件100的導電連接件152及第二封裝組件200的上部重佈線結構204機械接合且電接合至第二封裝組件200。
在一些實施例中，阻焊劑(未繪示)形成於上部重佈線結構204上。導電連接件152可安置於阻焊劑中的開口中以電耦接且機械耦接至第二封裝組件200中的導電特徵(例如，接合墊210)。阻焊劑可用於保護第二封裝組件200的區域(例如，上部重佈線結構204)免受外部損壞。在一些實施例中，在導電連接件152與在第一封裝組件100附接至第二封裝組件200之後剩餘的環氧樹脂助焊劑的環氧樹脂部分中的至少一些回焊之前，所述導電連接件152上形成有環氧樹脂助焊劑(未繪示)。
在一些實施例中，底部填充劑(未繪示)形成於第一封裝組件100與第二封裝組件200之間，從而包圍導電連接件152。 底部填充劑可減小應力，且保護由導電連接件152的回焊產生的接合處。底部填充劑可在第一封裝組件100附接至第二封裝組件200之後藉由毛細流動製程形成，或可在第一封裝組件100附接至第二封裝組件200之前藉由適合的沉積方法形成。在形成環氧樹脂助焊劑的實施例中，環氧樹脂助焊劑可充當底部填充劑。
在一些實施例中，諸如一或多個表面安裝元件(surface mount device；SMD)212(例如，電容器、電阻器、電感器或類似者)及內連線結構214(例如，連接件)的額外功能組件電耦接且機械耦接至第二封裝組件200。在一些實施例中，當第二封裝組件200為製程控制器時，第二封裝組件200形成於晶圓上，且接著將晶圓單體化為個別組件。一或多個SMD 212及內連線結構214可在單體化製程之前或在單體化製程之後附接至下部重佈線結構206以形成第二封裝組件200。在一些實施例中，一或多個SMD 212及內連線結構214在第一封裝組件100附接至上部重佈線結構204之後附接至下部重佈線結構206。在所示出的實施例中，一或多個SMD 212及內連線結構214附接至下部重佈線結構206。在其他實施例中，一或多個SMD 212及內連線結構214中的一些或全部可附接至上部重佈線結構204。儘管未特定示出，但內連線結構214可另外耦接至其他封裝或元件。
第一封裝組件100可實施於其他元件中。舉例而言，繪示PoP結構，但第一封裝組件100亦可實施於倒裝晶片球格陣列(Flip Chip Ball Grid Array；FCBGA)封裝中。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或3DIC元 件的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試接墊，其允許測試3D封裝或3DIC、使用探針及/或探針卡以及類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併入對良裸晶粒的中間驗證的測試方法使用，以提高良率且降低成本。
實施例可實現優勢。如上文所描述的絕緣層68的形成可提高整體製造製程的效率及良率。特定而言，絕緣層68被形成為在後續處理期間為穩定的。舉例而言，絕緣層68具有高玻璃轉移溫度及分解溫度，所述高玻璃轉移溫度及分解溫度允許絕緣層68維持實質上相同的組成物、對基底52及鈍化膜64的穩固黏著性，且避免在例如可使用升高的溫度的後續步驟(例如，包封體120的形成)期間的變形。在包封體120的後續平坦化(例如，研磨)期間，絕緣層68的良好抗拉強度及高楊氏模量向基底52及鈍化膜64提供額外耐久性及黏著性。另外，絕緣層68的特定組成物(例如，具有酯基的聚醯亞胺)有助於使用濕式蝕刻製程的快速且高效的移除。
根據實施例，一種封裝包含積體電路晶粒。積體電路晶粒的側壁具有第一小平面及第二小平面。第一小平面及第二小平面具有不同斜率。封裝包含：包封體，包圍積體電路晶粒且與第一小平面及第二小平面實體接觸；以及絕緣層，位於積體電路晶粒及包封體上方。積體電路晶粒的上部表面低於包封體的上部表面。絕緣層的側壁與第一小平面實質上共面。
實施例可包含以下特徵中的一或多者。封裝更包含延伸 穿過與積體電路晶粒相鄰的包封體的穿孔。在封裝中，絕緣層的寬度隨著絕緣層自包封體的上部表面朝向積體電路晶粒的上部表面延伸而增加。封裝更包含位於絕緣層上方的重佈線層，其中重佈線層的一部分延伸穿過絕緣層且電耦接至積體電路晶粒。在封裝中，包封體的上部表面的粗糙度在約0.5微米與約0.7微米之間。在封裝中，積體電路晶粒的第一小平面與上部表面形成第一角度，且其中第一角度在約50°與約70°之間。在封裝中，第二小平面實質上垂直於積體電路晶粒的上部表面。
根據另一實施例，一種封裝包含：積體電路晶粒；包封體，與積體電路晶粒的側壁實體接觸；以及第一重佈線結構，位於積體電路晶粒及包封體上方。包封體與積體電路晶粒之間的第一界面包含具有第一斜率的第一部分及具有與第一斜率不同的第二斜率的第二部分。第一重佈線結構包含絕緣層，所述絕緣層具有沿著包封體的上部表面延伸的第一部分及自包封體的上部表面朝向積體電路晶粒延伸的第二部分。絕緣層的第二部分與包封體之間的第二界面與第一界面的第一部分實質上共面。
實施例可包含以下特徵中的一或多者。封裝更包含第二重佈線結構，其中積體電路晶粒插入於第一重佈線結構與第二重佈線結構之間。封裝更包含延伸穿過與積體電路晶粒相鄰的包封體的穿孔，其中穿孔將第一重佈線結構電耦接至第二重佈線結構。在封裝中，穿孔的上部表面的粗糙度在約0.02微米與約0.2微米之間。在封裝中，絕緣層的第一部分與包封體之間的第三界面的粗糙度在約0.5微米與約0.7微米之間。在封裝中，第一界面 的第一部分與積體電路晶粒的上部表面形成第一角度，且其中第一角度在約50°與約70°之間。在封裝中，第一界面的第二部分實質上垂直於積體電路晶粒的上部表面。
根據又一實施例，一種方法包含將積體電路晶粒貼合至第一絕緣層。積體電路晶粒包含基底；接墊，位於基底上方；以及第二絕緣層，位於接墊及基底上方。基底的側壁具有第一小平面及第二小平面。第一小平面及第二小平面具有不同斜率。第二絕緣層的側壁與第一小平面實質上共面。方法更包含圍繞積體電路晶粒形成包封體；以及移除第二絕緣層以在包封體中形成第一開口。
實施例可包含以下特徵中的一或多者。在方法中，第二絕緣層包含具有酯基的聚醯亞胺。在方法中，移除第二絕緣層包含執行濕式蝕刻製程。在方法中，使用包含四甲基氫氧化銨(TMAH)、二甲基亞碸(DMSO)以及水的溶液執行濕式蝕刻製程。方法更包含在積體電路晶粒及包封體上方形成重佈線結構，其中重佈線結構的第三絕緣層填充第一開口。方法更包含在重佈線結構中形成第二開口，其中第二開口暴露積體電路晶粒。
前文概述若干實施例的特徵，以使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可容易地使用本揭露作為設計或修改用於執行本文中所引入的實施例的相同目的及/或實現相同優勢的其他製程及結構的基礎。所屬領域中具有通常知識者亦應認識到，此類等效構造不脫離本揭露的精神及範疇，且所屬領域中具有通常知識者可在不 脫離本揭露的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
50:積體電路晶粒
54:感測部件
100:第一封裝組件
108:絕緣層
110:金屬化圖案
120:包封體
122:重佈線結構
136:開口
152:導電連接件
200:第二封裝組件
204:上部重佈線結構
206:下部重佈線結構
208:穿孔
210:接合墊
212:表面安裝元件
214:內連線結構

Claims (8)

  1. 一種半導體封裝，包括：積體電路晶粒，所述積體電路晶粒的側壁具有第一小平面(facet)及第二小平面，所述第一小平面及所述第二小平面具有不同斜率；包封體，包圍所述積體電路晶粒且與所述第一小平面及所述第二小平面實體接觸，所述積體電路晶粒的上部表面低於所述包封體的上部表面；以及絕緣層，位於所述積體電路晶粒及所述包封體上方，所述絕緣層的側壁與所述第一小平面實質上共面，其中所述絕緣層的寬度隨著所述絕緣層自所述包封體的所述上部表面朝向所述積體電路晶粒的所述上部表面延伸而增加。
  2. 如請求項1所述的半導體封裝，更包括延伸穿過與所述積體電路晶粒相鄰的所述包封體的穿孔。
  3. 如請求項1所述的半導體封裝，更包括位於所述絕緣層上方的重佈線層，其中所述重佈線層的一部分延伸穿過所述絕緣層且電耦接至所述積體電路晶粒。
  4. 如請求項1所述的半導體封裝，其中所述包封體的所述上部表面的粗糙度在約0.5微米與約0.7微米之間。
  5. 如請求項1所述的半導體封裝，其中所述積體電路晶粒的所述第一小平面與所述積體電路晶粒的所述上部表面形成第一角度，且其中所述第一角度在約50°與約70°之間。
  6. 一種半導體封裝，包括：積體電路晶粒； 包封體，與所述積體電路晶粒的側壁實體接觸，所述包封體與所述積體電路晶粒之間的第一界面包括具有第一斜率的第一部分及具有與所述第一斜率不同的第二斜率的第二部分；以及第一重佈線結構，位於所述積體電路晶粒及所述包封體上方，所述第一重佈線結構包括絕緣層，所述絕緣層具有沿著所述包封體的上部表面延伸的第一部分及自所述包封體的所述上部表面朝向所述積體電路晶粒延伸的第二部分，所述絕緣層的所述第二部分與所述包封體之間的第二界面與所述第一界面的所述第一部分實質上共面，其中所述絕緣層的所述第一部分與所述包封體之間的第三界面的粗糙度在約0.5微米與約0.7微米之間。
  7. 如請求項6所述的半導體封裝，更包括第二重佈線結構，其中所述積體電路晶粒插入於所述第一重佈線結構與所述第二重佈線結構之間。
  8. 一種半導體封裝的形成方法，包括：將積體電路晶粒貼合至第一絕緣層，所述積體電路晶粒包括：基底，所述基底的側壁具有第一小平面及第二小平面，所述第一小平面及所述第二小平面具有不同斜率；接墊，位於所述基底上方；以及第二絕緣層，位於所述接墊及所述基底上方，所述第二絕緣層的側壁與所述第一小平面實質上共面，其中所述第二絕緣層包括具有酯基的聚醯亞胺；圍繞所述積體電路晶粒形成包封體；以及移除所述第二絕緣層以在所述包封體中形成第一開口。
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TW202044507A (zh) * 2019-01-31 2020-12-01 台灣積體電路製造股份有限公司 整合扇出型裝置、三維積體電路系統及其製作方法

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