CN109786360B - 半导体封装件和方法 - Google Patents

半导体封装件和方法 Download PDF

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Publication number
CN109786360B
CN109786360B CN201810789252.5A CN201810789252A CN109786360B CN 109786360 B CN109786360 B CN 109786360B CN 201810789252 A CN201810789252 A CN 201810789252A CN 109786360 B CN109786360 B CN 109786360B
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conductive
dielectric layer
conductive via
layer
integrated circuit
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CN109786360A (zh
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曾士豪
郭宏瑞
何明哲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，器件包括：集成电路管芯；与集成电路管芯相邻的通孔；密封集成电路管芯和通孔的模塑料；以及再分布结构，包括：穿过第一介电层延伸的第一导电通孔，第一导电通孔电连接至集成电路管芯，第一介电层位于集成电路管芯、通孔和模塑料上方；以及位于第一介电层和第一导电通孔上方的第一导线，第一导电通孔延伸至第一导线内。本发明的实施例还涉及半导体封装件和方法。

Description

半导体封装件和方法
技术领域
本发明的实施例涉及半导体封装件和方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这允许更多的组件集成到给定的区域。随着对电子器件缩小的需求不断增长，对半导体管芯的更小且更具创造性的封装技术的需求也已经出现。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部以提供高集成度和组件密度。PoP技术一般能够在印刷电路板(PCB)上产生具有增强的功能和较小的覆盖区的半导体器件。
发明内容
本发明的实施例提供了一种半导体封装件，包括：集成电路管芯；通孔，与所述集成电路管芯相邻；模塑料，密封所述集成电路管芯和所述通孔；以及再分布结构，包括：第一导电通孔，穿过第一介电层延伸，所述第一导电通孔电连接至所述集成电路管芯，所述第一介电层位于所述集成电路管芯、所述通孔和所述模塑料上方；以及第一导线，位于所述第一介电层和所述第一导电通孔上方，所述第一导电通孔延伸至所述第一导线内。
本发明的另一实施例提供了一种形成半导体封装件的方法，包括：用模塑料密封集成电路管芯，所述集成电路管芯具有管芯连接件；在所述集成电路管芯的所述管芯连接件上形成第一导电通孔；在所述集成电路管芯、所述模塑料和所述第一导电通孔上方沉积第一介电层，所述第一介电层沿着所述第一导电通孔的侧壁和顶面延伸，所述第一导电通孔的顶面位于所述第一介电层的主表面之上；去除所述第一介电层的位于所述第一导电通孔的侧壁和顶面上的部分，从而暴露所述第一导电通孔的部分；以及在所述第一介电层和所述第一导电通孔的暴露部分上形成第一导线。
本发明的又一实施例提供了一种形成半导体封装件的方法，包括：将集成电路管芯放置在第一介电层上，所述集成电路管芯具有管芯连接件；用模塑料密封所述集成电路管芯；在所述集成电路管芯的所述管芯连接件上形成第一导电通孔，所述第一导电通孔具有设置为离所述第一介电层层第一距离的最顶表面；在所述集成电路管芯、所述模塑料和所述第一导电通孔上沉积第二介电层，所述第二介电层具有设置为离所述第一介电层第二距离的主表面，所述第一距离大于所述第二距离；去除所述第一介电层的部分以暴露所述第一导电通孔的侧面和最顶表面；以及在所述第一导电通孔上形成第一导线，所述第一导线接触所述第一导电通孔的侧面和最顶表面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图16示出了根据一些实施例的用于形成器件封装件的工艺期间的中间步骤的截面图。
图17至图18示出了根据一些实施例的用于形成封装结构的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本文讨论的实施例可以在特定上下文中讨论，即具有细间距前侧再分布结构的封装结构(例如，叠层封装(PoP)结构)。前侧再分布结构的通孔形成为具有与上面的金属化图案的锚固连接。在锚固连接中，通孔部分地延伸至上面的金属化图案内，并且上面的金属化图案在通孔上方不具有凹槽。形成具有锚固连接的通孔可以避免盲孔的形成，例如不具有穿过相应的介电层完全暴露的通孔。此外，锚固连接可以具有更好的机械强度。
本发明的教导适用于包括再分布结构的任何封装结构。其它实施例考虑其它应用，诸如对阅读本发明之后的本领域普通技术人员将显而易见的不同封装件类型或不同配置。应该注意，本文讨论的实施例没有必要示出可能存在于结构中的每一个元件或部件。例如，诸如当一个组件的讨论可能足以表达实施例的各个方面时，可以从图中省略多个组件。此外，本文讨论的方法实施例可以以特定顺序实施；然而，其它方法实施例可以以任何逻辑顺序来实施。
图1至图15示出了根据一些实施例的用于形成器件封装件200的工艺期间的中间步骤的截面图。示出了第一封装区域600和第二封装区域602，并且在每个封装区域中均形成第一封装件200。第一封装件200也可以称为集成扇出(InFO)封装件。
在图1中，提供载体衬底100，并且在载体衬底100上形成释放层102。载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成，其可以与载体衬底100一起从在随后的步骤中形成的上面的结构去除。在一些实施例中，释放层102是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料，该材料在加热时失去其粘合性。在其它实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时失去其粘合性。释放层102可以以液体形式分配并且被固化，可以是层压在载体衬底100上的层压膜等。释放层102的顶面可以是齐平的并且可以具有高度的共面性。
在图2中，形成介电层104和金属化图案106(有时称为再分布层或再分布线)。介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中，介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层104由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成介电层104。
金属化图案106形成在介电层104上。作为形成金属化图案106的实例，在介电层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中，在金属化图案106和介电层104上形成介电层108。在一些实施例中，介电层108由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层108由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层108。之后，图案化介电层108以形成暴露金属化图案106的部分的开口。可以通过可接受的工艺图案化，诸如当介电层是光敏材料时通过将介电层108暴露于光或通过例如使用各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以称为背侧再分布结构110。在所示的实施例中，背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其它实施例中，背侧再分布结构110可以包括任何数量的介电层、金属化图案和导电通孔。通过重复用于形成金属化图案106和介电层108的工艺，可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料的金属化图案的形成期间形成导电通孔(未示出)。因此，导电通孔可以互连并且电连接各个金属化图案。
在图4中，形成通孔112。作为形成通孔112的实例，在背侧再分布结构110上方(例如，在如图所示的介电层108和金属化图案106的暴露部分上方)形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔112。
在图5中，通过粘合剂116将集成电路管芯114粘合至介电层108。虽然两个集成电路管芯114示出为粘合在第一封装区域600和第二封装区域602的每个中，但是应该理解，可以在每个封装区域中粘合更多或更少的集成电路管芯114。例如，可以在每个区域中仅粘合一个集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。而且，在一些实施例中，集成电路管芯114可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其它实施例中，集成电路管芯114可以具有相同的尺寸(例如，相同的高度和/或表面积)。
在粘合至介电层108之前，可以根据可应用的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如，集成电路管芯114每个均包括半导体衬底118，半导体衬底118诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上，并且可以通过互连结构120互连以形成集成电路，互连结构120由例如半导体衬底118上的一个或多个介电层中的金属化图案形成。
集成电路管芯114还包括制成外部连接的焊盘122，诸如铝焊盘。焊盘122位于可以称为集成电路管芯114的相应的有源侧的位置上。钝化膜124位于集成电路管芯114上并且位于焊盘122的部分上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械地和电连接至相应的焊盘122。可以通过例如镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的相应的集成电路。
介电材料128位于集成电路管芯114的有源侧上，诸如位于钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126，并且介电材料128与相应的集成电路管芯114横向共末端。介电材料128可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等或它们的组合，并且可以例如通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至背侧再分布结构110，诸如介电层108。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。粘合剂116可以施加至集成电路管芯114的背侧(诸如相应的半导体晶圆的背侧)或可以施加在载体衬底100的表面上方。集成电路管芯114可以诸如通过锯切或切割被分割并且使用例如拾取和放置工具通过粘合剂116粘合至介电层108。
在图6中，在各个组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、转移模塑等施加。密封剂130可以形成在载体衬底100上方，从而掩埋或覆盖通孔112和/或集成电路管芯114的管芯连接件126。之后，固化密封剂130。
在图7中，对密封剂130实施平坦化工艺以暴露通孔112和管芯连接件126。平坦化工艺也可以研磨介电材料128。在平坦化工艺之后，通孔112、管芯连接件126、介电材料128和密封剂130的顶面共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果已经暴露通孔112和管芯连接件126，则可以省略平坦化。
在图8至图13中，形成前侧再分布结构132。如将示出的，前侧再分布结构132包括介电层136、148、164、170，并且也包括金属化图案。金属化图案也可以称为再分布层或再分布线并且包括导电通孔134、146、162、168和导线144、160、166。因为前侧再分布结构132是细间距再分布结构，所以导线144、160、166可以具有约1μm或更小的相邻线之间的节距，并且导线144、160、166可以具有约1μm或更小的平均宽度。
在图8中，导电通孔134形成为电连接至例如通孔112和/或管芯连接件126。之后，在导电通孔134上和周围以及密封剂130、通孔112和管芯连接件126上沉积介电层136。图9A至图9D是示出用于形成导电通孔134和介电层136的工艺期间的区域650的更多细节的截面图。
在图9A中，在密封剂130、通孔112、管芯连接件126和介电材料128上形成晶种层138。在一些实施例中，晶种层138是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层138包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层138。在晶种层138上形成并且图案化掩模层140。掩模层140可以是光刻胶，诸如单层光刻胶、三层光刻胶等。掩模层140可以通过旋涂等形成，并且可以暴露于光以用于图案化。掩模层140的图案对应于通孔。图案化形成穿过掩模层140的开口142以暴露晶种层138。
在图9B中，在掩模层140的开口142中和晶种层138的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除掩模层140和晶种层138的其上未形成导电材料的部分。在掩模层140是光刻胶的实施例中，可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除掩模层140。一旦去除掩模层140，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层138的暴露部分。晶种层138的剩余部分和导电材料形成导电通孔134。
在图9C中，之后，在密封剂130、通孔112、管芯连接件126和导电通孔134上沉积介电层136。在一些实施例中，介电层136由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层136由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层136。具体地，介电层136共形地沉积在导电通孔134上方，从而使得导电通孔134的最顶表面在介电层136的主表面之上延伸距离D1。距离D1可以在从约0.1μm至约0.5μm。换句话说，介电层136是“下沉积”的，从而使得介电层136的位于相邻导电通孔134之间的部分凹进在导电通孔134的顶面下面。
在图9D中，实施去除工艺以去除介电层136的部分，从而暴露导电通孔134。去除工艺减薄导电通孔134和介电层136。在去除工艺之后，导电通孔134的顶面在介电层136的主表面之上延伸距离D2，其中，距离D2小于距离D1。距离D2可以在从约0.1μm至约0.3μm。在下沉积介电层136之后实施去除工艺可以避免盲孔的形成(例如，减小去除工艺之后导电通孔134保持被覆盖的可能性)。
在一些实施例中，去除工艺是CMP，其中，CMP的参数选择为引起介电层136的凹陷。可以通过选择CMP的参数(诸如垫、浆料或向下压力)来引入凹陷。可以使用软垫(诸如聚氨酯(PU)抛光垫)，使得抛光更共形。可以使用对介电层136的材料具有高选择性的浆料(诸如二氧化硅浆料)，从而允许介电层136以比导电通孔134更高的速率去除。例如，可以使用包括较温和的化学试剂或研磨剂的浆料。可以使用较小的向下压力，从而允许CMP对介电层136的材料更具选择性，介电层136可以是快速去除的有机材料。例如，可以使用从约2PSI至约5PSI的向下压力。通过相对于导电通孔134增加介电层136的去除速率，可以有意地引入凹陷，从而允许介电层136凹进至导电通孔134的顶部之下的距离D2。
在一些实施例中，去除工艺是CMP以及随后的回蚀刻工艺。CMP的参数选择为避免介电层136的凹陷。可以通过选择上述CMP的参数来避免凹陷，从而使得导电通孔134和介电层136的去除速率类似。在实施CMP之后，导电通孔134和介电层136的顶面基本齐平。之后，实施回蚀刻工艺以减薄介电层136。回蚀刻工艺以比导电通孔134更高的速率去除介电层136。例如，回蚀刻工艺可以使用对介电层136的有机材料具有选择性的蚀刻剂(诸如Ar或O2)的干蚀刻工艺来实施。
在整体平坦化工艺中，去除介电层136的位于导电通孔134上方的部分可以比去除介电层136的剩余部分更快。例如，在同一CMP工艺中，突出部分处的介电层136的去除速率可以比沿着主表面的介电层136的去除速率快达十倍，尤其当介电层136经历部件载荷时。因此，可以实施较少的平坦化来暴露穿过介电层136的导电通孔134并且平坦化介电层136。
在图10中，导线144形成在介电层136上，电连接至导电通孔134。下一步，形成电连接至导线144的导电通孔146。之后，在导线144和导电通孔146上和周围沉积介电层148。图11A至图11G是示出在用于形成导线144、导电通孔146和介电层148的工艺期间区域650的更多细节的截面图。
在图11A中，在导电通孔134和介电层136上方形成晶种层150。具体地，晶种层150沿着介电层136的顶面、导电通孔134的暴露侧壁和导电通孔134的顶面延伸。在一些实施例中，晶种层150是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层150包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层150。
在图11B中，在晶种层150上形成并且图案化掩模层152。掩模层152可以是光刻胶，诸如单层光刻胶、三层光刻胶等。掩模层152可以通过旋涂等形成，并且可以暴露于光以用于图案化。掩模层152的图案对应于导线144。图案化形成穿过掩模层152的开口154以暴露晶种层150。因为下面的介电层136的主表面是平坦的，所以掩模层152可以形成为基本均匀的厚度。因此，可以更一致地显影掩模层152，这可以减小残留的掩模层152覆盖开口154中的晶种层150的部分的可能性。
在图11C中，在掩模层152的开口154中和晶种层150的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除掩模层152。在掩模层152是光刻胶的实施例中，可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除掩模层152。导电材料和晶种层的位于导电材料下方的部分形成导线144。因为导电通孔134在介电层136之上延伸，所以导线144的部分具有凸起的拓扑结构。导线144的位于导电通孔134上方的部分可以具有凸形形状，从而使得导线144的位于导电通孔134上方的顶面在导线144的没有位于导电通孔134上方的顶面之上升高距离D3。距离D3可以在从约0μm至约0.2μm。换句话说，导线144在导电通孔134上方不具有凹槽。在一些实施例中，诸如距离D2较小的实施例中，导线144的位于导电通孔134上方的部分可以不是凸形形状，而是可以是基本平坦的。在形成之后，导电通孔134和晶种层150部分地延伸至相应的导线144内，从而在导电通孔134和导线144之间形成锚固连接。
在图11D中，在导线144和晶种层150上形成并且图案化掩模层156。掩模层156可以是光刻胶，诸如单层光刻胶、三层光刻胶等。掩模层156可以通过旋涂等形成，并且可以暴露于光以用于图案化。掩模层156的图案对应于导电通孔146。图案化形成穿过掩模层156的开口158以暴露导线144的部分。因为下面的介电层136的主表面是平坦的，所以掩模层156可以形成为基本均匀的厚度。因此，可以更一致地显影掩模层156，这可以减小残留的掩模层156覆盖开口158中的导线144的部分的可能性。
在图11E中，在掩模层156的开口158中和导线144的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。
下一步，去除掩模层156和晶种层150的其上未形成导线144的部分。在掩模层156是光刻胶的实施例中，可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除掩模层156。一旦去除掩模层156，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层150的暴露部分。开口158中的导电材料形成导电通孔146。
在图11F中，在介电层136、导线144和导电通孔146上沉积介电层148。在一些实施例中，介电层148由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层148由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层148。具体地，介电层148共形地沉积在导线144和导电通孔146上方，从而使得导电通孔146的最顶表面在介电层148的主表面之上延伸距离D4。距离D4可以在从约0.1μm至约0.5μm，并且可以与距离D1相同。换句话说，介电层148是下沉积的，从而使得相邻导电通孔146之间的介电层148的部分凹进在导电通孔146的顶面下面。
在图11G中，实施去除工艺以去除介电层148的部分，从而暴露导电通孔146。去除工艺减薄导电通孔146和介电层148。去除工艺可以与以上图9D中所示的去除工艺类似。
在图12中，导线160形成在介电层148上，电连接至导电通孔146。下一步，形成电连接至导线160的导电通孔162。之后，在导线160和导电通孔162上和周围沉积介电层164。导线160、导电通孔162和介电层164可以以与导线144、导电通孔146和介电层148类似的方式形成。
在图13中，导线166形成在介电层164上，电连接至导电通孔162。下一步，形成电连接至导线166的导电通孔168。之后，在导线166和导电通孔168上和周围沉积介电层170。导线166、导电通孔168和介电层170可以以与导线144、导电通孔146和介电层148类似的方式形成。
前侧再分布结构132示出为实例。可以在前侧再分布结构132中形成更多或更少的介电层、金属化图案和导电通孔。如果要形成更少的介电层、金属化图案和导电通孔，则可以省略以上讨论的步骤和工艺。如果要形成更多的介电层、金属化图案和导电通孔，则可以重复以上讨论的步骤和工艺。本领域普通技术人员将容易理解，可以省略或重复哪些步骤和工艺。
在图14中，在前侧再分布结构132的外侧上形成导电焊盘172。导电焊盘172可以称为凸块下金属(UBM)。在示出的实施例中，形成电和物理连接至导电通孔168的导电焊盘172。导电焊盘172以与导线144、160、166类似的方式形成，从而使得导电通孔168延伸至导电焊盘172内。作为形成导电焊盘172的实例，在介电层170和通孔168上方以及导电通孔168的侧壁上形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于导电焊盘172。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成导电焊盘172。
在图15中，在导电焊盘172上形成导电连接件174。导电连接件174可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件174可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成导电连接件174。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件174是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
在图16中，实施载体衬底脱粘以将载体衬底100从背侧再分布结构110(例如，介电层104)分离(脱粘)。从而在第一封装区域600和第二封装区域602的每个中形成第一封装件200。根据一些实施例，脱粘包括将诸如激光或UV光的光投射到释放层102上，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转该结构并且放置在带176上。此外，穿过介电层104形成暴露金属化图案106的部分的开口178。可以例如使用激光钻孔、蚀刻等形成开口178。
图17至图18示出了根据一些实施例的在用于形成封装结构500的工艺期间的中间步骤的截面图。封装结构500可以称为叠层封装(PoP)结构。
在图17中，将第二封装件300附接至第一封装件200。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。虽然示出了管芯308(308A和308B)的单个堆叠件，但是在其它实施例中，多个堆叠管芯308(每个均具有一个或多个堆叠管芯)可以并排设置为连接至衬底302的同一表面。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底302是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其它印刷电路板(PCB)材料或薄膜。对于衬底302，可以使用诸如味之素积聚膜(ABF)或其它层压材料的积聚膜。
衬底302可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于第二封装件300的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
衬底302也可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底302基本无有源和无源器件。
衬底302可以具有位于衬底302的第一侧上以连接至堆叠管芯308的接合焊盘303，以及位于衬底302的第二侧上以连接至导电连接件314的接合焊盘304，衬底302的第二侧与第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入至介电层内。在其它实施例中，由于接合焊盘303和304可以形成在介电层上，因此省略凹槽。在一些实施例中，接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘303和304是UBM，其包括三个导电材料层，诸如钛层、铜层和镍层。然而，本领域普通技术人员将意识到，存在适合于形成接合焊盘303和304的许多合适的材料和层的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于接合焊盘303和304的任何合适的材料或材料层均完全旨在包括在本申请的范围内。在一些实施例中，通孔306穿过衬底302延伸并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，通过引线接合310将堆叠管芯308连接至衬底302，但是也可以使用诸如导电凸块的其它连接。在实施例中，堆叠管芯308是堆叠的存储器管芯。例如，堆叠管芯308可以是诸如低功率(LP)双数据率(DDR)存储器模块(诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块)的存储器管芯。
堆叠管芯308和引线接合310可以由模塑材料312密封。可以例如使用压缩模塑将模塑材料312模塑在堆叠管芯308和引线接合310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料312，其中，固化可以是热固化、UV固化等或它们的组合。
在一些实施例中，将堆叠管芯308和引线接合310掩埋在模塑材料312中，并且在模塑材料312的固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过导电连接件314、接合焊盘304和金属化图案106将第二封装件300机械和电接合至第一封装件200。在一些实施例中，可以通过引线接合310、接合焊盘303和304、通孔306、导电连接件314和通孔112将堆叠管芯308连接至集成电路管芯114。
导电连接件314可以与以上描述的导电连接件174类似，并且此处不再重复描述，但是导电连接件314和导电连接件174不需要是相同的。导电连接件314可以在开口178中设置在衬底302的与堆叠管芯308相对的侧上。在一些实施例中，阻焊剂也可以形成在衬底302的与堆叠管芯308相对的侧上。导电连接件314可以设置在阻焊剂中的开口中以电和机械连接至衬底302中的导电部件(例如，接合焊盘304)。阻焊剂可以用于保护衬底302的区免受外部损坏。
在一些实施例中，在接合导电连接件314之前，导电连接件314涂覆有焊剂(未示出)，诸如免洗焊剂。导电连接件314可以浸入焊剂中，或可以将焊剂喷射到导电连接件314上。在另一实施例中，可以将焊剂施加至金属化图案106的表面。
在一些实施例中，导电连接件314可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将第二封装件300附接至第一封装件200之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。
可以在第一封装件200和第二封装件300之间以及围绕导电连接件314形成底部填充物(未示出)。底部填充物可以减小应力并且保护由导电连接件314的回流产生的接头。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。在形成环氧树脂焊剂的实施例中，环氧树脂焊剂可以用作底部填充物。
第二封装件300和第一封装件200之间的接合可以是焊料接合。在实施例中，通过回流工艺将第二封装件300接合至第一封装件200。在该回流工艺期间，导电连接件314与接合焊盘304和金属化图案106接触，以将第二封装件300物理和电连接至第一封装件200。在接合工艺之后，金属间化合物(IMC，未示出)可以形成在金属化图案106和导电连接件314的界面处并且也形成在导电连接件314和接合焊盘304之间的界面(未示出)处。
通过沿着划线区域(例如，在第一封装区域600和第二封装区域602之间)锯切来实施分割工艺。锯切分割第一封装区域600与第二封装区域602。产生来自第一封装区域600或第二封装区域602的一个的分割的第一封装件200和第二封装件300。在一些实施例中，在第二封装件300附接至第一封装件200之后实施分割工艺。在其它实施例(未示出)中，在将第二封装件300附接至第一封装件200之前，诸如在将载体衬底100脱粘并且形成开口178之后，实施分割工艺。
在图18中，使用导电连接件174将第一封装件200安装至封装衬底400。封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底400是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其PCB材料或薄膜。对于封装衬底400可以使用诸如ABF或其它层压材料的积聚膜。
封装衬底400可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于封装结构500的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底400基本无有源和无源器件。
在一些实施例中，回流导电连接件174以将第一封装件200附接至接合焊盘402。导电连接件174将包括封装衬底400中的金属化层的封装衬底400电和/或物理连接至第一封装件200。在一些实施例中，在安装在封装衬底400上之前，可以将无源器件(例如，未示出的表面安装器件(SMD))附接至第一封装件200(例如，接合至接合焊盘402)。在这种实施例中，无源器件可以与导电连接件174接合至第一封装件200的同一表面。
在一些实施例中，导电连接件174可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将第一封装件200附接至封装衬底400之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件174的回流产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件200和封装衬底400之间并且围绕导电连接件174。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。
实施例可以实现许多优势。在导电通孔和金属化图案之间形成锚固连接可以改进导电通孔和金属化图案之间的界面的机械强度，从而改进器件可靠性。此外，在导电通孔上方和周围的下沉积介电层可以允许导电通孔更容易穿过介电层暴露，从而减小形成盲孔(例如，未穿过相应的介电层完全暴露的通孔)的可能性。
在实施例中，器件包括：集成电路管芯；与集成电路管芯相邻的通孔；密封集成电路管芯和通孔的模塑料；以及再分布结构，包括：穿过第一介电层延伸的第一导电通孔，第一导电通孔电连接至集成电路管芯，第一介电层位于集成电路管芯、通孔和模塑料上方；以及位于第一介电层和第一导电通孔上方的第一导线，第一导电通孔延伸至第一导线内。
在一些实施例中，第一导电通孔的最顶表面在第一介电层的最顶表面之上延伸。在一些实施例中，第一导线包括：晶种层，沿着第一介电层的最顶表面、第一导电通孔的侧面和第一导电通孔的最顶表面延伸；以及设置在晶种层上的导电材料。在一些实施例中，第一导线具有第一部分和第二部分，第一部分设置在第一导电通孔上方，第一部分的最顶表面设置为比第二部分的最顶表面离第一介电层更远。在一些实施例中，再分布结构还包括：穿过第二介电层延伸的第二导电通孔，第二导电通孔电连接至第一导线，第二介电层位于第一介电层和第一导线上方。在一些实施例中，该器件还包括：位于第二介电层和第二导电通孔上方的导电焊盘，第二导电通孔延伸至导电焊盘内；以及位于导电焊盘上的导电连接件。在一些实施例中，该器件还包括：连接至导电连接件的第一衬底；以及连接至通孔的第二衬底。在一些实施例中，第一导线的位于第一导电通孔上方的部分具有凸形形状。
在实施例中，方法包括：用模塑料密封集成电路管芯，集成电路管芯具有管芯连接件；在集成电路管芯的管芯连接件上形成第一导电通孔；在集成电路管芯、模塑料和第一导电通孔上方沉积第一介电层，第一介电层沿着第一导电通孔的侧壁和顶面延伸，第一导电通孔的顶面位于第一介电层的主表面之上；去除第一介电层的位于第一导电通孔的侧壁和顶面上的部分，从而暴露第一导电通孔的部分；以及在第一介电层和第一导电通孔的暴露部分上形成第一导线。
在一些实施例中，去除第一介电层的部分包括：对第一介电层实施平坦化工艺，在平坦化工艺之后，暴露第一导电通孔的侧壁和顶面。在一些实施例中，平坦化工艺以在从2PSI至5PSI的向下压力实施，直至第一导电通孔的暴露部分在第一介电层的主表面之上延伸0.1μm至0.5μm的距离。在一些实施例中，去除第一介电层的部分包括：对第一介电层和第一导电通孔实施平坦化工艺，第一介电层和第一导电通孔的顶面齐平；对第一介电层实施蚀刻工艺，在蚀刻工艺之后，暴露第一导电通孔的侧壁和顶面。在一些实施例中，第一介电层是有机介电材料，并且蚀刻工艺是利用Ar或O2实施的干蚀刻工艺。在一些实施例中，第一导线的位于第一导电通孔上方的部分具有凸形形状。在一些实施例中，第一导线的位于第一导电通孔上方的部分具有平坦的形状。
在实施例中，方法包括：将集成电路管芯放置在第一介电层上，集成电路管芯具有管芯连接件；用模塑料密封集成电路管芯；在集成电路管芯的管芯连接件上形成第一导电通孔，第一导电通孔具有设置为离第一介电层层第一距离的最顶表面；在集成电路管芯、模塑料和第一导电通孔上沉积第二介电层，第二介电层具有设置为离第一介电层第二距离的主表面，第一距离大于第二距离；去除第一介电层的部分以暴露第一导电通孔的侧面和最顶表面；以及在第一导电通孔上形成第一导线，第一导线接触第一导电通孔的侧面和最顶表面。
在一些实施例中，形成第一导电通孔包括：在集成电路管芯和模塑料上沉积第一晶种层；在第一晶种层上形成第一掩模层；在第一掩模层中图案化第一开口；在第一开口中镀第一导电材料；以及去除第一掩模层和第一晶种层的暴露部分，第一导电材料和第一晶种层的剩余部分形成第一导电通孔。在一些实施例中，形成第一导线包括：在第二介电层上以及第一导电通孔的侧面和最顶表面上沉积第二晶种层；在第二晶种层上形成第二掩模层；在第一导电通孔上方的第二掩模层中图案化第二开口；以及在第二开口中从第二晶种层镀第二导电材料，第二导电材料和第二晶种层的位于第二导电材料下面的部分形成第一导线。在一些实施例中，该方法还包括：在第二导电材料和第二晶种层上形成第三掩模层；在第二导电材料上方的第三掩模层中图案化第三开口；在第三开口中从第二导电材料镀第三导电材料；去除第三掩模层和第二晶种层的暴露部分，第三导电材料和第二晶种层的剩余部分形成第二导电通孔；以及在第二介电层、第一导线和第二导电通孔上沉积第三介电层。在一些实施例中，第一导电材料的位于第一导电通孔上方的部分具有凸形形状。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体封装件，包括：
集成电路管芯；
通孔，与所述集成电路管芯相邻；
模塑料，密封所述集成电路管芯和所述通孔；以及
再分布结构，包括：
第一导电通孔，穿过第一介电层延伸，所述第一导电通孔的最顶表面在所述第一介电层的最顶表面之上延伸，所述第一导电通孔电连接至所述集成电路管芯，所述第一介电层位于所述集成电路管芯、所述通孔和所述模塑料上方；以及
第一导线，位于所述第一介电层和所述第一导电通孔上方，其中，所述第一导线具有彼此连接的第一部分和第二部分，所述第一部分设置在所述第一导电通孔上方，所述第一部分的最顶表面设置为比所述第二部分的最顶表面离所述第一介电层更远。
2.根据权利要求1所述的半导体封装件，其中，所述第一导电通孔的最顶表面在所述第一介电层的最顶表面之上延伸的距离在0.1μm至0.3μm的范围之间。
3.根据权利要求2所述的半导体封装件，其中，所述第一导线包括：
晶种层，沿着所述第一介电层的最顶表面、所述第一导电通孔的侧面和所述第一导电通孔的最顶表面延伸；以及
导电材料，设置在所述晶种层上。
4.根据权利要求3所述的半导体封装件，其中，所述晶种层包括钛层和位于所述钛层上的铜层。
5.根据权利要求1所述的半导体封装件，其中，所述再分布结构还包括：
第二导电通孔，穿过第二介电层延伸，所述第二导电通孔电连接至所述第一导线，所述第二介电层位于所述第一介电层和所述第一导线上方。
6.根据权利要求5所述的半导体封装件，还包括：
导电焊盘，位于所述第二介电层和所述第二导电通孔上方，所述第二导电通孔延伸至所述导电焊盘内；以及
导电连接件，位于所述导电焊盘上。
7.根据权利要求6所述的半导体封装件，还包括：
第一衬底，连接至所述导电连接件；以及
第二衬底，连接至所述通孔。
8.根据权利要求6所述的半导体封装件，其中，所述第一导线的位于所述第一导电通孔上方的部分具有凸形形状。
9.一种形成半导体封装件的方法，包括：
用模塑料密封集成电路管芯，所述集成电路管芯具有管芯连接件；
在所述集成电路管芯的所述管芯连接件上形成第一导电通孔；
在所述集成电路管芯、所述模塑料和所述第一导电通孔上方沉积第一介电层，所述第一介电层沿着所述第一导电通孔的侧壁和顶面延伸，所述第一导电通孔的顶面位于所述第一介电层的主表面之上；
去除所述第一介电层的位于所述第一导电通孔的侧壁和顶面上的部分，从而暴露所述第一导电通孔的侧壁的部分和顶面；以及
在所述第一介电层和所述第一导电通孔上形成第一导线，所述第一导线接触所述第一导电通孔的所述侧壁的部分和所述顶面。
10.根据权利要求9所述的方法，其中，去除所述第一介电层的部分包括：
对所述第一介电层实施平坦化工艺，在所述平坦化工艺之后，暴露所述第一导电通孔的所述侧壁的部分和所述顶面。
11.根据权利要求10所述的方法，其中，所述平坦化工艺以从2PSI至5PSI的向下压力实施，直至所述第一导电通孔的暴露部分在所述第一介电层的主表面之上延伸0.1μm至0.5μm的距离。
12.根据权利要求9所述的方法，其中，去除所述第一介电层的部分包括：
对所述第一介电层和所述第一导电通孔实施平坦化工艺，所述第一介电层和所述第一导电通孔的所述顶面齐平；
对所述第一介电层实施蚀刻工艺，在蚀刻工艺之后，暴露所述第一导电通孔的所述侧壁的部分和所述顶面。
13.根据权利要求12所述的方法，其中，所述第一介电层是有机介电材料，并且所述蚀刻工艺是利用Ar或O2实施的干蚀刻工艺。
14.根据权利要求9所述的方法，其中，所述第一导线的位于所述第一导电通孔上方的部分具有凸形形状。
15.根据权利要求9所述的方法，其中，所述第一导线的位于所述第一导电通孔上方的部分具有平坦的形状。
16.一种形成半导体封装件的方法，包括：
将集成电路管芯放置在第一介电层上，所述集成电路管芯具有管芯连接件；
用模塑料密封所述集成电路管芯；
在所述集成电路管芯的所述管芯连接件上形成第一导电通孔，所述第一导电通孔具有设置为离所述第一介电层第一距离的最顶表面；
在所述集成电路管芯、所述模塑料和所述第一导电通孔上沉积第二介电层，所述第二介电层具有设置为离所述第一介电层第二距离的主表面，所述第一距离大于所述第二距离；
去除所述第二介电层的部分以暴露所述第一导电通孔的侧面和最顶表面；以及
在所述第一导电通孔上形成第一导线，所述第一导线接触所述第一导电通孔的侧面和最顶表面。
17.根据权利要求16所述的方法，其中，形成所述第一导电通孔包括：
在所述集成电路管芯和所述模塑料上沉积第一晶种层；
在所述第一晶种层上形成第一掩模层；
在所述第一掩模层中图案化第一开口；
在所述第一开口中镀第一导电材料；以及
去除所述第一掩模层和所述第一晶种层的暴露部分，所述第一导电材料和所述第一晶种层的剩余部分形成所述第一导电通孔。
18.根据权利要求17所述的方法，其中，形成所述第一导线包括：
在所述第二介电层上以及所述第一导电通孔的侧面和最顶表面上沉积第二晶种层；
在所述第二晶种层上形成第二掩模层；
在所述第一导电通孔上方的所述第二掩模层中图案化第二开口；以及
在所述第二开口中从所述第二晶种层镀第二导电材料，所述第二导电材料和所述第二晶种层的位于所述第二导电材料下面的部分形成所述第一导线。
19.根据权利要求18所述的方法，还包括：
在所述第二导电材料和所述第二晶种层上形成第三掩模层；
在所述第二导电材料上方的所述第三掩模层中图案化第三开口；
在所述第三开口中从所述第二导电材料镀第三导电材料；
去除所述第三掩模层和所述第二晶种层的暴露部分，所述第三导电材料和所述第二晶种层的剩余部分形成第二导电通孔；以及
在所述第二介电层、所述第一导线和所述第二导电通孔上沉积第三介电层。
20.根据权利要求18所述的方法，其中，所述第一导电材料的位于所述第一导电通孔上方的部分具有凸形形状。
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