CN108735684B - 多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法 - Google Patents

多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法 Download PDF

Info

Publication number
CN108735684B
CN108735684B CN201710888309.2A CN201710888309A CN108735684B CN 108735684 B CN108735684 B CN 108735684B CN 201710888309 A CN201710888309 A CN 201710888309A CN 108735684 B CN108735684 B CN 108735684B
Authority
CN
China
Prior art keywords
pads
semiconductor
pad
tilted
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710888309.2A
Other languages
English (en)
Other versions
CN108735684A (zh
Inventor
林柏均
朱金龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of CN108735684A publication Critical patent/CN108735684A/zh
Application granted granted Critical
Publication of CN108735684B publication Critical patent/CN108735684B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16108—Disposition the bump connector not being orthogonal to the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法，半导体晶片包含半导体元件。半导体元件具有上表面以及对应至上表面的下表面。半导体元件包含输入端子、多个硅晶穿孔连接块、多个选择焊垫、多个倾斜焊垫以及多个倾斜导电结构。硅晶穿孔连接块延伸穿越半导体元件。选择焊垫位于下表面。倾斜焊垫位于上表面且通过硅晶穿孔连接块分别连接至选择焊垫。每个倾斜焊垫具有焊垫表面，其不平行于上表面。每个倾斜导电结构的底端接触对应的倾斜焊垫的焊垫表面，且每个倾斜导电结构的顶端垂直的对齐紧邻的倾斜焊垫。本发明具有以节省成本和生产效率的结构设计与生产方法达到晶片选择的功能。

Description

多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法
技术领域
本发明是关于一种半导体封装技术，特别是关于一种具有晶片选择焊垫的多晶片封装及其制造方法。
背景技术
为了满足增加半导体装置集成度和多功能性的迫切需求，近年来已经开发了各种半导体多晶片封装。
如下所述制造传统的半导体多晶片封装。在制造晶片并将晶片切割成多个单独的晶片之后，晶片被附接并电连接到基板，并且用模制树脂封装以形成封装体。然后，通过堆叠封装获得多晶片的封装体。
传统的多晶片封装通过使用复杂的工艺堆叠多个封装体而形成。此外，这些多晶片封装的尺寸比标准晶片大得多，从而降低了安装密度。此外，由于多晶片封装采用基板，它们拉长了信号传输路径，从而产生信号延迟的结果。
为了通过堆叠相同类型的存储器晶片来提高存储器容量，必须存在用于操作所需的存储器晶片的晶片选择机制。因此，每个存储器晶片需包括晶片选择端子。例如，在DRAM晶片的情况下，使用列位址选通(RAS)、行位址选通(CAS)或晶片选择接脚(CSP)作为晶片选择端子。通过选择性地将电子信号发送到与多晶片封装的所需晶片对应的特定晶片选择端子，对选择所需的晶片进行操作。多晶片封装中的存储器晶片的其他非选择端子通常连接在一起，但是每个单独晶片的晶片选择端子被隔离并连接到外部电子元件。
在上述多晶片封装中公开了用于将每个晶片的晶片选择端彼此分离的公知技术。也就是说，每个晶片的晶片选择端子通过形成在封装的基板上的连接布线连接到外部电子部件。因此，为了将每个晶片的晶片选择端子彼此分开，每个基板应包含与其它基板不同的连接布线构造，因而增加了生产成本并降低了生产率。
发明内容
本发明的目的在于提供一种具有以节省成本和生产效率的结构设计与生产方法达到晶片选择功能的多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法。
在本发明的一实施例中，一种半导体晶片包含半导体元件。半导体元件具有上表面以及对应至上表面的下表面。半导体元件包含输入端子、多个硅晶穿孔连接块、多个选择焊垫、多个倾斜焊垫以及多个倾斜导电结构。多个硅晶穿孔连接块延伸穿越半导体元件，其中这些硅晶穿孔连接块的其中之一连接至输入端子。多个选择焊垫位于下表面，其中这些选择焊垫的其中之一连接至输入端子，而这些选择焊垫的其余者分别连接至这些硅晶穿孔连接块的其余者。多个倾斜焊垫位于上表面且通过这些硅晶穿孔连接块分别连接至这些选择焊垫，其中每个倾斜焊垫具有焊垫表面，其不平行于上表面。多个倾斜导电结构分别位于对应的这些倾斜焊垫上，每个倾斜导电结构的底端接触对应的倾斜焊垫的焊垫表面，且每个倾斜导电结构的顶端垂直的对齐紧邻的倾斜焊垫。
在本发明的一实施例中，一种多晶片半导体封装体包含N个垂直堆叠的半导体晶片。每个半导体晶片包含半导体元件。半导体元件具有上表面以及对应至上表面的下表面。半导体元件包含输入端子、M个硅晶穿孔连接块、多个选择焊垫、(M-1)个倾斜焊垫以及多个倾斜导电结构。硅晶穿孔连接块延伸穿越半导体元件，其中M≥N，这些硅晶穿孔连接块的其中之一连接至输入端子。选择焊垫位于下表面，其中这些选择焊垫的其中之一连接至输入端子，而这些选择焊垫的其余者分别连接至这些硅晶穿孔连接块的其余者。多个倾斜焊垫位于上表面且通过这些硅晶穿孔连接块分别连接至这些选择焊垫，其中每个倾斜焊垫具有焊垫表面，其不平行于上表面。倾斜导电结构分别位于对应的倾斜焊垫上，每个倾斜导电结构的底端接触对应的倾斜焊垫的焊垫表面，且每个倾斜导电结构的顶端垂直的对齐紧邻的倾斜焊垫。
在本发明的一实施例中，一种方法用以垂直堆叠多个所述的半导体晶片而形成多晶片半导体封装体，该方法在这些半导体晶片的侧边对齐状况下垂直堆叠，且每个倾斜导电结构的顶端接触紧邻的半导体晶片上对应的选择焊垫，其中对应的选择焊垫是垂直对齐每个倾斜导电结构的底端紧邻的倾斜焊垫。
在本发明的一实施例中，每个倾斜导电结构包含柱状部以及锡球部。柱状部自每个倾斜焊垫的焊垫表面向上延伸。锡球部位于柱状部远离倾斜焊垫的一端，其中锡球部垂直的对齐紧邻的倾斜焊垫。
在本发明的一实施例中，这些柱状部均彼此相互平行。
在本发明的一实施例中，上表面具有多个V型槽，且这些倾斜焊垫是分别共形的形成于这些V型槽上。
在本发明的一实施例中，每个V型槽的两内表面夹角为90度。
在本发明的一实施例中，半导体元件还包含保护层，多条导电通道于保护层内延伸，其中这些倾斜焊垫分别通过这些条导电通道连接至这些硅晶穿孔连接块。
在本发明的一实施例中，这些倾斜焊垫彼此间隔，且每个倾斜导电结构的顶端在垂直方向超出其底端连接的倾斜焊垫。
在本发明的一实施例中，这些倾斜焊垫彼此间隔，且每个倾斜导电结构的锡球部在垂直方向超出倾斜导电结构的柱状部连接的倾斜焊垫。
在本发明的一实施例中，N个半导体晶片是以其侧边对齐状况下垂直堆叠。
在本发明的一实施例中，这些选择焊垫中最外侧的选择焊垫连接至输入端子。
在本发明的一实施例中，多晶片半导体封装体还包含外接基材，外接基材包含多个电连接锡球，其分别连接至这些半导体晶片的最底者的这些选择焊垫。
综上所述，本发明公开具有倾斜导电结构的半导体元件，能通过垂直堆叠方式形成多晶片半导体封装体，且以具有节省成本和生产效率的结构设计与生产方法达到晶片选择的功能。
以下将以实施方式对上述的说明作详细的描述，并对本发明的技术方案提供更进一步的解释。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂，结合附图说明如下：
图1是绘示依照本发明一实施例的一种半导体元件的剖面图；
图2是绘示图1的半导体元件部分的放大图；
图3是绘示依照本发明一实施例的一种多晶片半导体封装体的剖面图；以及
图4～图9是绘示依照本发明一实施例的半导体元件的制造方法步骤的剖面图。
具体实施方式
为了使本发明的叙述更加详尽与完备，可参照所附的附图及以下所述各种实施例，附图中相同的号码代表相同或相似的元件。另一方面，众所周知的元件与步骤并未描述于实施例中，以避免对本发明造成不必要的限制。
请同时参照图1、图2，图1是绘示依照本发明一实施例的一种半导体元件的剖面图，图2是绘示图1的半导体元件部分的放大图。半导体晶片包含半导体元件100，其具有上表面102与对应上表面102的下表面104。半导体元件100包含输入端子106、多个硅晶穿孔连接块(through silicon via)108、多个选择焊垫(110a,110b)、多个倾斜焊垫(112a,112b,112c)以及多个倾斜导电结构。
在一实施例中，每个倾斜导电结构包含柱状部114以及锡球部116。柱状部114从每个倾斜焊垫112的焊垫表面(113a或113b)向上延伸，且焊垫表面(113a或113b)是不平行于半导体元件100的上表面102。换言之，每个倾斜导电结构的底端(例如柱状部114)是接触倾斜焊垫112的焊垫表面(113a或113b)。锡球部116位于柱状部114远离倾斜焊垫112的一端(即远离焊垫表面(113a或113b)的一端)。
在一实施例中，倾斜焊垫(112a,112b,112c)是彼此间隔，即彼此电性分离或绝缘。如图2所绘示，每个倾斜导电结构的顶端在垂直方向超出其底端连接的该倾斜焊垫112。换言之，每个倾斜导电结构的锡球部116在垂直方向超出倾斜导电结构的柱状部114连接的倾斜焊垫112。
这里倾斜导电结构一词中的“倾斜”，意味着倾斜导电结构的长度方向偏离半导体元件100上表面102的法线方向102a一个夹角θ(即大于零度的角)。
在一实施例中(请参照图1)，每个倾斜导电结构的顶端(例如锡球部116)在垂直方向超出其底端(例如柱状部114)连接的倾斜焊垫(例如112a)，且每个倾斜导电结构的顶端(例如锡球部116)垂直的对齐紧邻的倾斜焊垫(例如112b)，但导电结构的顶端(例如锡球部116)仍与紧邻的倾斜焊垫(例如112b)之间有间隔(例如彼此电性绝缘或分离)。
硅晶穿孔连接块108延伸于半导体元件100内，且硅晶穿孔连接块108的其中之一连接至输入端子106。选择焊垫(110a,110b)位于半导体元件100的下表面104，其中选择焊垫110a连接至输入端子106，而其余的选择焊垫110b分别连接至其余的硅晶穿孔连接块108。在本实施例中，连接至输入端子106的选择焊垫110a为所有选择焊垫最外侧者，而其余的选择焊垫110b分别连接至其余的硅晶穿孔连接块108。倾斜焊垫(112a,112b,112c)位于上表面102，且经由硅晶穿孔连接块108分别连接至选择焊垫110b。每个倾斜焊垫112包含焊垫表面(113a或113b)，其不平行于上表面102。倾斜导电结构(即114及116)位于对应的倾斜焊垫s(112a,112b,112c)上。每个倾斜导电结构的底端接触每个倾斜焊垫112的焊垫表面(113a或113b)，且每个倾斜导电结构的顶端(例如锡球部116)垂直的对齐紧邻的倾斜焊垫(例如112b)。
请参照图3，其绘示依照本发明一实施例的一种多晶片半导体封装体200的剖面图。多晶片半导体封装体200是通过垂直堆叠N个相同的半导体元件(100a,100b,100c)所形成。半导体元件的数量(N)应小于或等于硅晶穿孔连接块108的数量(M)。例如，每个半导体元件(100a,100b,100c)上具有4个硅晶穿孔连接块108，最多能垂直堆叠的半导体晶片数量是4个，但3个或2个半导体晶片当然也可行。在本实施例中，3个半导体元件(100a,100b,100c)以其所有侧边(130a,130b)对齐状况下垂直堆叠，且每个半导体元件有4个硅晶穿孔连接块108，因此还能再多堆叠另一个半导体元件。
在每个半导体元件(100a,100b,100c)内，(M-1)个倾斜焊垫(112a,112b,112c)位于上表面，且经硅晶穿孔连接块108分别连接至位于下表面的选择焊垫110。因此，晶片选取功能即通过图3上的箭号传递信号达到功能。每个晶片上设计越多的倾斜焊垫以及倾斜导电结构，即能使多晶片半导体封装体能垂直堆叠更多的晶片且具有晶片选取功能。
当3个半导体元件(100a,100b,100c)垂直堆叠时，每个倾斜导电结构从堆叠较下方的半导体晶片(例如100c)的每个倾斜焊垫(例如112a)延伸而上而接触堆叠较上方的半导体晶片(例如100b)对应的选择焊垫。而堆叠上方的半导体晶片对应的选择焊垫(例如110)是垂直对齐堆叠较下方的半导体晶片(例如100c)上紧邻倾斜焊垫(例如112b)。
在本实施例中，从每个倾斜焊垫向上延伸的这些柱状部114均彼此平行(就其长度方向而言)。例如，从倾斜焊垫112a向上延伸的柱状部114平行于从紧邻的倾斜焊垫112b向上延伸的柱状部114。在其他实施例中，这些柱状部114或许无法完全彼此相互平行，但只要柱状部114或锡球部116能彼此电性分隔或电性绝缘即可。
如图3所绘示，外接基材120可用以垂直堆叠(N)个半导体元件(100a,100b,100c)。换言之，最底层的半导体元件100c接合于外接基材120上，使其选择焊垫110焊接于外接基材120对应的焊垫126上。外接基材120仍具有金属内走线124以及下表面的焊接锡球122用以连接至其他的应用装置中。
在3个半导体元件(100a,100b,100c)垂直堆叠在外接基材120上后，环氧树脂的封装胶体(未绘示于图面)即可用以封装3个半导体元件(100a,100b,100c)并填入元件间的间隙(例如倾斜导电结构间的间隙)，而能形成多晶片半导体封装体200。
请参照图4～图9，其绘示依照本发明一实施例的半导体元件的制造方法步骤的剖面图。
请参照图4，提供半导体基材101且硅晶穿孔连接块108形成于其内。硅晶穿孔连接块108可由铜或其合金所制成。
请参照图5，保护层103形成于半导体基材101的上表面，且选择焊垫110形成于半导体基材101的下表面。导电通道105接着形成于保护层103内。
请参照图6，硬罩幕140形成于保护层103上，且经图案化后形成开孔142以裸露出欲蚀刻的区域。
请参照图7，激光150或其他蚀刻方式用以蚀刻V型槽107(通过开孔142)于半导体元件的上表面。在本实施例中，每个V型槽107的两个表面(107a,107b)之间的夹角θ约90度。
请参照图8，移除硬罩幕140，且倾斜焊垫112以共形方式(conformal)的形成于V型槽107的内表面而形成焊垫表面(113a或113b)，两焊垫表面皆不平行于半导体元件的上表面。倾斜焊垫112的一部分延伸出V型槽107外，而经导电通道105及硅晶穿孔连接块108连接至对应的选择焊垫110。
请参照图9，柱状部114形成于倾斜焊垫112的焊垫表面(113a或113b)，而锡球部116形成于柱状部114的顶端且远离倾斜焊垫112的焊垫表面(113a或113b)。柱状部114的材质为铜或其合金，且锡球部116的材质为焊接材料，例如共晶的锡及/或铅。
因此，具有单一倾斜导电结构的半导体元件即能以上述步骤制成。具有多个倾斜导电结构的半导体元件也能以类似上述步骤的方法制成，而形成多晶片半导体封装体所需的单一晶片。例如多个半导体积体电路形成于晶圆上，而切割成多个相同的晶片单元，而多个具有倾斜导电结构的晶片单元即能垂直堆叠(例如以加热方式)而形成如图3的多晶片半导体封装体200。晶片选取功能即能沿着选择焊垫与倾斜导电结构等传递沟通信号而达到。
综上所述，本发明公开具有倾斜导电结构的半导体元件，能通过垂直堆叠方式形成多晶片半导体封装体，且以具有节省成本和生产效率的结构设计与生产方法达到晶片选择的功能。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何所属领域的一般技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (20)

1.一种半导体晶片，其特征在于，包含：
半导体元件，具有上表面以及对应至所述上表面的下表面，其中所述半导体元件包含：
输入端子；
多个硅晶穿孔连接块，延伸穿越所述半导体元件，其中所述多个硅晶穿孔连接块的其中之一连接至所述输入端子；以及
多个选择焊垫，位于所述下表面，其中所述多个选择焊垫的其中之一连接至所述输入端子，而所述多个选择焊垫的其余者分别连接至所述多个硅晶穿孔连接块的其余者；
多个倾斜焊垫，位于所述上表面且通过所述多个硅晶穿孔连接块分别连接至所述多个选择焊垫，其中每个所述倾斜焊垫具有焊垫表面，其不平行于所述上表面；以及
多个倾斜导电结构，分别位于对应的所述多个倾斜焊垫上，每个所述倾斜导电结构的底端接触对应的所述倾斜焊垫的所述焊垫表面，且每个所述倾斜导电结构的顶端垂直的对齐紧邻的所述倾斜焊垫。
2.如权利要求1所述的半导体晶片，其特征在于，每个所述倾斜导电结构包含：
柱状部，自每个所述倾斜焊垫的所述焊垫表面向上延伸；以及
锡球部，位于所述柱状部远离所述倾斜焊垫的一端，其中所述锡球部垂直的对齐紧邻的所述倾斜焊垫。
3.如权利要求2所述的半导体晶片，其特征在于，所述多个倾斜导电结构的所述柱状部均彼此相互平行。
4.如权利要求1所述的半导体晶片，其特征在于，所述上表面具有多个V型槽，且所述多个倾斜焊垫是分别共形的形成于所述多个V型槽上。
5.如权利要求4所述的半导体晶片，其特征在于，每个所述V型槽的两内表面夹角为90度。
6.如权利要求4所述的半导体晶片，其特征在于，所述半导体元件还包含保护层，多条导电通道于所述保护层内延伸，其中所述多个倾斜焊垫分别通过所述多条导电通道连接至所述多个硅晶穿孔连接块。
7.如权利要求4所述的半导体晶片，其特征在于，所述多个倾斜焊垫彼此间隔，且每个所述倾斜导电结构的顶端在垂直方向超出其底端连接的所述倾斜焊垫。
8.如权利要求2所述的半导体晶片，其特征在于，所述多个倾斜焊垫彼此间隔，且每个所述倾斜导电结构的所述锡球部在垂直方向超出所述倾斜导电结构的所述柱状部连接的所述倾斜焊垫。
9.一种多晶片半导体封装体，包含N个垂直堆叠的半导体晶片，其特征在于，每个所述半导体晶片包含：
半导体元件，具有上表面以及对应至所述上表面的下表面，其中所述半导体元件包含：
输入端子；
M个硅晶穿孔连接块，延伸穿越所述半导体元件，其中M≥N，且所述M个硅晶穿孔连接块的其中之一连接至所述输入端子；以及
多个选择焊垫，位于所述下表面，其中所述多个选择焊垫的其中之一连接至所述输入端子，而所述多个选择焊垫的其余者分别连接至所述多个硅晶穿孔连接块的其余者；
M-1个倾斜焊垫，位于所述上表面且通过所述多个硅晶穿孔连接块分别连接至所述多个选择焊垫，其中每个所述倾斜焊垫具有焊垫表面，其不平行于所述上表面；以及
多个倾斜导电结构，分别位于对应的所述多个倾斜焊垫上，每个所述倾斜导电结构的底端接触对应的所述倾斜焊垫的所述焊垫表面，且每个所述倾斜导电结构的顶端垂直的对齐紧邻的所述倾斜焊垫。
10.如权利要求9所述的多晶片半导体封装体，其特征在于，每个所述倾斜导电结构包含：
柱状部，自每个所述倾斜焊垫的所述焊垫表面向上延伸；以及
锡球部，位于所述柱状部远离所述倾斜焊垫的一端，其中所述锡球部垂直的对齐紧邻的所述倾斜焊垫。
11.如权利要求10所述的多晶片半导体封装体，其特征在于，所述多个倾斜导电结构的所述柱状部均彼此相互平行。
12.如权利要求9所述的多晶片半导体封装体，其特征在于，所述上表面具有多个V型槽，且所述多个倾斜焊垫是分别共形的形成于所述多个V型槽上。
13.如权利要求12所述的多晶片半导体封装体，其特征在于，每个所述V型槽的两内表面夹角为90度。
14.如权利要求12所述的多晶片半导体封装体，其特征在于，所述半导体元件还包含保护层，多条导电通道于所述保护层内延伸，其中所述多个倾斜焊垫分别通过所述多条导电通道连接至所述多个硅晶穿孔连接块。
15.如权利要求9所述的多晶片半导体封装体，其特征在于，所述N个半导体晶片是以其侧边对齐状况下垂直堆叠。
16.如权利要求9所述的多晶片半导体封装体，其特征在于，所述多个选择焊垫中最外侧的选择焊垫连接至所述输入端子。
17.如权利要求9所述的多晶片半导体封装体，其特征在于，还包含外接基材，所述外接基材包含多个电连接锡球，其分别连接至所述多个半导体晶片的最底者的所述多个选择焊垫。
18.如权利要求9所述的多晶片半导体封装体，其特征在于，所述多个倾斜焊垫彼此间隔，且每个所述倾斜导电结构的顶端在垂直方向超出其底端连接的所述倾斜焊垫。
19.如权利要求10所述的多晶片半导体封装体，其特征在于，所述多个倾斜焊垫彼此间隔，且每个所述倾斜导电结构的所述锡球部在垂直方向超出所述倾斜导电结构的所述柱状部连接的所述倾斜焊垫。
20.一种方法用以垂直堆叠多个如权利要求1所述的半导体晶片而形成多晶片半导体封装体，其特征在于，所述方法包含：
将所述多个半导体晶片以其侧边对齐状况下垂直堆叠，且每个所述倾斜导电结构的顶端接触紧邻的所述半导体晶片上对应的所述选择焊垫，其中对应的所述选择焊垫是垂直对齐每个所述倾斜导电结构的底端紧邻的所述倾斜焊垫。
CN201710888309.2A 2017-04-20 2017-09-27 多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法 Active CN108735684B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/493,096 US9893037B1 (en) 2017-04-20 2017-04-20 Multi-chip semiconductor package, vertically-stacked devices and manufacturing thereof
US15/493,096 2017-04-20

Publications (2)

Publication Number Publication Date
CN108735684A CN108735684A (zh) 2018-11-02
CN108735684B true CN108735684B (zh) 2020-04-10

Family

ID=61148033

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710888309.2A Active CN108735684B (zh) 2017-04-20 2017-09-27 多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法

Country Status (3)

Country Link
US (1) US9893037B1 (zh)
CN (1) CN108735684B (zh)
TW (1) TWI652782B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11201701725QA (en) * 2014-09-17 2017-04-27 Toshiba Kk Semiconductor device
US10879157B2 (en) * 2018-11-16 2020-12-29 Xilinx, Inc. High density substrate and stacked silicon package assembly having the same
KR20220000294A (ko) 2020-06-25 2022-01-03 삼성전자주식회사 반도체 패키지

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5995379A (en) * 1997-10-30 1999-11-30 Nec Corporation Stacked module and substrate therefore
US6169325B1 (en) * 1997-12-17 2001-01-02 Hitachi, Ltd. Semiconductor device
US6222278B1 (en) * 1996-12-12 2001-04-24 Hitachi, Ltd. Input-output circuit cell and semiconductor integrated circuit apparatus
US6448661B1 (en) * 2001-02-09 2002-09-10 Samsung Electornics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
CN103155143A (zh) * 2011-05-18 2013-06-12 晟碟半导体（上海）有限公司 瀑布引线键合

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9831155B2 (en) * 2016-03-11 2017-11-28 Nanya Technology Corporation Chip package having tilted through silicon via

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222278B1 (en) * 1996-12-12 2001-04-24 Hitachi, Ltd. Input-output circuit cell and semiconductor integrated circuit apparatus
US5995379A (en) * 1997-10-30 1999-11-30 Nec Corporation Stacked module and substrate therefore
US6169325B1 (en) * 1997-12-17 2001-01-02 Hitachi, Ltd. Semiconductor device
US6448661B1 (en) * 2001-02-09 2002-09-10 Samsung Electornics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
CN103155143A (zh) * 2011-05-18 2013-06-12 晟碟半导体（上海）有限公司 瀑布引线键合

Also Published As

Publication number Publication date
US9893037B1 (en) 2018-02-13
CN108735684A (zh) 2018-11-02
TW201839938A (zh) 2018-11-01
TWI652782B (zh) 2019-03-01

Similar Documents

Publication Publication Date Title
TWI649849B (zh) 具有高佈線密度補片的半導體封裝
US10784178B2 (en) Wafer-level stack chip package and method of manufacturing the same
US8110910B2 (en) Stack package
US7847379B2 (en) Lightweight and compact through-silicon via stack package with excellent electrical connections and method for manufacturing the same
US8592952B2 (en) Semiconductor chip and semiconductor package with stack chip structure
US9972606B2 (en) Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
CN108735684B (zh) 多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法
TW202133282A (zh) 半導體封裝
KR100914987B1 (ko) 몰드 재형상 웨이퍼 및 이를 이용한 스택 패키지
KR100959606B1 (ko) 스택 패키지 및 그의 제조 방법
KR101013556B1 (ko) 스택 패키지의 제조방법
KR101037827B1 (ko) 반도체 패키지
CN117594566A (zh) 半导体封装件
CN110634848A (zh) 一种多芯片堆叠封装结构及其制作方法
KR101013548B1 (ko) 스택 패키지
KR20230041250A (ko) 반도체 소자 및 이를 포함하는 반도체 패키지
KR20100050976A (ko) 반도체 패키지 및 그의 제조 방법
CN112397497A (zh) 半导体封装件
EP4369392A1 (en) Semiconductor package
US20240153886A1 (en) Semiconductor package
KR102502239B1 (ko) 반도체 칩, 인쇄 회로 기판, 이들을 포함하는 멀티 칩 패키지 및 멀티 칩 패키지의 제조방법
US9966364B2 (en) Semiconductor package and method for fabricating the same
CN112490129A (zh) 半导体封装及其制造方法
TW202420527A (zh) 半導體封裝
CN104733407A (zh) 半导体装置及其制法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant