TWI649849B - 具有高佈線密度補片的半導體封裝 - Google Patents

具有高佈線密度補片的半導體封裝 Download PDF

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Publication number
TWI649849B
TWI649849B TW105111577A TW105111577A TWI649849B TW I649849 B TWI649849 B TW I649849B TW 105111577 A TW105111577 A TW 105111577A TW 105111577 A TW105111577 A TW 105111577A TW I649849 B TWI649849 B TW I649849B
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patch
substrate
wiring density
semiconductor die
wiring
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TW105111577A
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TW201701432A (zh
Inventor
麥克 凱利
羅德 派翠克 胡默艾樂
大衛 喬 錫納樂
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美商艾馬克科技公司
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Abstract

用於一種具有高佈線密度的佈線補片的半導體封裝之方法及系統係被揭示，並且其可包含一被接合到一基板的半導體晶粒、以及一被接合至該基板以及該半導體晶粒的高佈線密度的補片，其中該高佈線密度的補片係包括一比該基板更稠密的線路密度。該高佈線密度的補片可以是一無矽的整合的模組(SLIM)補片，其係包括一BEOL部分，並且可以是無TSV的。金屬接點可被形成在該基板的一第二表面上。一第二半導體晶粒可被接合至該基板以及該高佈線密度的補片。該高佈線密度的補片可以提供在該些半導體晶粒之間的電互連。該基板可被接合到一矽中介體。該高佈線密度的補片可以具有一10微米或更小的厚度。該基板可以具有一10微米或更小的厚度。

Description

具有高佈線密度補片的半導體封裝
本揭露內容的某些實施例係有關於半導體晶片封裝。更明確地說，本揭露內容的某些實施例係有關於一種用於一具有一高佈線密度的補片(patch)的半導體封裝之方法及系統，其可包括一無矽的整合的模組(SLIM)。
半導體封裝係保護積體電路或晶片免於物理性損壞以及外部的應力。此外，其可以提供一導熱路徑以有效率地移除在一晶片中所產生的熱，並且例如亦提供電連接至其它像是印刷電路板的構件。用於半導體封裝的材料通常包括陶瓷或是塑膠，並且形狀因素尤其是已經從陶瓷扁平封裝及雙列直插式封裝，進步到針柵陣列及無引線晶片載體的封裝。
習知及傳統的方式的進一步限制及缺點對於具有此項技術的技能者而言，透過此種系統與如同在本申請案的其餘部分中參考圖式所闡述的本揭露內容的比較將會變成是明顯的。
本揭露內容的某些特點可見於一種具有高佈線密度的補片之半導體封裝中，其可包括一無矽的整合的模組(SLIM)以增加佈線密度。本揭露內容的範例特點係包含一種電子裝置，其係包括一被接合到一基板的 一第一表面的半導體晶粒、以及一被接合至該基板的高佈線密度的補片，其中該高佈線密度的補片係包括一比該第一基板更稠密的線路密度。在某些例子中，該高佈線密度的補片的佈線密度可以是在次微米的範圍內。該電子裝置亦可包括一種封入該半導體晶粒的至少一部分的密封劑(encapsulant)、該高佈線密度的補片、以及利用一密封劑而被封入的該基板的該第一表面、以及在該基板的一第二表面上的金屬接點。一第二半導體晶粒可被接合至該基板的該第一表面以及該高佈線密度的補片。該高佈線密度的補片可以提供在該半導體晶粒與該第二半導體晶粒之間的電互連。該基板可以是在一可包括矽的中介體上。該高佈線密度的補片可以具有一10微米或更小的厚度。該些金屬接點可包括焊料球。該基板可以具有一10微米或更小的厚度。
100‧‧‧封裝
101A、101B‧‧‧半導體晶粒
103‧‧‧高佈線密度的補片
105‧‧‧基板
106‧‧‧金屬層
107‧‧‧底膠填充材料
108‧‧‧介電層
109‧‧‧金屬接點
111‧‧‧接點結構
113‧‧‧凸塊下金屬(UBM)
115‧‧‧密封劑
116‧‧‧金屬層
118‧‧‧介電層
201‧‧‧晶圓(基板)
203‧‧‧基板
300‧‧‧半導體封裝
301A、301B‧‧‧半導體晶粒
303‧‧‧補片
305‧‧‧基板
306‧‧‧金屬層
307‧‧‧底膠填充材料
308‧‧‧介電層
309‧‧‧金屬接點
311‧‧‧接點結構
313‧‧‧凸塊下金屬(UBM)
315‧‧‧底膠填充材料
317‧‧‧補片接點
500‧‧‧半導體封裝
501A、501B‧‧‧半導體晶粒
503‧‧‧補片
505‧‧‧基板
506‧‧‧金屬層
507‧‧‧底膠填充材料
508‧‧‧介電層
509‧‧‧金屬接點
510‧‧‧中介體
512‧‧‧貫孔(TSV)
圖1是描繪根據本揭露內容的一範例實施例的一種具有被接合到一高佈線密度的補片的頂端晶粒之半導體封裝。
圖2A-2D係描繪根據本揭露內容的一範例實施例的在形成具有被接合到一高佈線密度的補片的頂端晶粒之半導體封裝中的範例步驟。
圖3是描繪根據本揭露內容的一範例實施例的一種具有被安裝高佈線密度的補片的背面之半導體封裝。
圖4A-4D係描繪根據本揭露內容的一範例實施例的用於形成一種具有被安裝高佈線密度的補片的背面之半導體封裝的範例步驟。
圖5是描繪根據本揭露內容的一範例實施例的一種具有在一中介體上 的一高佈線密度的補片之半導體封裝。
圖6A-6C係描繪根據本揭露內容的一範例實施例的在形成一種具有在一中介體上的一高佈線密度的補片之半導體封裝中的範例步驟。
本揭露內容的某些特點可見於一種具有高佈線密度的補片之半導體封裝中，其可包括一無矽的整合的模組(SLIM)以增加佈線密度。本揭露內容的範例特點係包含一種電子裝置，其係包括一被接合到一基板的一第一表面的半導體晶粒、以及一被接合至該基板的高佈線密度的補片，其中該高佈線密度的補片係包括一比該第一基板更稠密的線路密度。在某些例子中，該高佈線密度的補片的佈線密度可以是在次微米的範圍內。該電子裝置亦可包括一種封入該半導體晶粒的至少一部分的密封劑(encapsulant)、該高佈線密度的補片、以及利用一密封劑而被封入的該基板的該第一表面、以及在該基板的一第二表面上的金屬接點。一第二半導體晶粒可被接合至該基板的該第一表面以及該高佈線密度的補片。該高佈線密度的補片可以提供在該半導體晶粒與該第二半導體晶粒之間的電互連。該基板可以是在一可包括矽的中介體上。該高佈線密度的補片可以具有一10微米或更小的厚度。該些金屬接點可包括焊料球。該基板可以具有一10微米或更小的厚度。
圖1是描繪根據本揭露內容的一範例實施例的一種具有被接合到一高佈線密度的補片的頂端晶粒之半導體封裝。參照圖1，其係展示有一種封裝100，其係包括半導體晶粒101A及101B、高佈線密度的補片103、基板105、底膠填充材料107、金屬接點109、接點結構111、凸塊下 金屬(UBM)113、以及密封劑115。如同在圖1中可見的，補片103可被設置在半導體晶粒101A/B的一表面與基板105的一表面之間，但是補片103並不需要覆蓋半導體晶粒101A/B的此種表面的全部，並且可以延伸超出半導體晶粒101A/B的此種表面的一周邊。
該些晶粒101A及101B分別可以包括從一半導體晶圓分開的一積體電路晶粒，並且例如可包括像是數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器、以及特殊應用積體電路的電路。
該補片103例如可以包括一薄的高佈線密度的補片，其可以在該些半導體晶粒101A/101B之間、及/或在該些晶粒101A/101B與該基板105之間提供高密度的互連。在本例子中，補片103可包括一無矽的整合的模組(SLIM)補片，使得在其分層式結構中實質沒有矽或是其它半導體、且/或沒有穿過其的直通半導體通孔(TSV)。在某些SLIM實施例中，補片103可被產生為具有兩個部分。該SLIM補片的一後段製程(BEOL)部分(例如見於在圖1中的插圖的部分"a")可被製造成包括半導體製造類型的BEOL互連層，其可包括例如是SiN、SiO2或氮氧化物的無機介電材料，且/或可以是沒有有機介電材料的。該SLIM補片的一RDL部分(例如見於在圖1中的插圖的部分"b")可被形成以包括一被形成在該BEOL部分上的後製造的重分佈層(RDL)，並且可以具有例如是聚醯亞胺及/或PBO的有機介電材料。在某些例子中，該BEOL部分的厚度可以是大於該SLIM補片的RDL部分的厚度。在相同或是其它的例子中，該SLIM補片的BEOL部分可包括比該SLIM補片的RDL部分更大數量的導電層。作為一非限制性的例子，在某些實施方 式中，無機BEOL可以產生比那些經由具有有機介電質的RDL所產生者更多的平面層，使得該補片的BEOL部分可以具有3個或是更多個導電層，而該RDL部分由於平面性的考量而可能需要被限制為3個或是較少的導電層。儘管有以上的內容，但仍可能有其中該BEOL部分可包括小於3個導電層的例子。在相同或是其它的例子中，在該SLIM補片的BEOL部分中的導電層之間的分隔及/或介電質可以是比在該SLIM補片的RDL部分中的薄。然而，可以有其中該SLIM補片可包括該BEOL部分，而無該RDL部分的例子。亦可以有其中補片103不需要是一SLIM補片，但仍然包括比基板105更高佈線密度的例子。
在該補片103中的導電層例如可包括銅、鎳、及/或金。該SLIM結構可以是實質沒有例如是具有一矽或玻璃中介體的半導體材料，因為相較於該SLIM結構的介電質/金屬結構，矽及玻璃是更加有損失的。再者，SLIM結構可以是比矽或玻璃中介體薄的，且/或可以在其導電線路上提供更細的間距。
例如，該補片103可以是5-10μm厚的(或例如是<5μm厚的)，並且可包括具有高佈線密度的列及/或行的互連線，例如是0.5-1.0μm的線及/或在線之間的線間隔(或例如是<0.5μm的線或線間隔)、及/或30μm的用於行的間距(或例如是<30μm的間距)，但是本揭露內容並非限於此的，因為根據所要的互連密度，較大或是較小的線路或線間隔尺寸/間距都可被利用。該補片103可包括一或多個金屬層106以及介電層108(例如見於圖2A)，以提供隔離的高密度的電互連給耦接至該補片103的裝置及結構。
該基板105可包括一具有一種介電質/金屬分層式結構的基 板，但是可能有較低的佈線密度，此係致能一種比補片103的較高成本的高佈線密度的互連更低成本的結構。基板105可包括一或多個金屬層116以及介電層118(例如見於圖2A)，以提供隔離的電互連給耦接至該基板的裝置及結構。在某些例子中，基板105可以是一類似於如上所述的補片103的SLIM版本之SLIM，但是可包括比補片103更低的佈線密度。
該底膠填充材料107可被利用以填入在該些晶粒101A/101B之間、及/或在該些晶粒101A/101B與該基板105之間、及/或在該些晶粒101A/101B與該補片103之間的空間。底膠填充材料107可以提供機械式支撐給在該些晶粒101A/101B與該基板105之間、以及在該些晶粒101A/101B與該補片103之間的接合，並且提供該些金屬接點109保護。該底膠填充材料的高度例如可以是10-25μm的數量級。該底膠填充材料107可包括一預先施加的底膠填充、或是一在該晶粒101A/101B至該基板105的接合之後所施加的毛細管底膠填充。在一範例情節中，該底膠填充材料107可包括一種非導電膏。
該密封劑115例如可包括一環氧樹脂材料或是模製化合物，其可以保護該晶粒、補片103以及基板103與外部的環境隔開，並且提供物理強度給該封裝100。應注意到的是，該密封劑是一選配的結構，並且例如可以在該基板105提供足夠的物理強度給該封裝100時被排除。
該些金屬接點109例如可包括各種類型的用於將一晶粒接合至一基板的金屬(或導電的)互連，例如是微凸塊、金屬柱、焊料凸塊、焊料球。在一範例情節中，該些金屬接點109係包括具有一用於回焊及接合至該基板105上的接觸墊的焊料凸塊(或蓋)之銅柱。在相同或是其它的例子 中，金屬接點109可包括一約20-50μm的細微的間距、及/或一約90-100μm的粗略的間距。
該些接點結構111例如可包括金屬柱、焊料凸塊、焊料球、微凸塊、或是焊盤(lands)。該些接點結構可以具有不同的尺寸範圍，例如100-200μm的凸塊、或是20-100μm的微凸塊/柱。在其中焊料凸塊係被使用的實例中，該些接點結構可包括一或多種焊料金屬，其係在一比其它金屬低的溫度下熔化，使得在熔化及後續的冷卻之後，該些接點結構111係在該半導體封裝100與一外部的電路板或其它封裝之間提供機械式及電性接合。該些接點結構111例如可包括一球格陣列(BGA)或是焊盤柵格陣列(LGA)。儘管焊料球係被描繪，但是該些接點111可包括各種類型的接點的任一種。
該UBM 113可包括被形成在該基板105上的薄的金屬層，以用於接收該些接點結構111。該UBM 113可包括單一或是多個層，其係包括例如是銅、鉻/鉻-銅合金/銅(Cr/Cr-Cu/Cu)、鈦-鎢合金/銅(Ti-W/Cu)、鋁/鎳/銅(Al/Ni/Cu)、或是其它適當的金屬的材料，以用於接觸到該基板105以及該些接點結構111。
用以將一整個系統單晶片(SOC)設計到例如是10nm的CMOS(亦即，10nm閘極長度的CMOS製程)之更細微的CMOS技術節點中的成本可能是令人卻步的。晶粒尺寸並未快速地縮小，這是因為在該晶粒中的某些構件在次一技術節點下，並未在x-y尺寸上縮小。用於L0或L1快取的SRAM是晶粒尺寸並未隨著閘極尺寸而縮小的一個例子。最終結果是該10nm節點的10nm缺陷密度可能會由於製造複雜度而高出許多的，並 且可能會加倍每個晶圓的14/15nm CMOS的成本，同時所產生的晶粒尺寸即使有縮減的話，也未被縮減多少。
為了這些原因，該10nm的矽CMOS節點可以有利地被利用於那些在效能上的回報(來自較快的電晶體)是所需的商品(例如，CPU核心、GPU核心、等等)，並且該晶粒的其它功能可以用一例如是28nm或14nm的較舊的節點來充分地加以製造。此係表示將過去一直是單一晶粒的SOC拆開成為一種多晶粒的解決方案，其中該些個別的晶粒的功能係在IC封裝層級下加以重新整合。此係稱為"晶粒分化(split)"或是"晶粒解構(deconstruction)"。各種用於此種設計的平台可能會利用到一種直通半導體通孔(TSV)或是直通玻璃通孔(TGV)中介體的方法。然而，此種中介體可能是相當昂貴而且厚的(至少50-200μm)，因而為了容許有較低的成本以及較小的裝置，尤其是用於例如在行動市場中的較小封裝，本揭露內容的高佈線密度的補片及/或基板可被利用。
應注意到的是，該SLIM補片/基板不只是可應用於10nm或是低於10nm的技術節點。於是，該SLIM補片/基板可被用在其中高密度的互連是所要的任何應用中，特別是在一個其中一補片可以是最有空間且符合成本效益的小區域中。例如，SLIM補片/基板可被使用於14nm的技術。
在一晶粒分化中，如同在圖1的插圖中所繪的，所需的信號佈線密度可能是非常需要該兩個晶粒的彼此緊鄰的區域。儘管可以有較大的晶粒數量，但是兩個晶粒係在此單純為了舉例說明的目的而被展示。SLIM的成本例如可以是由所需的1)層計數、以及2)線厚度及間隔所驅使的。例如，若整個SLIM結構可以利用1層的2μm線以及2μm間隔而被佈線，則 此將會是相當經濟的。然而，如同在圖1的插圖可見的，在該晶粒之間或是在其它區域中的佈線需求可能是更費力的、需要更多層及/或較高的行、線或是線間隔的密度，此係顯著地增加成本。若在該SLIM基板上即使有一個具有0.5/0.5μm(例如)的線及/或線間隔的小的位置，則整個基板的成本將會是在佈線的額外費用。如同在圖2A中所示，該基板105在BEOL處理期間例如可以是被形成在可包括矽的晶圓201上的SLIM，並且該晶圓201接著係被移除，以得到完成的封裝100。在另一範例情節中，晶圓201的一薄層的矽可以留在基板105上。
在一範例情節中，若一需要較高佈線密度的區域(亦即，在圖1的插圖中所展示的區域)可以利用一例如是補片103的高佈線密度的補片來加以互連，則整體封裝成本可以是較低的，因為該區域的不需要此種高佈線密度的剩餘的部分可以利用例如是由基板105所提供的較低的成本的較低的密度佈線來適當地滿足需要。由這些較小的高佈線密度的補片所構成的一個晶圓將會產出大量的單元，並且因此每一個高佈線密度的補片的價格將會是較小的。跨越兩個晶粒的x-y維度的非高佈線密度的基板(例如，基板105)可以具有比該高佈線密度的補片的線及/或線間隔密度較粗略的線及/或線間隔密度(例如，2μm/2μm或是更大的線及線間隔)。
圖2A-2D係描繪根據本揭露內容的一範例實施例的在形成具有被接合到一高佈線密度的補片的頂端晶粒之半導體封裝中的範例步驟。圖2A-2D可以共用圖1的任一個以及所有的特點。參照圖2A，其係展示有該補片103以及該基板105。該補片103可以利用在該補片103以及基板105上的對應的金屬接點而被接合至該基板105。然而，在某些例子中， 補片103可以經由一黏著劑而被接合到基板105，且/或不需要直接電性耦接至基板105，其在此種情形中是只欲提供在半導體晶粒101A及101B之間的互連。
在一範例情節中，該基板105以及補片103分別可被形成在像是基板201及203的較厚的支撐結構上、或是藉由其來加以支承，該些支撐結構例如可以是具有晶圓或是晶粒的形式。在一範例情節中，該基板201可包括一矽或是玻璃晶圓，並且該基板203可包括一個經切割的晶圓之矽或是玻璃晶粒。或者是，該些基板201及203都可以是具有晶圓形式。
該補片103可以利用各種的接合技術(例如，黏著劑、熱導電的接合、相對高溫的回焊、等等)而被接合至該基板105。在其中該補片103在傳輸及接合至該基板105時包含用於實體支撐的基板203的實例中，該基板203可以在接合之前或是之後實質或完全地加以移除。
參照圖2B，該晶粒101A/101B可被接合到該補片103以及該基板105兩者。在一範例情節中，一回焊製程可被利用以將該些金屬接點109接合至該補片103以及基板105。該些金屬接點109例如可包括具有焊料凸塊的金屬柱，其中該些柱可以根據它們是被接合至該補片103或是該基板105而具有不同的高度。在一範例情節中，該些柱例如可包括不同的橫截面的形狀、寬度、及/或間距。
圖2C係描繪底膠填充材料107至圖2B的結構的施加，其例如可以在一毛細管底膠填充製程中被施加，儘管該底膠填充材料107可以替代地在接合該晶粒101A/101B之前預先被施加。此外，圖2C係描繪該UBM 113被施加至該基板105的底表面。一鈍化層可被施加至該基板105 的背面，其具有用於該UBM 113的後續的形成之開口。於是，該基板105可以在頂表面以及底表面上包括金屬接點、以及用於隔離及保護來與環境的污染物隔開的鈍化層。
該半導體晶粒101A及101B以及該底膠填充107可以為了環境的保護及/或該封裝的物理強度，藉由該密封劑115來加以封入。該密封劑115是一選配的結構，並且例如在該基板105提供足夠的物理強度給該封裝100時可被排除。在該密封劑115被利用的實例中，該基板201例如可以藉由蝕刻或是化學機械拋光來加以移除。
最後，在圖2D中，該些接點結構111可被設置在該UBM 113上，此係產生最終的結構，亦即該半導體封裝100。該些接點結構111例如可包括焊料球，以用於接合至一外部的印刷電路板或是其它裝置。然而，注意到的是各種接點結構的任一種都可被利用。
圖3是描繪根據本揭露內容的一範例實施例的一種具有被安裝高佈線密度的補片的背面之半導體封裝。圖3可以共用圖1-2的對應的特點的任一個以及全部。參照圖3，其係展示有半導體封裝300，該半導體封裝300係包括半導體晶粒301A及301B、補片303、基板305、底膠填充材料307、金屬接點309、接點結構311、UBM 313、底膠填充材料315、以及補片接點317。
在此例子中，可包括一類似於補片103的高佈線密度的補片之補片303可被接合至該基板305的底表面，該基板305可以是類似於基板105。由於該補片303的厚度可以是5μm厚、或甚至是更小的數量級、並且在面積上是每一側邊幾毫米，因此其並不妨礙該半導體封裝300的BGA接 合的使用、或是各種具有一大於5μm的間隔的不同的接點結構的任一種的利用。類似地，該基板305可包括一SLIM基板，但是具有相較於該補片303的較低的佈線密度。
該底膠填充材料315可被利用以填入在該補片303與該基板305之間的空間，並且可以提供機械式支撐給在該些結構之間的接合，並且提供保護給該些補片接點317。該底膠填充材料315例如可以包括一預先施加的底膠填充、或是在該補片303至該基板305的接合之後被施加的一毛細管底膠填充。在一範例情節中，該底膠填充材料313可包括一種非導電膏。
該些補片接點317可包括各種類型的用於接合該補片303至該基板305的金屬互連，例如是微凸塊、金屬柱、焊料凸塊、焊料球、等等。
圖4A-4D係描繪根據本揭露內容的一範例實施例的用於製造一種具有被安裝高密度的補片的背面之半導體封裝的範例步驟。圖4A-4D可以共用圖1-3的對應的特點的任一個以及全部。參照圖4A，該晶粒301A/301B可以利用該些金屬接點309而被接合至該基板305。該基板305可包括一具有5-10μm的數量級厚的介電質/金屬分層式結構之SLIM基板，並且可包括在該金屬層306中的接觸墊以用於接收該些金屬接點309、以及用於隔離在該基板305中的金屬互連線的介電層308。
該些金屬接點309可包括各種類型的用於將一晶粒接合至一基板的金屬互連，例如是金屬柱、焊料球、微凸塊、等等。在一範例情節中，該些金屬接點309係包括具有一用於回焊製程的焊料凸塊(或是蓋)的銅柱，以將該些金屬接點309接合至在該基板305上的金屬層306中的接觸 墊。
在圖4B中，底膠填充材料307例如可以在一毛細管底膠填充製程中被施加。在另一範例情節中，該底膠填充材料307可以是一預先施加的底膠填充材料，其係有助於將該些金屬接點309接合至該基板305。
圖4B亦展示該UBM 313在該基板305的底表面上的形成，以用於接收接點結構311。於是，該基板305可包括在該金屬層308中的用於接收該UBM 313的接觸墊、以及在頂表面及底表面上的用於電性隔離及保護來與環境的污染物隔開的鈍化層。
在圖4C中，該補片303可以利用在該基板305上的金屬層306中的金屬接點(未顯示)以及在該補片303上的類似的層，而被接合至該基板305的底表面。一種底膠填充材料315可以預先被施加在該基板305上、或是可以在接合之後，在一毛細管底膠填充製程中被施加在該基板305與該補片303之間。該底膠填充材料315可以有助於該補片303至該基板305的接合製程。
最後，該些接點結構311可被形成在該UBM 313上，此係產生最終的結構，亦即該半導體封裝300。一回焊製程例如可被利用以將該些可包括焊料球的接點結構311附著至該UBM 313。如同在此所解說的，相關圖4所展示及論述的方法及結構可以與在此論述的其它方法及結構共用任一個或是所有的特徵。例如，在一範例的實施方式中，補片可以被耦接至該基板的兩側面。此外，晶粒亦可被接合到該基板的兩側面。
圖5係描繪根據本揭露內容的一範例實施例的一種具有在一中介體上的一高密度的補片之半導體封裝。參照圖5，其係展示有半導體 封裝500，該半導體封裝500係包括半導體晶粒501A及501B、補片503、基板505、底膠填充材料507、金屬接點509、以及中介體510。圖5可以共用圖1-4的對應的特點的任一個以及全部。例如，補片503可以是類似於補片103，且/或基板505可以是類似於基板105。
在此例子中，可包括一高佈線密度的補片之補片503可被接合到中介體510的頂表面。在圖5中的結構的厚度並未按照比例。例如，中介體一般是遠厚於該SLIM結構、補片503以及基板505，其例如是50-200μm的數量級。此外，藉由將在該補片中的高佈線密度的互連納入一標準的中介體結構，成本可以大為降低，因為藉由納入該補片503，因此在該中介體510中的薄膜佈線的層計數可被降低。
圖6A-6C係描繪根據本揭露內容的一範例實施例的在製造一種具有在一中介體上的一高佈線密度的補片之半導體封裝中的範例步驟。圖6A-6C可以共用圖1-5的特點的任一個以及全部。參照圖6A，其係展示有中介體510、補片503、以及基板505。該補片503及/或該基板505可包括SLIM結構，其係包括如上分別相關補片103以及基板105所述的金屬以及介電層。
該基板505在圖6A中係以橫截面來加以展示，並且可包括一在中心具有一開口的SLIM基板，其中該補片503(可包括一SLIM高密度的補片)可被接合至該中介體510。該基板505可包括一或多個金屬層506以及介電層508，並且在其分層式結構中可以實質不包括對於電性信號可能有較多損失的矽。
該中介體510(以及任何在此論述的中介體)例如可包括一具 有TSV的矽或玻璃中介體、或是一積層中介體，其係具有絕緣以及導電材料以用於提供在該晶粒501A/501B以及該中介體510經由該補片503或是該基板505所接合到的一結構之間的電性接觸。如同在圖6A中所示並且在圖6B中所示之產生的結構，在該基板505內的金屬層506中或是其之上的金屬接點可以電耦接至在該中介體510中的貫孔512。
圖6B係展示該晶粒501A/501B是利用該些金屬接點509而被接合至該補片503以及該基板505。該些金屬接點509可包括各種類型的用於將一晶粒接合至一基板的金屬互連，例如是金屬柱、焊料球、微凸塊、等等。在一範例情節中，該些金屬接點509係包括具有一用於回焊製程的焊料凸塊(或是蓋)的銅柱，以將該些金屬接點509接合至在該基板505上的金屬層506中的接觸墊。
在其中這些補片503或基板505的結構的厚度是不同的實例中，該些金屬接點509可以根據它們被接合至該補片503或是基板505而具有不同的高度。當該補片包括多個層以用於在該些晶粒501A及501B與其它耦接至該中介體510的結構之間的大量高佈線密度的互連線時，該補片503可以是比該基板505更厚的。或者是，該補片503可以是比該基板505更薄的(例如，此係產生比用於連接至該基板505更長的用於連接至該補片503的金屬接點509)、或是相同的厚度(例如，此係大致產生用於連接至該補片503以及該基板505之一致的接點長度)。
一種底膠填充材料507可被形成在該晶粒501A/501B與該基板505及補片503之間、以及在該些晶粒501A/501B之間。在一範例情節中，該底膠填充材料507可以在一毛細管底膠填充製程中加以形成。在一替代 的情節中，該底膠填充材料507可以是預先施加的底膠填充，並且有助於將該些金屬接點509接合至該基板510。所產生的結構係被展示在圖6C中。
該中介體510例如可包括一具有TSV 512的矽基板，以用於經由該些金屬接點509以及該補片/基板503/505來將該些晶粒501A及501B電耦接至一外部的印刷電路板或是其它外部的裝置。藉由納入一高佈線密度的補片(該補片503)以及該中介體510，成本可以大為降低，因為該補片503包含該些高密度的互連，使得在該中介體510中的薄膜佈線的層計數可被降低。
其它的變化係被思及。例如，基板105(圖1-2)及/或基板305(圖3-4)可以是一中介體、或者可被稱為一中介體，其可以是類似於在一些實施方式中的中介體510。再者，如同相關圖1-4所敘述的，不論是否具有一中介體，將一SLIM補片安裝至一基板，並且接著將該晶粒接合至SLIM+基板的整體組合是可能的。在某些情形中，數個SLIM補片可被接合到一基板，以容許多個晶粒能夠用此種方式來連接。例如，在圖5-6中的基板505可以是具有類似於補片503的補片形式，而不論是否具有SLIM形式及/或具有較低的佈線密度、且/或不論是否耦接至中介體510或是一非SLIM基板。作為另一例子的是，圖1-4可以固有地包括多個補片103及/或303的一組合，以允許在多個晶粒之間的進一步的互連接。
在本揭露內容的一實施例中，一種用於一具有一高佈線密度的補片的半導體封裝之方法及系統係被揭示，其可包括一無矽的整合的模組(SLIM)。就此點而言，本揭露內容的特點可包括將一半導體晶粒接合至一基板的一第一表面以及一被接合至該基板的高佈線密度的補片。該半導體 晶粒、該高佈線密度的補片、以及該基板可以利用一密封劑而被封入。
金屬接點可被形成在該基板的一第二表面上。一第二半導體晶粒可被接合至該基板的該第一表面以及該高佈線密度的補片。該高佈線密度的補片可以提供在該些半導體晶粒之間的電互連。該基板可被接合到一中介體。該高佈線密度的補片可以具有一10微米或更小的厚度。該些金屬接點可包括焊料球。該基板可以具有一10微米或更小的厚度。
該高佈線密度的補片的厚度的一部分可包括金屬及無機介電層的交替的層(BEOL結構)，並且該高佈線密度的補片的厚度的另一部分可包括金屬及有機介電層的交替的層。
在本揭露內容的一實施例中，一半導體晶粒可被接合到一基板的一第一表面、以及一被接合到該基板的一與該第一表面相對的第二表面之高佈線密度的補片，其中該基板以及該高佈線密度的補片並不包括半導體層。該半導體晶粒以及該基板的至少一部分可以利用一密封劑而被封入，並且金屬接點可以是在該基板的該第二表面上。
一第二半導體晶粒可被接合至該基板的該第一表面。該高佈線密度的補片可以提供在該半導體晶粒與該第二半導體晶粒之間的電互連。該高佈線密度的補片可以具有一10微米或更小的厚度。
在某些例子中，可以有其中基板105、305及/或505並不需要是一SLIM基板的實施例，而可以例如是具有貫孔的一積層中介體或是一矽/玻璃中介體，例如是相關中介體510所敘述者。
儘管本揭露內容已經參考某些實施例來加以敘述，但是熟習此項技術者將會理解到可以做成各種的改變，並且等同物可加以取代，而 不脫離本揭露內容的範疇。此外，可以做成許多修改以將一特定的情況或材料調適至本揭露內容的教示，而不脫離其範疇。因此，所欲的是本揭露內容並不受限於所揭露之特定的實施例，而是本揭露內容將會包含落入所附的申請專利範圍的範疇內之所有的實施例。

Claims (20)

  1. 一種用於半導體封裝之方法，該方法係包括：接收一高佈線密度的補片，其包括：一半導體材料；至少一導電層，其係在該半導體材料上；及至少一無機介電層，其係在該半導體材料上；從該高佈線密度的補片移除至少實質上所有的該半導體材料；將該高佈線密度的補片接合至一基板的一第一表面；以及將一半導體晶粒接合至該基板的該第一表面和該高佈線密度的補片；其中該高佈線密度的補片係包括一比該基板更稠密的線路密度，並且該高佈線密度的補片的該至少一無機介電層所具有的寬度係小於該基板的該第一表面的寬度。
  2. 根據申請專利範圍第1項之方法，其係包括將一第二半導體晶粒直接接合至該基板的該第一表面以及該高佈線密度的補片，其中該高佈線密度的補片係提供在該半導體晶粒與該第二半導體晶粒之間的電互連，並且該高佈線密度的補片在該補片的中心附近具有一高密度佈線的區域，並在該高密度佈線的區域之相反側具有低密度佈線的區域。
  3. 根據申請專利範圍第1項之方法，其中將該高佈線密度的補片接合至該基板的該第一表面係包括將該高佈線密度的補片直接接合至該基板的無機介電層，並且其中該高佈線密度的補片係在一晶圓製造製程的後段製程(BEOL)中形成的，且是無直通半導體通孔(TSV)的。
  4. 一種電子裝置，其係包括：一基板；一高佈線密度的補片，其係被接合至該基板的一第一表面，其中該高佈線密度的補片係包括一介電層，該介電層具有的寬度係小於該基板的該第一表面的寬度；一半導體晶粒，其係被接合至該基板的該第一表面以及該高佈線密度的補片，其中該高佈線密度的補片包括一比該基板更稠密的線路密度，其中該高佈線密度的補片包括一半導體晶圓的經切割和薄化部分，其係在一晶圓製造製程的後段製程(BEOL)中形成的。
  5. 根據申請專利範圍第4項之裝置，其係包括一第二半導體晶粒，該第二半導體晶粒係被直接接合至該基板的該第一表面並且係被直接接合至該高佈線密度的補片。
  6. 根據申請專利範圍第5項之裝置，其中該高佈線密度的補片係提供在該半導體晶粒與該基板之間的電互連。
  7. 根據申請專利範圍第4項之裝置，其係包括定位在該基板的該第一表面上之一中介體，其係與該高佈線密度的補片不同且與該基板不同。
  8. 根據申請專利範圍第4項之裝置，其中該半導體晶粒係利用具有第一高度的第一銅柱而接合至該基板的該第一表面，並且利用具有第二高度的第二銅柱而接合至該高佈線密度的補片，該第二高度小於該第一高度。
  9. 根據申請專利範圍第4項之裝置，其中該高佈線密度的補片在厚度上係10微米或更小。
  10. 根據申請專利範圍第4項之裝置，其中該高佈線密度的補片係包括在一約1μm或更小的間隔下的線路，並且該基板並不包括在一小於1μm的間隔下的線路。
  11. 根據申請專利範圍第4項之裝置，其中該基板在厚度上係10微米或更小。
  12. 根據申請專利範圍第4項之裝置，其包括：一底膠填充材料，其係直接填充於該半導體晶粒的第一部分下方，但不是直接填充於該半導體晶粒的第二部分下方，該半導體晶粒的第一部分係直接位於該高佈線密度的補片上方，該半導體晶粒的第二部分並非直接位於該高佈線密度的補片上方；以及一密封劑材料，其係封入該半導體晶粒的至少一部分、該高佈線密度的補片、該基板的該第一表面、和該底膠填充材料。
  13. 根據申請專利範圍第4項之裝置，其中：該半導體晶粒係利用具有第一高度的第一導電柱並且利用與該第一導電柱不同的第一焊料而直接接合至該基板；該半導體晶粒係利用具有第二高度的第二導電柱並且利用第二焊料而直接接合至該高佈線密度的補片，該第二高度比該第一高度還低；並且該第一導電柱在垂直方向上比該第一焊料長。
  14. 根據申請專利範圍第4項之裝置，其中該高佈線密度的補片係直接接合至該基板的無機介電層，並且不包括直通半導體通孔。
  15. 根據申請專利範圍第4項之裝置，其中該高佈線密度的補片包括矽。
  16. 根據申請專利範圍第4項之裝置，其中：該高佈線密度的補片包括一無機介電層；該基板包括一有機介電層；以及該補片的該無機介電層係接合至該基板的該有機介電層而沒有一居間的黏著層。
  17. 一種電子裝置，其包括：一基板；一高佈線密度的補片，其係被接合至該基板的一第一表面，其中該高佈線密度的補片包括一導電層和一介電層；一第一半導體晶粒，其係被直接接合至該基板的該第一表面和該高佈線密度的補片；一第二半導體晶粒，其係被直接接合至該基板的該第一表面和該高佈線密度的補片；其中：該高佈線密度的補片的該介電層所具有的寬度小於該基板的該第一表面的寬度；該高佈線密度的補片包括一比該基板更稠密的線路密度，該高佈線密度的補片係提供在該第一半導體晶粒和該第二半導體晶粒之間的電互連，其係與該基板獨立；並且該高佈線密度的補片係提供在該第一半導體晶粒和該基板之間的電互連。
  18. 根據申請專利範圍第17項之裝置，其中該高佈線密度的補片係直接接合至該基板的無機介電層，並且不包括直通半導體通孔。
  19. 根據申請專利範圍第17項之裝置，其中該高佈線密度的補片在該補片的中心附近具有一高密度佈線的區域，並在該高密度佈線的區域之相反側具有低密度佈線的區域。
  20. 根據申請專利範圍第17項之裝置，其中：該第一半導體晶粒係利用具有第一高度的第一導電柱並且利用與該第一導電柱不同的第一焊料而直接接合至該基板；該第一半導體晶粒係利用具有第二高度的第二導電柱並且利用與該第二導電柱不同的第二焊料而直接接合至該高佈線密度的補片，該第二高度比該第一高度還低；並且該第一導電柱在垂直方向上比該第一焊料長。
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