WO2020147107A1 - 一种多中介层互联的集成电路 - Google Patents

一种多中介层互联的集成电路 Download PDF

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Publication number
WO2020147107A1
WO2020147107A1 PCT/CN2019/072323 CN2019072323W WO2020147107A1 WO 2020147107 A1 WO2020147107 A1 WO 2020147107A1 CN 2019072323 W CN2019072323 W CN 2019072323W WO 2020147107 A1 WO2020147107 A1 WO 2020147107A1
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Prior art keywords
integrated circuit
interconnection
die
interposer
substrate
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PCT/CN2019/072323
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English (en)
French (fr)
Inventor
陶军磊
赵南
张晓东
王晨
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华为技术有限公司
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Priority to CN201980065923.6A priority Critical patent/CN112889149B/zh
Priority to PCT/CN2019/072323 priority patent/WO2020147107A1/zh
Publication of WO2020147107A1 publication Critical patent/WO2020147107A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This application relates to the field of electronic technology, in particular to an integrated circuit with multiple interposer interconnections.
  • the 2.5D TSV silicon interposer technology is a technical solution for the interconnection of stacked chips in three-dimensional integrated circuits. This solution can integrate multiple different dies through the silicon interposer. Compared with the traditional single-die chip, the overall performance of the chip is greatly improved. However, due to the limitation of the size of the silicon interposer, the number of multiple dies integrated on a single silicon interposer still cannot meet the industry's continuous demand for integrating more dies.
  • the chip shown in Figure 1 contains a substrate on which there are two silicon interposers. Each silicon interposer is sealed with a system-on chip (SOC) and four high Bandwidth memory (High bandwidth Memory, HBM).
  • SOC system-on chip
  • HBM High bandwidth Memory
  • Fig. 1 shows a top view of the chip
  • Fig. 2 shows a cross-sectional side view of the chip
  • the BGA ball in Fig. 2 is a ball grid array (Ball Grid Array) ball.
  • the traces in the substrate still remain on the rough surface and the line width and line spacing (for example, 13um/13um) are large, and the interconnection density is low.
  • the traces in the silicon interposer can be super Ultra-high interconnection density with fine line width and line spacing (for example, 0.4um/0.4um). Therefore, interconnecting different silicon interposers through the substrate will make signal transmission need to pass through multiple paths and cross different impedances, which greatly affects the signal quality.
  • This application provides a multi-intermediate-layer interconnected integrated circuit, which is used to improve the signal quality transmitted when different silicon interposers are interconnected.
  • an integrated circuit with multiple interposer interconnections includes: a first semiconductor interposer, a second semiconductor interposer, a substrate, and a low-loss connector.
  • the first semiconductor interposer and the second semiconductor interposer And the low-loss connector are arranged on the same side of the substrate; wherein, the side of the first semiconductor interposer facing away from the substrate is provided with at least one first die, and the first semiconductor interposer is provided with a first interconnection circuit;
  • the side of the interposer facing away from the substrate is provided with at least one second die, and the second semiconductor interposer is provided with a second interconnection circuit; one of the at least one first die passes through the first interconnection circuit with low loss
  • the connector and the second interconnection circuit form an electrical connection with one of the at least one second die.
  • the low-loss connector is used to connect the first interconnection circuit of the first semiconductor interposer and the second interconnection circuit of the second semiconductor interposer, so that the transmission path between the dies on different semiconductor interposers Compared with the transmission path in the prior art, the signal transmission loss is smaller, thereby improving the signal quality in the integrated circuit.
  • the low-loss connector includes a base body and an interconnection layer disposed on one side of the base body, and at least one first die and at least one second die pass through the low-loss connector. Interconnection layer connection.
  • the interconnection layer of the first semiconductor interposer and the interconnection layer of the second semiconductor interposer are directly connected through a low-loss connector, so as to achieve interconnection between different dies.
  • the transmission path is specifically: bare chip-interconnection circuit of the first semiconductor interposer-interconnection layer of low loss connector-interconnection circuit of the second semiconductor interposer-bare chip, which can greatly reduce the signal compared with the prior art. The transmission path further improves the quality of the signal.
  • the trace width of the interconnection layer matches the trace width of the first interconnection circuit and the second interconnection circuit.
  • the impedance on the signal transmission path can be made continuous, thereby reducing signal transmission loss and improving signal quality.
  • the lowest line width/line pitch of the low-loss connector is equal to 0.4um/0.4um.
  • the minimum line width/line distance can reach 0.4um/0.4um, which is similar to the wiring in the prior art substrate.
  • the line width/line spacing of 13um/13um has been greatly improved, so that when more dies are integrated, the package size of the integrated circuit can be reduced, the thickness of the substrate in the integrated circuit can be reduced, and the design of the substrate can be simplified Pressure, thereby reducing the cost of the integrated circuit.
  • the matrix of the low-loss connector is a plastic sealing material; optionally, the structure of the low-loss connector is a mixed structure of an organic medium and a redistribution layer.
  • the above possible implementation manners can reduce the cost of the low-loss connector 304, and at the same time, the use of a mixed structure of an organic medium and a redistribution layer can improve the performance and reduce the size of the low-loss connector 304.
  • the base of the low-loss connector is a silicon base, or the base of the low-loss connector is a glass base.
  • the base of the low-loss connector is a silicon base, or the base of the low-loss connector is a glass base.
  • At least one first die is a plurality of first dies
  • at least one second die is a plurality of first dies
  • the first semiconductor interposer is further provided with a An interconnection circuit
  • the second semiconductor interposer is also provided with a second interconnection circuit
  • the first interconnection circuit is also used to form an electrical connection between each first die
  • the second interconnection circuit is also used to form each second die Electrical connection between the slices.
  • the at least one first die and the at least one second die both include an application specific integrated circuit ASIC and a high-bandwidth memory HBM.
  • ASIC application specific integrated circuit
  • HBM high-bandwidth memory
  • the first semiconductor interposer and the second semiconductor interposer are silicon interposers; or, the structures of the first semiconductor interposer and the second semiconductor interposers are organic medium and redistribution Layer mixed structure.
  • a terminal device in a second aspect, includes a printed circuit board PCB, and a multi-intermediate-layer interconnected integrated circuit as provided in the first aspect or any one of the possible implementation manners of the first aspect.
  • the integrated circuit is arranged on one side of the PCB and forms an electrical connection with the PCB.
  • FIG. 1 is a schematic diagram 1 of the structure of a chip provided by the prior art
  • FIG. 2 is a second schematic diagram of the structure of a chip provided in the prior art
  • FIG. 3 is a first structural diagram of an integrated circuit provided by an embodiment of this application.
  • FIG. 4 is a second structural diagram of an integrated circuit provided by an embodiment of this application.
  • FIG. 5 is a schematic structural diagram of a low-loss connector provided by an embodiment of the application.
  • FIG. 6 is a third structural diagram of an integrated circuit provided by an embodiment of this application.
  • FIG. 7 is a fourth structural diagram of an integrated circuit provided by an embodiment of this application.
  • FIG. 8 is a fifth structural schematic diagram of an integrated circuit provided by an embodiment of the application.
  • FIG. 9 is a sixth structural diagram of an integrated circuit provided by an embodiment of this application.
  • At least one (a) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c may be single or multiple.
  • words such as “first” and “second” do not limit the number and order.
  • the 2.5D TSV technology can improve the performance of the chip, such as enhancing the function of the chip and reducing the size of the chip.
  • the 2.5D TSV silicon interposer technology is a technical solution for the interconnection of stacked chips in three-dimensional integrated circuits. This solution can integrate multiple different dies through the silicon interposer. Compared with the traditional single-die chip, the overall performance of the chip is greatly improved.
  • This technical solution uses semiconductor technology to produce line widths and node pitches on silicon wafers that are much smaller than those made on resin substrates, so that chips with different functions (such as CPU, DRAM, etc.) can be connected to the same
  • chips with different functions such as CPU, DRAM, etc.
  • a silicon interposer a large number of calculations and data exchanges are completed through the silicon interposer, which greatly increases the stacking density of the chips in the three-dimensional direction, shortens the interconnection lines between the chips, reduces the appearance size, significantly reduces noise, and reduces RC delay , And improve chip speed and low power consumption performance.
  • an embodiment of the present application provides an integrated circuit for achieving the integration of more dies while ensuring signal quality.
  • FIG. 3 is a schematic structural diagram of an integrated circuit with multiple interposer interconnections provided by an embodiment of the application.
  • the integrated circuit includes: a first semiconductor interposer 301, a second semiconductor interposer 302, a substrate 303, and a low
  • the loss connector 304, the first semiconductor interposer 301, the second semiconductor interposer 302 and the low loss connector 304 are disposed on the same side of the substrate 303.
  • the side of the first semiconductor interposer 301 facing away from the substrate 303 is provided with at least one first die 305
  • the first semiconductor interposer 301 is provided with a first interconnect circuit 3011
  • the second semiconductor interposer 302 is facing away from the substrate 303
  • At least one second die 306 is provided on one side of the second semiconductor interposer 302, and a second interconnect circuit 3021 is provided in the second semiconductor interposer 302; one of the at least one first die 305 passes through the first interconnect circuit 3011
  • the low-loss connector 304 and the second interconnection circuit 3021 are electrically connected to one of the at least one second die 306.
  • the interconnection of multiple interposers may include the interconnection of two or more semiconductor interposers, and the low-loss connector 304 may connect every two adjacent semiconductor interposers or connect them.
  • a group of two adjacent semiconductor interposers The embodiment of the present application takes the first semiconductor interposer 301 and the second semiconductor interposer 302 as examples for description.
  • first semiconductor interposer 301 and the second semiconductor interposer 302 may be silicon interposers.
  • the silicon interposers may be interposers formed by alternating a layer of silicon and a layer of metal (such as copper).
  • the structure of the first semiconductor interposer 301 and the second semiconductor interposer 302 may be a structure in which an organic medium and a redistribution layer are mixed, for example, the structure is a PI/RDL structure, and PI may refer to polyimide (polyimide) , RDL may refer to a redistribution layer, where the PI/RDL structure may refer to a structure of an interposer formed by a layer of PI and a layer of metal (such as copper) alternately.
  • the PI/RDL structure is characterized by better performance and smaller size.
  • This article takes the silicon interposer as an example for description.
  • At least one first die 305 and at least one second die 306 both include application specific integrated circuits (ASIC) and high bandwidth memory (HBM). ) Is taken as an example for description, and FIG. 3 does not limit the embodiment of the present application. In practical applications, at least one first die 305 and at least one second die 306 may also include system-on-chip (SOC) and high-bandwidth memory HBM, or include other different dies, etc. The embodiment does not specifically limit this.
  • FIG. 3 is a side sectional view of the integrated circuit
  • FIG. 4 is a top view corresponding to FIG. 3
  • the BGA ball in FIG. 3 is a ball grid array (Ball Grid Array) ball.
  • the first interconnect circuit 3011 of the first semiconductor interposer 301 may specifically be the top metal of the first semiconductor interposer 301
  • the second interconnect circuit 3021 of the second semiconductor interposer 302 may specifically be the second semiconductor interposer 302 Top metal.
  • the low-loss connector 304 is used to connect the first interconnection circuit 3011 of the first semiconductor interposer 301 and the second interconnection circuit 3021 of the second semiconductor interposer 302, so that the nakedness on different semiconductor interposers Compared with the transmission path in the prior art, the transmission path between the chips has less signal transmission loss, thereby improving the quality of the signal in the integrated circuit.
  • At least one first die 305 is a plurality of first dies
  • at least one second die 306 is a plurality of second dies
  • the first semiconductor interposer 301 is also provided with a first interconnection circuit 3011.
  • the second semiconductor interposer 302 is also provided with a second interconnection circuit 3021.
  • the first interconnection circuit 3011 is also used to form an electrical connection between each first die
  • the second interconnection circuit 3021 is also used to form each first die. Electrical connection between the two dies.
  • the at least one first die 305 and the at least one second die 306 both include multiple dies, the industry's demand for integrating more dies can be met, and the signal transmission does not need to pass through multiple paths.
  • the signal transmission path can be: ASIC-first interconnection circuit 3011-low-loss connector 304-second interconnection circuit 3021-ASIC), which can improve the integration The signal quality of a bare chip integrated circuit.
  • the low-loss connector 304 includes a base and an interconnection layer disposed on one side of the base, and at least one first die 305 and at least one second die 306 pass through the low-loss connector 304. Interconnection layer connection.
  • the signal transmission path in the integrated circuit may be: ASIC-first interconnection circuit 3011-interconnection layer of low-loss connector 304-second interconnection circuit 3021-ASIC.
  • the base of the low-loss connector 304 may be a silicon base, a molding (molding) or a glass base, etc.;
  • the interconnection layer may be a metal layer, for example, the metal layer may be a copper layer, and the interconnection layer may also include interconnections. Bumps, the interconnecting bumps may specifically be connection points between the interconnection layer and the top metal of the silicon interposer.
  • the low-loss connector 304 may be obtained by growing an interconnection layer on a silicon substrate, or by growing an interconnection layer on a plastic package, or by growing an interconnection layer on a glass substrate; optionally, when When the interconnection layer further includes interconnection bumps, the interconnection bumps can continue to grow after the interconnection layer is grown. Wherein, after the interconnection layer is grown on a silicon substrate, a plastic package or a glass substrate, a larger size substrate can be obtained, and then the substrate can be cut into a single low loss connector 304 according to the size of the low loss connector 304.
  • Figure 5(a) shows a top view of the silicon substrate/plastic/glass substrate
  • Figure 5(b) shows a top view of the substrate after the interconnection layer is grown
  • Figure 5(c) shows a single The top view and side cutaway view of the low loss connector 304.
  • the structure of the low-loss connector 304 may be a PI/RDL structure
  • PI may refer to polyimide
  • RDL may refer to a redistribution layer
  • PI/RDL structure The connector has better performance and smaller size.
  • PI/RDL structure reference may be made to the related description in the prior art, which is not described in the embodiment of the present application.
  • first semiconductor interposer 301 and the second semiconductor interposer 302 may be fabricated through a 2.5D TSV process in which a silicon interposer is interposer OS first, and OS is an abbreviation for on substrate. Specifically, first connect the two silicon interposers to the substrate 303, as shown in FIG. 6, and then connect at least one first die 305, at least one second die 306, and low-loss connector 304 to the The two silicon interposers of the substrate 303 are connected (for example, at least one first die 305, at least one second die 306, and low-loss connector 304 are mounted on the two silicon interposers respectively), and the resulting integrated circuit can be See Figure 3.
  • the first semiconductor interposer 301 and the second semiconductor interposer 302 may be fabricated through a 2.5D TSV process of a silicon interposer (interposer OS last). Specifically, two silicon interposers connected to each other are obtained through a 2.5D TSV process, and each silicon interposer is provided with a die (for example, at least one first die 305 and at least one second die 306 are respectively provided), And the interconnection circuits on the two silicon interposers used to connect to the low-loss connector 304 are wrapped by plastic, as shown in Figure 7; firstly, the plastic is removed by laser or chemical methods to expose the interconnection The circuit is shown in Fig.
  • the two interconnected silicon interposers that expose the interconnection circuit are separated, and each of the separated silicon interposers is connected to the substrate 303 (for example, the separated The two silicon interposers are respectively mounted on the substrate 303), as shown in FIG. 9; finally, the two silicon interposers are electrically connected through a low-loss connector 304, and the obtained integrated circuit can be shown in FIG. 3.
  • the advantage is that there is no plastic encapsulation on each silicon interposer, that is, each silicon interposer is used for pasting.
  • the areas where the die and the low-loss connector 304 are mounted are completely exposed, so there is no need for additional laser or chemical methods to remove the plastic package.
  • the die and the low-loss connector 304 can be directly mounted on the silicon interposer. on. Therefore, it will be more convenient and simpler to manufacture through the 2.5D TSV process where the silicon interposer is applied to the substrate first.
  • the trace width of the interconnection layer of the low-loss connector 304 matches the trace width of the first interconnection circuit 3011 and the second interconnection circuit 3012, so that the impedance on the signal transmission path can be continuous, thereby Reduce signal transmission loss and improve signal quality.
  • the lowest line width/line distance of the low-loss connector 304 is equal to 0.4um (micrometer)/0.4um, that is, when two silicon interposers are connected through the low-loss connector 304, the lowest line width/line distance can be Reaching 0.4um/0.4um, which is greatly improved compared with the 13um/13um line width/line spacing achieved by the wiring in the prior art substrate, so that the integrated circuit can be reduced when more dies are integrated
  • the package size of the integrated circuit is reduced, the thickness of the substrate in the integrated circuit is reduced, and the design pressure of the substrate is simplified, thereby reducing the cost of the integrated circuit.
  • the multi-intermediate-layer interconnected integrated circuit provided by the embodiments of the present application can realize the signal interconnection requirements of high density, high bandwidth, low loss, and low delay, thereby providing more competition for high-end chips with high bandwidth, high speed and high performance. Powerful interconnection solutions, which in turn strongly enhance product performance and competitiveness.
  • a terminal device in another aspect of the present application, includes a printed circuit board (PCB) and an integrated circuit interconnected by multiple interposers.
  • the structure of the integrated circuit may be as shown in Figure 3 above.
  • the integrated circuit is arranged on one side of the PCB and forms an electrical connection with the PCB.

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Abstract

一种多中介层互联的集成电路，涉及电子技术领域，用于提高不同硅中介层互联时，传输的信号质量。所述多中介层互联的集成电路包括：采用低损耗连接器（304）将第一半导体中介层（301）和第二半导体中介层（302）中的互联电路形成电连接以实现不同半导体中介层之间的互联，由于低损耗连接器（304）的损耗较小，从而使得不同半导体中介层上设置的裸片之间的信号传输路径上的传输损耗较小，进而提高了该传输路径上的信号质量。

Description

一种多中介层互联的集成电路 技术领域
本申请涉及电子技术领域，尤其涉及一种多中介层互联的集成电路。
背景技术
随着电子技术的不断发展，对芯片性能要求也日渐提高，如功能增强、尺寸减小等，从而出现了2.5D硅通孔(Through-Silicon-Via，TSV)技术。2.5D TSV硅中介层(silicon interposer)技术是三维集成电路中实现堆叠芯片互连的一种技术解决方案，该方案可以通过硅中介层将多颗不同的裸片(die)集成在一起，相比传统的单裸片芯片而言，极大地提高了芯片的整体性能。然而，由于硅中介层尺寸的限制，单个硅中介层上集成的多个裸片的数量，仍无法满足业界对于集成更多个裸片的持续需求。
现有技术中，提供了一种将多个硅中介层集成在单个基板上，通过基板的走线来完成不同硅中介层之间的互联，从而实现更多个裸片的集成。比如，图1所示的芯片，该芯片中包含一个基板，基板上面有两个硅中介层，每个硅中介层上合封了1个系统级芯片(system on chip，SOC)和4个高带宽内存(High band-width Memory，HBM)。图1示出了该芯片的俯视图，图2示出了该芯片的侧视切面图，图2中的BGA球为球栅阵列(Ball Grid Array)球。
但是，基板中的走线由于工艺问题，依然停留在表面很粗糙并且线宽线距(比如，13um/13um)较大的状态、互联密度低，而硅中介层中的走线可以做到超细的线宽线距(比如，0.4um/0.4um)的超高互联密度。因此，通过基板将不同的硅中介层互联，会使得信号传输需要通过多重路径、跨越不同的阻抗，从而极大地影响了信号质量。
发明内容
本申请提供一种多中介层互联的集成电路，用于提高不同硅中介层互联时，传输的信号质量。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种多中介层互联的集成电路，该集成电路包括：第一半导体中介层、第二半导体中介层、基板以及低损耗连接器，第一半导体中介层、第二半导体中介层和低损耗连接器设置于基板的同一侧；其中，第一半导体中介层背对基板的一侧设置有至少一个第一裸片，第一半导体中介层中设置有第一互联电路；第二半导体中介层背对基板的一侧设置有至少一个第二裸片，第二半导体中介层中设置有第二互联电路；至少一个第一裸片中的其中一个裸片通过第一互联电路、低损耗连接器、第二互联电路与至少一个第二裸片中的其中一个裸片形成电连接。
上述技术方案中，由于采用低损耗连接器将第一半导体中介层的第一互联电路和第二半导体中介层的第二互联电路连接，从而使得不同半导体中介层上的裸片之间的传输路径相比于现有技术中的传输路径，信号传输损耗较小，从而提高了该集成电路中信号的质量。
在第一方面的一种可能的实现方式中，低损耗连接器包括基体、以及设置在基体 一侧的互联层，至少一个第一裸片和至少一个第二裸片具体通过低损耗连接器中的互联层连接。上述可能的实现方式中，第一半导体中介层的互联层和第二半导体中介层的互联层直接通过低损耗连接器连接，从而实现不同裸片之间的互联，此时该集成电路中信号的传输路径具体为：裸片-第一半导体中介层的互联电路-低损耗连接器的互联层-第二半导体中介层的互联电路-裸片，从而与现有技术相比，能够大大减小信号的传输路径，进一步提高信号的质量。
在第一方面的一种可能的实现方式中，所述互联层的走线宽度与第一互联电路和第二互联电路的走线宽度相匹配。上述可能的实现方式中，能够使得信号传输路径上的阻抗连续，从而降低信号传输损耗，提高信号质量。
在第一方面的一种可能的实现方式中，低损耗连接器的最低线宽/线距等于0.4um/0.4um。上述可能的实现方式中，通过低损耗连接器第一半导体中介层和第二半导体中介层时，能够使得最低线宽/线距达到0.4um/0.4um，与现有技术的基板中走线实现的线宽/线距13um/13um相比得到了很大提升，从而在集成更多个裸片时，能够减小该集成电路的封装尺寸、降低该集成电路中基板的厚度、简化基板的设计压力，进而降低该集成电路的成本。
在第一方面的一种可能的实现方式中，低损耗连接器的基体为塑封材料；可选的，低损耗连接器的结构为有机介质和重布线层混合的结构。上述可能的实现方式能够降低该低损耗连接器304的成本，同时使用有机介质和重布线层混合的结构，能够提高该低损耗连接器304的性能、减小尺寸。
在第一方面的一种可能的实现方式中，低损耗连接器的基体为硅基体，或者低损耗连接器的基体为玻璃基体。上述可能的实现方式中，提供了几种可能的低损耗连接器的基体，从而能够提高该低损耗连接器的多样性和灵活性。
在第一方面的一种可能的实现方式中，至少一个第一裸片为多个第一裸片，至少一个第二裸片为多个第一裸片，第一半导体中介层还设置有第一互联电路，第二半导体中介层还设置有第二互联电路，第一互联电路还用于形成每颗第一裸片之间的电连接，第二互联电路还用于形成每颗第二裸片之间的电连接。上述可能的实现方式中，能够使得信号在第一半导体中介层上的任一裸片与第二半导体中介层上的任一裸片之间传输，同时能够提高信号质量。
在第一方面的一种可能的实现方式中，至少一个第一裸片和至少一个第二裸片均包括专用集成电路ASIC和高带宽内存HBM。上述可能的实现方式，能够实现不同类型的多个裸片的集成。
在第一方面的一种可能的实现方式中，第一半导体中介层和第二半导体中介层为硅中介层；或者，第一半导体中介层和第二半导体中介层的结构为有机介质和重布线层混合的结构。上述可能的实现方式，能够提高半导体中介层的多样性和灵活性。
第二方面，提供一种终端设备，该终端设备包括印制电路板PCB，以及如上述第一方面或者第一方面的任一种可能的实现方式所提供的多中介层互联的集成电路，该集成电路设置于所述PCB的一侧并与所述PCB形成电连接。其中，关于该终端设备可达到的有益效果可参考上文所提供的多中介层互联的集成电路中的有益效果的描述，此处不再赘述。
附图说明
图1为现有技术提供的一种芯片的结构示意图一；
图2为现有技术提供的一种芯片的结构示意图二；
图3为本申请实施例提供的一种集成电路的结构示意图一；
图4为本申请实施例提供的一种集成电路的结构示意图二；
图5为本申请实施例提供的一种低损耗连接器的结构示意图；
图6为本申请实施例提供的一种集成电路的结构示意图三；
图7为本申请实施例提供的一种集成电路的结构示意图四；
图8为本申请实施例提供的一种集成电路的结构示意图五；
图9为本申请实施例提供的一种集成电路的结构示意图六。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在介绍本申请实施例之前，首先对本申请涉及的背景技术进行介绍说明。
2.5D TSV技术能够提高芯片的性能，比如，增强芯片的功能、减小芯片的尺寸等。2.5D TSV硅中介层(silicon interposer)技术是三维集成电路中实现堆叠芯片互连的一种技术解决方案，该方案可以通过硅中介层将多颗不同的裸片(die)集成在一起，相比传统的单裸片芯片而言，极大地提高了芯片的整体性能。该技术方案使用半导体工艺在硅片上制作的线宽、节点间距都比树脂基板上制作的线宽、节点间距小得多，从而能够将不同功能的芯片(比如CPU、DRAM等)连到同一块硅中介层上面，通过硅中介层完成大量运算和数据交流，从而大大增加芯片在三维方向堆叠的密度、缩短芯片之间的互连线、减小外观尺寸、显著降低噪声、减小RC延迟，并改善芯片速度和低功耗的性能等。
现有技术中，为了满足业界对于集成更多个裸片的持续需求，提供了一种将多颗硅中介层集成在单颗基板(substrate)上，通过基板的走线来完成不同硅中介层之间的互联，从而实现更多个裸片的集成。但是，基板中的走线由于工艺问题，依然停留在表面很粗糙并且线宽线距(比如，13um/13um)较大的状态、互联密度低，通过基板将不同的硅中介层互联，会使得信号传输需要通过多重路径、跨越不同的阻抗(以图 1为例，此时信号的传输路径为：SoC-硅中介层-TSV-C4凸点(bump)-基板-C4凸点-TSV-硅中介层-SoC)，从而极大地影响了信号质量。基于此，本申请实施例提供一种集成电路，用于在保证信号质量的同时，实现更多个裸片的集成。
图3为本申请实施例提供的一种多中介层互联的集成电路的结构示意图，参见图3，该集成电路包括：第一半导体中介层301、第二半导体中介层302、基板303、以及低损耗连接器304，第一半导体中介层301、第二半导体中介层302和低损耗连接器304设置于基板303的同一侧。其中，第一半导体中介层301背对基板303的一侧设置有至少一个第一裸片305，第一半导体中介层301中设置有第一互联电路3011；第二半导体中介层302背对基板303的一侧设置有至少一个第二裸片306，第二半导体中介层302中设置有第二互联电路3021；至少一个第一裸片305中的其中一个第一裸片通过第一互联电路3011、低损耗连接器304、第二互联电路3021与至少一个第二裸片306中的其中一个第二裸片形成电连接。
在本申请实施例中，多中介层的互联可以包括两个或者两个以上的半导体中介层的互联，低损耗连接器304可以是连接每两个相邻的半导体中介层，也可以是连接其中一组相邻的两个半导体中介层，本申请实施例以第一半导体中介层301和第二半导体中介层302为例进行说明。
另外，第一半导体中介层301和第二半导体中介层302可以为硅中介层，比如该硅中介层可以是一层硅、一层金属(比如铜)交替形成的中介层。或者，第一半导体中介层301和第二半导体中介层302的结构可以为有机介质和重布线层混合的结构，比如，该结构为PI/RDL结构，PI可以是指聚酰亚胺(polyimide)，RDL可以是指重布线层(redistribution layer)，这里PI/RDL结构可以是指一层PI、一层金属(比如铜)交替形成的中介层的结构。PI/RDL结构的特点是性能较好，且尺寸较小。具体的PI/RDL结构可以参见现有技术中的相关描述，本申请实施例对此不作阐述。本文中以硅中介层为例进行说明。
需要说明的是，图3中以至少一个第一裸片305和至少一个第二裸片306均包括应用专用集成电路(Application Specific Integrated Circuit，ASIC)和高带宽内存(High band-width Memory，HBM)为例进行说明，图3不对本申请实施例构成限制。在实际应用中，至少一个第一裸片305和至少一个第二裸片306也可以包括系统级芯片(system on chip，SOC)和高带宽内存HBM，或者包括其他不同的裸片等，本申请实施例对此不作具体限定。另外，图3为该集成电路的侧视切面图，图4是与图3对应的俯视图，图3中的BGA球为球栅阵列(Ball Grid Array)球。
可选的，第一半导体中介层301的第一互联电路3011具体可以是第一半导体中介层301的顶层金属，第二半导体中介层302的第二互联电路3021具体可以是第二半导体中介层302的顶层金属。
在上述集成电路中，由于采用低损耗连接器304将第一半导体中介层301的第一互联电路3011和第二半导体中介层302的第二互联电路3021连接，从而使得不同半导体中介层上的裸片之间的传输路径相比于现有技术中的传输路径，信号传输损耗较小，从而提高了该集成电路中信号的质量。
进一步的，参见图3，至少一个第一裸片305为多个第一裸片，至少一个第二裸 片306为多个第二裸片，第一半导体中介层301还设置有第一互联电路3011，第二半导体中介层302还设置有第二互联电路3021，第一互联电路3011还用于形成每个第一裸片之间的电连接，第二互联电路3021还用于形成每个第二裸片之间的电连接。在本申请实施例中，当至少一个第一裸片305和至少一个第二裸片306均包括多个裸片时，能够满足业界对于集成更多裸片的需求，同时信号传输无需通过多重路径、跨越不同的阻抗(以图3为例，此时信号的传输路径可以为：ASIC-第一互联电路3011-低损耗连接器304-第二互联电路3021-ASIC)，从而能够提高集成有多个裸片的集成电路的信号质量。
在一种可能的实施例中，低损耗连接器304包括基体、以及设置在基体一侧的互联层，至少一个第一裸片305和至少一个第二裸片306具体通过低损耗连接器304中的互联层连接。此时以图3为例，该集成电路中信号的传输路径可以为：ASIC-第一互联电路3011-低损耗连接器304的互联层-第二互联电路3021-ASIC。
可选的，低损耗连接器304的基体可以为硅基体、塑封(molding)或者玻璃基体等；该互联层可以是金属层，比如该金属层可以为铜层，该互联层上还可以包括互联凸点，该互联凸点具体可以是该互联层与硅中介层的顶层金属之间的连接点。
示例性的，如图5所示，低损耗连接器304可以是在硅基体上生长互联层得到，或者在塑封上生长互联层得到，或者在玻璃基体上生长互联层得到；可选的，当该互联层上还包括互联凸点时，可以在该互联层生长完成之后，继续生长互联凸点。其中，在硅基体、塑封或者玻璃基体上生长该互联层后，可以得到较大尺寸的基底，之后可以按照低损耗连接器304的尺寸，将该基底切割成单个低损耗连接器304。图5中的(a)示出了硅基体/塑封/玻璃基体的俯视图，图5中的(b)示出了生长互联层之后的基底的俯视图，图5中的(c)示出了单个低损耗连接器304的俯视图和侧视切面图。
其中，当低损耗连接器304的基体为玻璃基体时，低损耗连接器304的结构可以是PI/RDL结构，PI可以是指聚酰亚胺，RDL可以是指重布线层，PI/RDL结构的连接器的性能较好，且尺寸较小。具体的PI/RDL结构可以参见现有技术中的相关描述，本申请实施例对此不作阐述。
进一步的，第一半导体中介层301和第二半导体中介层302可以是通过硅中介层先上基板(interposer OS first)的2.5D TSV工艺制作得到，OS是on substrate的缩写。具体的，先将两个硅中介层与基板303连接，具体如图6所示；之后，再将至少一个第一裸片305、至少一个第二裸片306和低损耗连接器304与连接有基板303的两个硅中介层连接(比如，至少一个第一裸片305、至少一个第二裸片306和低损耗连接器304分别贴装在两个硅中介层上)，得到的集成电路可以参见图3所示。
或者，第一半导体中介层301和第二半导体中介层302可以是通过硅中介层后上基板(interposer OS last)的2.5D TSV工艺制作得到。具体的，通过2.5D TSV工艺得到相互连接的两个硅中介层，每个硅中介层上设置有裸片(比如分别设置有至少一个第一裸片305和至少一个第二裸片306)，且两个硅中介层上用于与低损耗连接器304连接的互联电路由塑封包裹着，具体如图7所示；首先，通过激光或者化学等方法将该塑封清除掉，以暴露出该互联电路，具体如图8所示；之后，再将暴露出该互联电路的相互连接的两个硅中介层分割开，将分割得到的每个硅中介层与基板303连接(比 如，将分割得到的两个硅中介层分别贴装在基板303上)，具体如图9所示；最后，通过低损耗连接器304将两个硅中介层电连接，得到的集成电路可以参见图3所示。
上述两种不同的2.5D TSV工艺中，硅中介层先上基板与硅中介层后上基板相比，其优点在于每个硅中介层上并没有塑封，即每个硅中介层上用于贴装裸片和低损耗连接器304的区域都是完全暴露的，所以也就不需要额外的激光或者化学等方法去除该塑封，可直接将裸片和低损耗连接器304贴装在硅中介层上。因此，通过硅中介层先上基板的2.5D TSV工艺制作会更加方便、简单。
需要说明的是，上述图6-图9中均以两个硅中介层、每个硅中介层上集成的裸片包括HBM和ASIC为例进行说明，其并不对本申请实施例构成限定。
在本申请实施例中，低损耗连接器304的互联层的走线宽度与第一互联电路3011和第二互联电路3012的走线宽度相匹配，这样能够使得信号传输路径上的阻抗连续，从而降低信号传输损耗，提高信号质量。可选的，低损耗连接器304的最低线宽/线距等于0.4um(微米)/0.4um，即通过该低损耗连接器304连接两个硅中介层时，能够使得最低线宽/线距达到0.4um/0.4um，与现有技术的基板中走线实现的线宽/线距13um/13um相比得到了很大提升，从而在集成更多个裸片时，能够减小该集成电路的封装尺寸、降低该集成电路中基板的厚度、简化基板的设计压力，进而降低该集成电路的成本。
本申请实施例提供的多中介层互联的集成电路，能够实现高密度、高带宽、低损耗、低延迟的信号互联需求，从而对于高带宽、高速率、高性能的高端芯片提供了更具竞争力的互联解决方案，进而有力提升了产品的性能和竞争力。
在本申请的另一方面，提供一种终端设备，该终端设备包括印制电路板(printed circuit board，PCB)和多中介层互联的集成电路，该集成电路的结构可以如上述图3-图9所示，该集成电路设置于该PCB的一侧并与该PCB形成电连接。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种多中介层互联的集成电路，其特征在于，所述集成电路包括：第一半导体中介层、第二半导体中介层、基板以及低损耗连接器；所述第一半导体中介层、所述第二半导体中介层和所述低损耗连接器设置于所述基板的同一侧；其中，
    所述第一半导体中介层背对所述基板的一侧设置有至少一个第一裸片，所述第一半导体中介层中设置有第一互联电路；
    所述第二半导体中介层背对所述基板的一侧设置有至少一个第二裸片，所述第二半导体中介层中设置有第二互联电路；
    所述至少一个第一裸片中的其中一个第一裸片通过所述第一互联电路、所述低损耗连接器、所述第二互联电路与所述至少一个第二裸片中的其中一个第二裸片形成电连接。
  2. 根据权利要求1所述的集成电路，其特征在于，所述低损耗连接器包括基体、以及设置在所述基体一侧的互联层，所述至少一个第一裸片和所述至少一个第二裸片具体通过所述低损耗连接器中的互联层连接。
  3. 根据权利要求2所述的集成电路，其特征在于，所述互联层的走线宽度与所述第一互联电路和所述第二互联电路的走线宽度相匹配。
  4. 根据权利要求3所述的集成电路，其特征在于，所述低损耗连接器的最低线宽/线距等于0.4um/0.4um。
  5. 根据权利要求2至4任意一项所述的集成电路，其特征在于，所述基体为塑封材料。
  6. 根据权利要求5所述的集成电路，其特征在于，所述低损耗连接器的结构为有机介质和重布线层混合的结构。
  7. 根据权利要求2至4任意一项所述的集成电路，其特征在于，所述基体为硅基体。
  8. 根据权利要求2至4任意一项所述的集成电路，其特征在于，所述基体为玻璃基体。
  9. 根据权利要求1至8任意一项所述的集成电路，其特征在于，所述至少一个第一裸片为多个第一裸片，所述至少一个第二裸片为多个第二裸片，所述第一半导体中介层还设置有所述第一互联电路，所述第二半导体中介层还设置有所述第二互联电路，所述第一互联电路还用于形成每个第一裸片之间的电连接，所述第二互联电路还用于形成每个第二裸片之间的电连接。
  10. 根据权利要求9所述的集成电路，其特征在于，所述至少一个第一裸片和所述至少一个第二裸片均包括专用集成电路ASIC和高带宽内存HBM。
  11. 根据权利要求1至10任意一项所述的集成电路，其特征在于，所述第一半导体中介层和第二半导体中介层为硅中介层；或者，所述第一半导体中介层和第二半导体中介层的结构为有机介质和重布线层混合的结构。
  12. 一种终端设备，其特征在于，所述终端设备包括印制电路板PCB，以及如权利要求1-11任一项所述的多中介层互联的集成电路，所述集成电路设置于所述PCB的 一侧并与所述PCB形成电连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130200511A1 (en) * 2012-02-08 2013-08-08 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
US9570375B2 (en) * 2012-06-27 2017-02-14 Longitude Semiconductor S.A.R.L. Semiconductor device having silicon interposer on which semiconductor chip is mounted
WO2018004620A1 (en) * 2016-06-30 2018-01-04 Qian Zhiguo Bridge die design for high bandwidth memory interface
US20180102469A1 (en) * 2016-10-11 2018-04-12 Massachusetts Institute Of Technology Cryogenic electronic packages and methods for fabricating cryogenic electronic packages

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9548251B2 (en) * 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
US9196575B1 (en) * 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
US9402312B2 (en) * 2014-05-12 2016-07-26 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US10192836B2 (en) * 2015-03-30 2019-01-29 Pezy Computing K.K. Semiconductor device
KR20160122022A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 인터포저를 갖는 반도체 패키지 및 제조 방법
US10074630B2 (en) * 2015-04-14 2018-09-11 Amkor Technology, Inc. Semiconductor package with high routing density patch
US9842813B2 (en) * 2015-09-21 2017-12-12 Altera Corporation Tranmission line bridge interconnects
US9761533B2 (en) * 2015-10-16 2017-09-12 Xilinx, Inc. Interposer-less stack die interconnect

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130200511A1 (en) * 2012-02-08 2013-08-08 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
US9570375B2 (en) * 2012-06-27 2017-02-14 Longitude Semiconductor S.A.R.L. Semiconductor device having silicon interposer on which semiconductor chip is mounted
WO2018004620A1 (en) * 2016-06-30 2018-01-04 Qian Zhiguo Bridge die design for high bandwidth memory interface
US20180102469A1 (en) * 2016-10-11 2018-04-12 Massachusetts Institute Of Technology Cryogenic electronic packages and methods for fabricating cryogenic electronic packages

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