CN112889149A - 一种多中介层互联的集成电路 - Google Patents

一种多中介层互联的集成电路 Download PDF

Info

Publication number
CN112889149A
CN112889149A CN201980065923.6A CN201980065923A CN112889149A CN 112889149 A CN112889149 A CN 112889149A CN 201980065923 A CN201980065923 A CN 201980065923A CN 112889149 A CN112889149 A CN 112889149A
Authority
CN
China
Prior art keywords
integrated circuit
substrate
interposer
die
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201980065923.6A
Other languages
English (en)
Other versions
CN112889149B (zh
Inventor
陶军磊
赵南
张晓东
王晨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN112889149A publication Critical patent/CN112889149A/zh
Application granted granted Critical
Publication of CN112889149B publication Critical patent/CN112889149B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种多中介层互联的集成电路，涉及电子技术领域，用于提高不同硅中介层互联时，传输的信号质量。所述多中介层互联的集成电路包括：采用低损耗连接器(304)将第一半导体中介层(301)和第二半导体中介层(302)中的互联电路形成电连接以实现不同半导体中介层之间的互联，由于低损耗连接器(304)的损耗较小，从而使得不同半导体中介层上设置的裸片之间的信号传输路径上的传输损耗较小，进而提高了该传输路径上的信号质量。

Description

PCT国内申请，说明书已公开。

Claims (12)

  1. PCT国内申请，权利要求书已公开。
CN201980065923.6A 2019-01-18 2019-01-18 一种多中介层互联的集成电路 Active CN112889149B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/072323 WO2020147107A1 (zh) 2019-01-18 2019-01-18 一种多中介层互联的集成电路

Publications (2)

Publication Number Publication Date
CN112889149A true CN112889149A (zh) 2021-06-01
CN112889149B CN112889149B (zh) 2023-09-08

Family

ID=71613637

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980065923.6A Active CN112889149B (zh) 2019-01-18 2019-01-18 一种多中介层互联的集成电路

Country Status (2)

Country Link
CN (1) CN112889149B (zh)
WO (1) WO2020147107A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117457619A (zh) * 2023-12-26 2024-01-26 北京奎芯集成电路设计有限公司 一种基于高带宽互联技术的半导体器件
WO2024093965A1 (zh) * 2022-10-31 2024-05-10 上海嘉楠捷思信息技术有限公司 芯片及其制造、封装方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
US20130200511A1 (en) * 2012-02-08 2013-08-08 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
US20150327367A1 (en) * 2014-05-12 2015-11-12 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US9196575B1 (en) * 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
US20160307870A1 (en) * 2015-04-14 2016-10-20 Amkor Technology, Inc. Semiconductor package with high routing density patch
CN106057788A (zh) * 2015-04-13 2016-10-26 爱思开海力士有限公司 具有中介层的半导体封装及其制造方法
CN106549002A (zh) * 2015-09-21 2017-03-29 阿尔特拉公司 传输线桥接互连
WO2018004620A1 (en) * 2016-06-30 2018-01-04 Qian Zhiguo Bridge die design for high bandwidth memory interface
US20180033743A1 (en) * 2015-03-30 2018-02-01 Pezy Computing K.K. Semiconductor device
CN108352378A (zh) * 2015-10-16 2018-07-31 赛灵思公司 无中介层的叠式裸片互连

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014011169A (ja) * 2012-06-27 2014-01-20 Ps4 Luxco S A R L シリコンインターポーザ及びこれを備える半導体装置
US10381541B2 (en) * 2016-10-11 2019-08-13 Massachusetts Institute Of Technology Cryogenic electronic packages and methods for fabricating cryogenic electronic packages

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
US20130200511A1 (en) * 2012-02-08 2013-08-08 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
US9196575B1 (en) * 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
US20150327367A1 (en) * 2014-05-12 2015-11-12 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US20180033743A1 (en) * 2015-03-30 2018-02-01 Pezy Computing K.K. Semiconductor device
CN106057788A (zh) * 2015-04-13 2016-10-26 爱思开海力士有限公司 具有中介层的半导体封装及其制造方法
US20160307870A1 (en) * 2015-04-14 2016-10-20 Amkor Technology, Inc. Semiconductor package with high routing density patch
CN106549002A (zh) * 2015-09-21 2017-03-29 阿尔特拉公司 传输线桥接互连
CN108352378A (zh) * 2015-10-16 2018-07-31 赛灵思公司 无中介层的叠式裸片互连
WO2018004620A1 (en) * 2016-06-30 2018-01-04 Qian Zhiguo Bridge die design for high bandwidth memory interface

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024093965A1 (zh) * 2022-10-31 2024-05-10 上海嘉楠捷思信息技术有限公司 芯片及其制造、封装方法
CN117457619A (zh) * 2023-12-26 2024-01-26 北京奎芯集成电路设计有限公司 一种基于高带宽互联技术的半导体器件
CN117457619B (zh) * 2023-12-26 2024-04-05 北京奎芯集成电路设计有限公司 一种基于高带宽互联技术的半导体器件

Also Published As

Publication number Publication date
CN112889149B (zh) 2023-09-08
WO2020147107A1 (zh) 2020-07-23

Similar Documents

Publication Publication Date Title
US10114775B2 (en) Stacked semiconductor device assembly in computer system
CN107039393B (zh) 半导体器件
US11063017B2 (en) Embedded organic interposer for high bandwidth
US9847248B2 (en) Method of making a stacked device assembly
US7365992B2 (en) Electronic circuit package
US20030020171A1 (en) Semiconductor package
US6538213B1 (en) High density design for organic chip carriers
US20210217737A1 (en) Semiconductor packages with pass-through clock traces and associated systems and methods
KR101780145B1 (ko) 시스템 온 칩 상의 컴포넌트 파티션 방법 및 이의 디바이스
CN112889149B (zh) 一种多中介层互联的集成电路
CN102915996A (zh) 用于3d集成电路的电性互连机构
JP2003529203A (ja) 配線層当たりの信号ライン数を最大化するための変動ピッチ・コンタクト・アレイを有する集積回路および／またはパッケージ
US20060027935A1 (en) Semiconductor device with semiconductor components connected to one another
CN114400219A (zh) 半导体器件及其制造方法、封装器件和电子装置
US20140061950A1 (en) Stackable flip chip for memory packages
KR20010062801A (ko) 도체 임피던스가 조립 중에 선택되는 반도체 패키지
US11101542B2 (en) Integrated radio package having a built-in multi directional antenna array
CN114400209A (zh) 中介层、半导体封装器件和电子装置
CN116114396A (zh) 前道工艺互连结构以及相关联的系统和方法
CN111883499A (zh) 多芯片封装的半导体器件及其形成方法
CN217426742U (zh) 电子器件
CN216902914U (zh) 一种硅基基板及芯片
CN218039195U (zh) 半导体封装结构
US8125087B2 (en) High-density flip-chip interconnect
CN221176222U (zh) 基于晶粒互联的半导体封装

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant