CN104425467B - 叠层封装体及其制造方法 - Google Patents

叠层封装体及其制造方法 Download PDF

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Publication number
CN104425467B
CN104425467B CN201410108380.0A CN201410108380A CN104425467B CN 104425467 B CN104425467 B CN 104425467B CN 201410108380 A CN201410108380 A CN 201410108380A CN 104425467 B CN104425467 B CN 104425467B
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chip
layer
backside
insulating layer
package body
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CN104425467A (zh
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梁胜宅
金锺薰
吴卓根
罗松
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

实施例的叠层封装体可以包括：上芯片，在下芯片之上；背面钝化层，覆盖下芯片的背面表面，并且具有与下通孔电极的突出部的高度大体相等的厚度；背面凸块，与突出部大体接触；以及正面凸块，与上芯片的芯片接触部电耦接，并且与背面凸块物理和电连接。背面钝化层可以包括被提供在突出部的侧壁之上和下芯片的背面表面之上的第一绝缘层。还公开了制造方法的实施例。

Description

叠层封装体及其制造方法
相关申请的交叉引用
本申请要求2013年8月29日向韩国知识产权局提交的申请号为10-2013-0103078的韩国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
实施例涉及一种封装技术，更具体而言，涉及一种包括通孔电极的叠层封装体及其制造方法。
背景技术
用于电子系统的半导体器件可以包括各种电子电路元件，并且电子电路元件可以被集成在半导体衬底中和/或上，以构成半导体器件（此外，被称作为半导体芯片或半导体裸片）。存储器半导体芯片也可以用于电子系统中。在包括存储器半导体芯片的半导体器件用于电子系统之前，半导体器件可以被封装以形成封装体。这些半导体封装体可以用于电子系统，例如计算机、移动系统或数据存储媒介。
随着诸如智能电话的移动系统变得更轻且更小，用于移动系统的半导体封装体会不断地按比例缩小。另外，随着多功能的移动系统的发展，越来越需要大容量的半导体封装体。结合这种情况，已经致力于将多个半导体器件置于单个封装体中，以提供诸如叠层封装体的大容量的半导体封装体。另外，已经提出了穿过半导体芯片的穿硅通孔（TSV）电极以将单个叠层封装体中的半导体芯片彼此电连接。
发明内容
各种实施例涉及叠层封装体及其制造方法。
根据一些实施例，一种叠层封装体包括：上芯片，在下芯片上；下通孔电极，穿过下芯片，并且包括从下芯片的背面表面突出的突出部；背面钝化层，覆盖下芯片的背面表面，并且具有与突出部的高度大体相等的厚度；背面凸块，与突出部的顶表面大体接触；以及正面凸块，与上芯片的芯片接触部电连接，并且与背面凸块物理且电连接。背面钝化层包括：第一绝缘层，覆盖突出部的侧壁和下芯片的背面表面；和第二绝缘层，在第一绝缘层上。
根据另外的实施例，一种叠层封装体包括：上芯片，被设置在下通孔电极穿过的下芯片上；模塑件，覆盖下芯片的侧壁和上芯片的侧壁；外连接端子，被设置在下芯片的正面表面上和模塑件的底表面上；以及重布线，将外连接端子与下通孔电极电连接，并且被设置在下芯片的正面表面上。
根据另外的实施例，一种制造叠层封装体的方法包括以下步骤：在包括下通孔电极的下芯片的背面表面上形成第一绝缘层。下通孔电极具有从下芯片的背面表面突出的突出部，并且第一绝缘层被形成覆盖突出部的侧壁。第二绝缘层形成在第一绝缘层上，并且第二绝缘层被形成具有与突出部的高度大体相等的厚度。背面凸块被形成与突出部的顶表面大体接触。上芯片层叠在下芯片上，使得背面凸块与电连接至上芯片的芯片接触部的正面凸块电连接且物理连接。第一绝缘层和第二绝缘层构成背面钝化层。
附图说明
结合附图和所附详细说明来描述实施例，其中：
图1是说明根据一个实施例的叠层封装体的截面图；
图2至图4是说明根据一个实施例的构成叠层封装体的各种半导体芯片的截面图；
图5是说明根据一个实施例的构成叠层封装体的半导体芯片之间的互连结构的截面图；
图6至图12是说明根据一个实施例的一种制造叠层封装体的方法的截面图；
图13至图17是说明根据一个实施例的一种形成构成叠层封装体的半导体芯片的互连凸块的方法的截面图；
图18是说明包括根据一个实施例的叠层封装体的一种电子系统的框图；以及
图19是说明包括根据一个实施例的叠层封装体的另一种电子系统的框图。
具体实施方式
实施例可以提供包括多个层叠芯片的叠层封装体以及制造叠层封装体的方法，多个层叠芯片通过通孔电极电连接。每个叠层封装体可以包括外连接端子，并且外连接端子可以排列在层叠芯片中的最下面芯片的底表面上、和覆盖层叠芯片的侧壁的模塑件的底表面上。即，模塑件的底表面可以用作叠层封装体的整个底表面的一部分。因而，即使最下面芯片的宽度减小，外连接端子也可以容易地排列在叠层封装体的整个底表面上，而不减小外连接端子之间的间距、或者不减小外连接端子的宽度。
将理解的是，尽管本文中可以利用术语第一、第二、第三等来描述各种元件，但是不应当采用限制的方式来解释这些元件。这些术语仅用作区分一个元件与另一个元件。因而，在一些实施例中的第一元件在其他的实施例中可以被称作为第二元件。
将理解的是，当一个元件关于另一个元件被提及“在…上”、“在…上面”、“在…下面”或“在…之下”时，其可以关于另一个元件分别直接“在…上”、“在…上面”、“在…下面”或“在…之下”，或者也可以存在中间元件。因此，本文中使用的诸如“在…上”、“在…上面”、“在…下面”或“在…之下”的术语仅出于说明性的目的，并非意图限制实施例。
还将理解的是，当一个元件被提及与另一个元件“连接”、“耦接”时，其可以直接与其他的元件连接或耦接，或者可以存在中间元件。相反地，当一个元件被提及与另一个元件“直接连接”、“直接耦接”时，则不存在中间元件。用于描述元件或层之间关系的其他词语应当以相同的方式来解释。半导体衬底可以具有对应于集成有构成电子电路的晶体管和内部互连线的区域应的有源层。可以通过利用裸片切割工艺来将半导体衬底分成多个片来获得半导体芯片。
半导体芯片可以包括存储器芯片或逻辑芯片。存储器芯片可以包括被集成在半导体衬底上和/或中的动态随机存取存储器（DRAM）电路、静态随机存取存储器（SRAM）电路、快闪存储器电路、磁性随机存取存储器（MRAM）电路、阻变随机存取存储器（ReRAM）电路、铁电随机存取存储器（FeRAM）电路或者相变随机存取存储器（PcRAM）电路。逻辑芯片可以包括被集成在半导体衬底上和/或中的逻辑电路。在一些情况下，本文中利用的术语“半导体衬底”可以被解释为形成有集成电路的半导体芯片或半导体裸片。
参见图1，根据本实施例的叠层封装体10可以被配置成包括叠层结构，所述叠层结构具有顺序层叠的多个半导体芯片100、200和300，覆盖和保护叠层结构的侧壁的模塑件510、以及将叠层结构与外部设备或系统电连接的外连接端子550。半导体芯片100、200和300可以通过通孔连接结构而彼此电连接。
参见图1和图2，构成叠层封装体10的下半导体芯片100可以包括下半导体衬底110和穿过下半导体衬底110的下通孔电极170。下通孔电极170可以构成叠层封装体10的通孔连接结构。每个下通孔电极170可以包括从下半导体衬底110的正面表面111朝向下半导体衬底110的背面表面113延伸的导电柱体。
每个下通孔电极170可以包括可扩散金属材料，例如铜（Cu）材料、锡（Sn）材料、银（Ag）材料，包括以上所列材料中的至少两种的合金材料。在一些实施例中，每个下通孔电极170可以包括：镓（Ga）材料、铟（In）材料、锡（Sn）材料、汞（Hg）材料、铋（Bi）材料、铅（Pb）材料、金（Au）材料、锌（Zn）材料、铝（Al）材料、或者包括以上所列材料中的至少两种的合金材料。尽管附图中未示出，但是绝缘内衬可以被设置在下通孔电极170与下半导体衬底110之间。
阻挡金属层可以被设置在下半导体衬底110和下通孔电极170之间。更具体地，阻挡金属层可以被设置在绝缘内衬和下通孔电极170之间。阻挡金属层可以防止下通孔电极170中的金属原子扩散至下半导体衬底110中。例如，阻挡金属层可以包括：钛（Ti）材料、钽（Ta）材料、钨（W）材料、氮化钛（TiN）材料、氮化钽（TaN）材料、氮化钨（WN）材料、氮化钽硅（TaSiN）材料、氮化钛硅（TiSiN）材料、氮化钨硅（WSiN）材料、锰（Mn）材料、钌（Ru）材料、或者包括以上所列材料中的至少两种的合金材料。如图5中所示，下通孔电极170可以被形成包括诸如铜材料的金属材料，并且阻挡金属层177可以被形成包围下通孔电极170的侧壁。尽管附图中未示出，但是绝缘内衬可以被设置在阻挡金属层177和下半导体衬底110之间，以将下通孔电极170与下半导体衬底110电绝缘。
下半导体衬底110可以是硅衬底，并且下半导体衬底110的正面表面111可以对应于有源层的表面，其中形成有构成半导体器件（诸如存储器半导体器件）的集成电路。下半导体衬底110的背面表面113可以与正面表面111相对。诸如晶体管的构成集成电路的电路元件可以被设置在有源层中和/或上，并且层间绝缘层130和在层间绝缘层130中的内部互连结构131和133可以被设置在下半导体衬底110的正面表面111上。
内部互连结构131和133可以包括与晶体管电连接的互连线，并且下通孔电极170可以经由内部互连结构131和133与构成集成电路的电路元件电连接。内部互连结构131和133可以包括互连线和与互连线连接的连接通孔。互连线和连接通孔可以将下通孔电极170与用作接触焊盘的芯片接触部135电连接。正面钝化层140可以被设置在层间绝缘层130上，以暴露出芯片接触部135。正面钝化层140可以包括氧化硅层、氮化硅（SiN）层或他们的组合。
如图1中所示，外连接端子550可以电连接至与叠层封装体10的最下面的芯片相对应的下半导体芯片100的芯片接触部135中相应的芯片接触部135。由于下半导体芯片100的芯片接触部135与外连接端子550连接，所以下半导体芯片100可以被倒置（倒装芯片）。
再次参见图1和图2，下通孔电极170可以大体穿过下半导体衬底110的本体，并且包括从下半导体衬底110的背面表面113突出的突出部175。下通孔电极170的突出部175可以穿过覆盖下半导体衬底110的背面表面113的背面钝化层150，使得突出部175的顶表面171暴露。突出部175的暴露出的顶表面171可以用下背面凸块180来覆盖。
背面钝化层150可以包括第一背面绝缘层151和第二背面绝缘层153。第一背面绝缘层151可以被设置在背面表面113上，以覆盖下通孔电极170突出部175的侧壁。第一背面绝缘层151可以具有正形的内衬形状，以覆盖背面表面113、和突出部175的侧壁。第二背面绝缘层153可以被设置在第一背面绝缘层151上。第二背面绝缘层153可以包括与第一背面绝缘层151不同的绝缘层。背面钝化层150的表面可以与突出部175的顶表面171齐平。
第一背面绝缘层151可以被设置成直接覆盖突出部175的整个侧壁。第一背面绝缘层151可以用作防止突出部175中的金属原子（例如，铜原子）扩散或移出的扩散阻挡层。用作扩散阻挡层的第一背面绝缘层151可以包括氮化硅层或氧化硅层，以有效地阻挡金属原子或金属离子的迁移。如果突出部175中的诸如铜离子的金属离子扩散出，则扩散出的铜离子可以与第二背面绝缘层153中的硅原子反应，以形成铜硅化合物材料。具体地，如果突出部175中的诸如铜离子的金属离子被扩散至下半导体衬底110中，则扩散出的金属离子会引起形成在下半导体衬底110中的晶体管的异常操作。例如，如果突出部175中的诸如铜离子的金属离子扩散至下半导体衬底110中，则扩散出的铜离子会降低形成在下半导体衬底110中的晶体管的阈值电压特性和/或泄漏电流特性。因而，如果下半导体芯片100是DRAM器件，则会降低下半导体芯片100的刷新特性。因而，用作扩散阻挡层的第一背面绝缘层151可以防止下半导体芯片100被诸如铜离子的金属离子污染。
如上所述，背面钝化层150的第一背面绝缘层151可以具有正形地覆盖突出部175的侧壁和下半导体衬底110的背面表面113的内衬形状。因而，第一背面绝缘层151在突出部175之间可以具有凹面形状。第二背面绝缘层153可以填充由第一背面绝缘层151的凹面形状限定的空间，以形成背面钝化层150的平整表面。因此，背面钝化层150的表面可以与突出部175的顶表面171齐平。另外，第二背面绝缘层153可以用作减轻施加至背面钝化层150的压力的绝缘缓冲层。因而，第二背面绝缘层153可以减小施加至背面钝化层150的压力，以增强半导体芯片100、200和300之间的凸块结构的机械可靠性。用作绝缘缓冲层的第二背面绝缘层153可以包括氧化硅层。
下背面凸块180可以被设置成与穿过背面钝化层150的突出部175的顶表面171直接接触。每个下背面凸块180可以包括：与突出部175的顶表面171接触的背面凸块本体181、与背面凸块本体181接触的湿润层183、以及与湿润层183接触的抗氧化层185。背面凸块本体181可以包括铜，湿润层183可以包括镍，以及抗氧化层185可以包括金。在一些实施例中，每个下背面凸块180可以仅包括背面凸块本体181和湿润层183。突出部175和背面凸块本体181可以彼此接触而具有“T”形配置（从截面图观察时）。即，下背面凸块180可以具有比突出部175的宽度更大的宽度。结果，半导体芯片100和200之间的凸块结构的接触区可以增大。中间半导体芯片200可以层叠在下半导体芯片100上，使得中间半导体芯片200的中间正面凸块（图1中的290）与下背面凸块180中相应的正面凸块结合。
参见图1和图3，层叠在下半导体芯片100上的中间半导体芯片200可以具有与下半导体芯片100大体相同的功能。另外，中间半导体芯片200可以具有与下半导体芯片100大体相同的配置。不同于下半导体芯片100，中间半导体芯片200还可以包括正面凸块290（即，中间正面凸块）。中间正面凸块290可以构成下半导体芯片100与中间半导体芯片200之间的凸块结构。
中间半导体芯片200可以包括中间半导体衬底210和穿过中间半导体衬底210的中间通孔电极270。中间通孔电极270可以构成叠层封装体10的通孔连接结构。每个中间通孔电极270可以对应于从中间半导体衬底210的正面表面211向中间半导体衬底210的背面表面213延伸的导电柱体。中间半导体衬底210的正面表面211可以与设置在中间半导体衬底210中的有源层的表面相对应，并且中间半导体衬底210的背面表面213可以与中间半导体衬底210的正面表面211相对。层间绝缘层230和在层间绝缘层230中的内部互连结构231和233可以被设置在中间半导体衬底210的正面表面211上。
内部互连结构231和233可以包括互连线、和与互连线电连接的连接通孔。内部互连231和233可以将中间通孔电极270与用作接触焊盘的芯片接触部235电连接。正面钝化层240可以被设置在层间绝缘层230上，以暴露出芯片接触部235，并且中间正面凸块290可以被设置在暴露出的芯片接触部235中相应的芯片接触部235上。
每个中间正面凸块290可以包括：与芯片接触部235接触的正面凸块本体291、和层叠在正面凸块本体291上的湿润层293。正面凸块本体291可以包括，例如铜材料，并且湿润层293可以包括，例如镍材料。导电粘合剂295（例如，焊料层）可以被设置在相应的湿润层293上。导电粘合剂295可以与下背面凸块（图1中的180）结合。
每个中间通孔电极270可以穿过中间半导体衬底210，并且包括从中间半导体衬底210的背面表面213突出的突出部275，并且突出部275可以穿过覆盖中间半导体衬底210的背面表面213的背面钝化层250，使得突出部275的顶表面271暴露。突出部275的每个暴露出的顶表面271可以用中间背面凸块280来覆盖。背面钝化层250可以包括第一背面绝缘层251和第二背面绝缘层253，并且背面钝化层250可以被设置在中间半导体衬底210的背面表面213上，并且包围突出部275的侧壁。第一背面绝缘层251可以用作扩散阻挡层，并且第二背面绝缘层253可以用作绝缘缓冲层。
至少一个额外的中间半导体芯片可以层叠在中间半导体芯片200上。额外的中间半导体芯片可以具有与中间半导体芯片200相同的功能和结构。在一些实施例中，中间半导体芯片200可以具有比下半导体芯片100更大或更小的尺寸。
参见图1和图4，上半导体芯片300可以层叠在中间半导体芯片200上。上半导体芯片300可以具有与下半导体芯片100或中间半导体芯片200相同的功能。上半导体芯片300可以具有与下半导体芯片100或中间半导体芯片200相同的配置。然而，不同于下半导体芯片100和中间半导体芯片200，上半导体芯片300可以不包括任何通孔电极。上半导体芯片300可以具有比下半导体芯片100更大或更小的尺寸。
上半导体芯片300可以包括上半导体衬底310，而上半导体衬底310可以包括彼此相对的正面表面311和背面表面313。正面表面311可以与设置在上半导体衬底310中的有源层的表面相对应。中间绝缘层330以及在中间绝缘层中的内部互连结构331和333可以被设置在上半导体衬底310的正面表面311上。内部互连结构331和333可以包括互连线和与互连线电连接的连接通孔。内部互连结构331和333可以与用作接触焊盘的芯片接触部335电连接。正面钝化层340可以被设置在层间绝缘层330上，以暴露出芯片接触部335，并且上正面凸块390可以被设置在暴露出的芯片接触部335中相应的芯片接触部335上。每个上正面凸块390可以包括与芯片接触部335接触的正面凸块本体391、和层叠在正面凸块本体391上的湿润层393。正面凸块本体391可以包括，例如铜材料，并且湿润层393可以包括，例如镍材料。导电粘合剂395，例如焊料层，可以被设置在湿润层393中相应的湿润层393上。导电粘合剂395可以与中间背面凸块（图1中的280）结合。
模塑件510可以覆盖半导体芯片100、200和300的侧壁，并且暴露出上半导体衬底310的背面表面313。在一些实施例中，模塑件510可以延伸以覆盖上半导体衬底310的背面表面313。如果上半导体衬底310的背面表面313被模塑件510暴露出，则可以增强叠层封装体10的热辐射效率。在叠层封装体10中产生的热可以经由暴露出的背面表面313被便利地辐射出。
参见图1和图5，半导体芯片100、200和300可以通过提供垂直电信号路径的通孔连接结构彼此电连接。因而，叠层封装体10的水平宽度可以被最小化。通孔连接结构可以被配置成包括彼此电连接的通孔电极170和270。通孔电极170可以通过凸块结构与通孔电极270电连接。如图5中所示，与下半导体芯片100的下通孔电极170连接的下背面凸块180可以与中间半导体芯片200的中间正面凸块290垂直对准，并且下背面凸块180和中间正面凸块290可以通过诸如焊料层的导电粘合剂295彼此结合，使得中间半导体芯片200层叠在下半导体芯片100上。
如图1中所示，包括下背面凸块180和中间正面凸块290的相邻凸块结构可以通过设置在下半导体芯片100和中间半导体芯片200之间的绝缘芯片粘合剂520彼此电绝缘。绝缘芯片粘合剂520可以采用粘合薄膜形式提供，或者可以通过注入液体粘合材料来形成。可替选地，绝缘芯片粘合剂520可以在形成模510的同时与模塑件510一起形成塑。
再次参见图1，叠层封装体10可以包括外连接端子550，外连接端子550与设置在下半导体芯片100的正面表面111上的芯片接触部135电连接，芯片接触部135通过模塑件510暴露出。模塑件510可以被形成为包括环氧模塑化合物（EMC）材料。模塑件510可以被形成仅覆盖顺序层叠有半导体芯片100、200和300的叠层结构的侧壁。即，模塑件510可以暴露出下半导体芯片100（例如，芯片接触部135和正面钝化层140）的正面表面。
外连接端子550可以被配置成包括被二维排列的多个焊料球。外连接端子550可以被设置在下半导体芯片100的正面表面上也在模塑件510的底表面上。即，外连接端子550甚至可以被设置在模塑件510的底表面上。因而，可以最大化排列有外连接端子550的表面的面积。结果，即使下半导体芯片100的宽度被减小，也可以保证提供外连接端子550的面积。
为了允许外连接端子550甚至排列在模塑件510的底表面上，与相应的芯片接触部135电连接的重布线530可以延伸至模塑件510的底表面上。重布线530可以通过沉积金属材料（延伸至模塑件510的底表面上）并将其图案化来形成。重布线530可以用绝缘层540来覆盖，并且绝缘层540可以被图案化以暴露出重布线530的封装体接触部531（即，焊球着落部）。外连接端子550可以被附接至暴露出的封装体接触部531中相应的封装体接触部531。
叠层封装体10可以被配置成具有有利的热辐射效率，因为上半导体芯片300的背面表面313被暴露出。另外，外连接端子550（包括，例如焊料球）甚至可以被排列在模塑件510上，以增加外连接端子550的布局空间，或者增加外连接端子550的数目。
参见图6，下半导体芯片100可以被安装在辅助衬底710上，并且可以彼此间隔开。辅助衬底710可以是载体衬底。辅助衬底可以是玻璃衬底或硅衬底。每个下半导体芯片100可以被提供成包括下通孔电极（图1或图2中的170），如参照图2所述。下半导体芯片100可以被安装在辅助衬底710上，使得下半导体芯片100的正面表面（图2中的111）面对辅助衬底710。下半导体芯片100可以通过附着至辅助衬底710的粘合带730被固定至辅助衬底710。
参见图7，中间半导体芯片200可以层叠在相应的下半导体芯片100上。中间半导体芯片200可以利用凸块结合工艺与下半导体芯片100结合。可以执行凸块结合工艺，使得中间半导体芯片200的中间前正面凸块290与下半导体芯片100的下背面凸块180结合，如图5中所示。绝缘芯片粘合剂520可以被引入下半导体芯片100与中间半导体芯片200之间的间隙区。
参见图8，上半导体芯片300可以层叠在相应的中间半导体芯片200上。在一些实施例中，至少一个额外的中间半导体芯片可以在层叠上半导体芯片300之前层叠在每个中间半导体芯片200上。额外的中间半导体芯片可以具有与中间半导体芯片200大体相同的功能。可替选地，额外的中间半导体芯片可以具有与中间半导体芯片200不同的功能或配置。下半导体芯片100、中间半导体芯片200、和上半导体芯片300可以构成多个叠层结构。即，每个叠层结构可以包括顺序层叠的下半导体芯片100、中间半导体芯片200和上半导体芯片300。叠层结构可以被设置在辅助衬底710上以彼此间隔开。
参见图9，模塑件510可以形成在辅助衬底710上，以覆盖包括下半导体芯片100、中间半导体芯片200和上半导体芯片300的叠层结构。
参见图2和图10，辅助衬底710和粘合带730可以与下半导体芯片100脱离，以暴露出下半导体芯片100的正面表面。重布线530可以形成在下半导体芯片100的暴露出的正面表面上。即，重布线530可以形成在芯片接触部（图2中的135）、正面钝化层（图2中的140）、以及模塑件510的底表面上。可以通过在下半导体芯片100的暴露出的正面表面上沉积金属材料来形成金属层、并且将金属层图案化来形成重布线530。绝缘层540可以被形成覆盖重布线530，并且绝缘层540可以被图案化以暴露出重布线530的封装体接触部531（即，焊球着落部）。与每个下半导体芯片100连接的重布线530的封装体接触部531之中的至少一个可以在模塑件510的底表面之上延伸。
如上所述，多个叠层结构可以被二维排列，并且叠层结构的顶表面和侧壁可以用模塑件510来覆盖。因而，如同封装工艺被应用至形成在晶片上的所有半导体芯片，用于在模塑件510的底表面和下半导体芯片100的正面表面上形成重布线530的工艺每次可以被应用至所有的叠层结构。
参见图11，可以去除模塑件510的一部分，以暴露出上半导体芯片300的背面表面313。去除工艺可以利用背面研磨工艺。另外，包括例如焊料球的外连接端子550可以利用球安装工艺来附着至暴露出的封装体接触部531。
参见图1和图12，在叠层结构之间的模塑件510可以利用切割过程工艺来切割，以将叠层结构彼此分开。结果，可以形成多个叠层封装体（图1中的10）。
根据上述制造方法，半导体芯片100、200和300可以被层叠，使得包括半导体芯片100、200和300的多个叠层结构被二维排列在辅助衬底上。随后，用于形成重布线的工艺、模塑工艺、背面研磨工艺、球安装工艺和裸片切割工艺可以被顺序应用于所有的叠层结构，以形成多个独立的叠层封装体。即，如同封装工艺被应用于形成在晶片上的全部半导体芯片，多个单独的叠层封装体可以被同时形成以形成多个单独的晶片级封装体。
另外，根据以上实施例的叠层封装体可以包括由通孔电极组成的通孔连接结构以提供垂直信号路径。因而，可以实现具有大容量的紧凑封装体。另外，包围通孔电极的突出部的侧壁的背面钝化层可以被形成用作扩散阻挡层。因而，即使通孔电极包括铜材料，背面钝化层也可以防止叠层封装体被铜离子污染。
参见图13，通孔电极170和包围通孔电极170的阻挡金属层177可以穿过半导体衬底110。通孔电极170可以包括从半导体衬底110的背面表面113突出的突出部175。通孔电极170可以包括铜材料，并且通孔电极170的突出部175可以通过将半导体衬底110的背面部凹陷来暴露出。
参见图14，背面钝化层150可以形成在半导体衬底110的背面表面113上，以覆盖通孔电极170的突出部175。具体地，第一背面绝缘层151可以被形成覆盖包围突出部175的阻挡金属层177的侧壁173和顶表面。第一背面绝缘层151可以是正形内衬层。第一背面绝缘层151可以用作防止通孔电极170中的金属离子扩散出的扩散阻挡层。例如，第一背面绝缘层151可以由氮化硅层或氮氧化硅层形成，被正形地沉积在半导体衬底110的背面表面113和通孔电极170的突出部175上。
第二背面绝缘层153可以形成在第一背面绝缘层151上，以补偿第一背面绝缘层151的不均匀表面。第二背面绝缘层153可以由与第一背面绝缘层151不同的材料形成。第一背面绝缘层151和第二背面绝缘层153可以共同地构成背面钝化层150。第二背面绝缘层153可以减轻施加至背面钝化层150的压力，且因而增强设置在层叠半导体芯片之间的凸块结构的机械可靠性。即，第二背面绝缘层153可以用作绝缘缓冲层。例如，第二背面绝缘层153可以包括氧化硅层。由于第一背面绝缘层151被形成整体覆盖通孔电极170的突出部175，所以与第二背面绝缘层153用作扩散阻挡层的情况相比，第一背面绝缘层151可以更加有效地抑制铜离子的扩散。在随后的工艺中执行化学机械抛光（CMP）工艺以将背面钝化层150平坦化期间，第二背面绝缘层153可以缓冲和减轻施加至背面钝化层150的压力。因而，第二背面绝缘层153可以防止背面钝化层150在平坦化工艺期间被破坏或破裂。
参见图15，背面钝化层150可以被平坦化，以暴露出通孔电极170的突出部175的顶表面171。在平坦化工艺期间，阻挡金属层177的一部分可以被去除以暴露出突出部175的顶表面171。在平坦化工艺之后，背面钝化层150可以具有平坦的顶表面，并且突出部175的暴露出的顶表面171可以与背面钝化层150的顶表面齐平。即使在平坦化工艺之后，第一背面绝缘层151也可以与突出部175的整个侧壁接触，以有效地用作扩散阻挡层。此外，如上所述，第二背面绝缘层153可以防止背面钝化层150在平坦化工艺期间被破坏或破裂。
如参照图13、14和15所述，背面钝化层150可以被形成具有包括扩散阻挡层和绝缘缓冲层的双层结构。然而，实施例并非局限于此。例如，背面钝化层可以被形成为具有包括至少三个绝缘层的多层结构。
例如，参见图16，背面钝化层157可以被形成为具有三层结构。具体地，通孔电极170和包围通孔电极170的阻挡金属层177可以被形成穿过半导体衬底110，如参照图13所述。通孔电极170可以被形成包括从半导体衬底110的背面表面113突出的突出部175。第一背面绝缘层151可以被形成覆盖包围突出部175的阻挡金属层177的侧壁173和顶表面。第一背面绝缘层151可以由正形内衬层形成。第一背面绝缘层151可以由防止通孔电极170中的金属离子扩散出的扩散阻挡层形成。例如，第一背面绝缘层151可以由正形地沉积在半导体衬底110的背面表面113和通孔电极170的突出部175上的氮化硅层或氮氧化硅层形成。
第二背面绝缘层153可以形成在第一背面绝缘层151上，以补偿第一背面绝缘层151的不均匀表面。第二背面绝缘层153可以由与第一背面绝缘层151不同的材料形成。第二背面绝缘层153可以减轻施加至背面钝化层150的压力，并且增强设置在层叠半导体芯片之间的凸块结构的机械可靠性。即，第二背面绝缘层153可以由绝缘缓冲层形成。例如，第二背面绝缘层153可以被形成包括氧化硅层。在背面钝化层157通过随后的化学机械抛光（CMP）工艺被平坦化期间，第二背面绝缘层153可以防止背面钝化层157被破坏或破裂。
第三背面绝缘层155可以形成在第二背面绝缘层153上。第三背面绝缘层155可以包括第二扩散阻挡层。第一背面绝缘层151、第二背面绝缘层153和第三背面绝缘层155可以包括背面钝化层157。用作第二扩散阻挡层的第三背面绝缘层155可以额外地防止通孔电极170的突出部175中的铜离子经由半导体衬底110的背面表面113扩散至半导体衬底110中。第三背面绝缘层155可以由包括氮化硅层或氮氧化硅层的正形内衬层形成。在一些实施例中，用作缓冲层的第四背面绝缘层159可以额外地形成在第三背面绝缘层155上。第四背面绝缘层159可以被形成包括氧化硅层。第四背面绝缘层159也可以防止背面钝化层157在随后的平坦化工艺期间被破坏或破裂。
参见图17，背面钝化层157可以利用CMP工艺来平坦化，以暴露出突出部175的顶表面171。由氮化硅层或氮氧化硅层形成的第三背面绝缘层155可以在平坦化工艺期间用作抛光停止层。第二背面绝缘层153和第四背面绝缘层159可以防止背面钝化层157在平坦化工艺期间被破坏或破裂。
参见图18，根据实施例的叠层封装体可以采用存储卡1800的形式来提供。例如，存储卡1800可以包括诸如非易失性存储器件的存储器1810和存储器控制器1820。存储器1810和存储器控制器1820可以储存数据或者读出储存的数据。
存储器1810可以包括应用实施例的封装技术的非易失性存储器件。存储器控制器1820可以控制存储器1810，使得响应于来自主机1830的读取/写入请求而读出储存的数据、或者将数据储存。
参见图19，根据实施例的叠层封装体可以被应用于电子系统2710。电子系统2710可以包括：控制器2711、输入/输出单元2712和存储器2713。控制器2711、输入/输出单元2712和存储器2713可以经由提供路径的总线2715彼此耦接，数据经此路径而移动。
例如，控制器2711可以包括：至少一个微处理器、至少一个数字信号处理器、至少一个微控制器、能执行与这些部件相同功能的逻辑器件、或者他们的组合。控制器2711或存储器2713可以包括根据实施例的叠层封装体。输入/输出单元2712可以包括：按键、键盘、显示设备、触摸屏等。存储器2713是用于储存数据的器件。存储器2713可以储存数据和/或命令以通过控制器2711来执行等。
存储器2713可以包括诸如DRAM的易失性存储器件和/或诸如快闪存储器的非易失性存储器件。例如，快闪存储器可以被安装至诸如移动终端或笔记本计算机的信息处理系统。快闪存储器可以包括固态盘（SSD）。在这种情况下，电子系统2710可以将大量的数据稳定地储存在快闪存储系统中。
电子系统2710还可以包括接口2714，该接口2714被配置成传送数据至通信网络和从通信网络接收数据。接口2714可以是有线类型或无线类型。例如，接口2714可以包括天线、或者有线或无线收发器。
电子系统2710可以被实现为移动系统、个人计算机、工业用计算机、或执行各种功能的逻辑系统。例如，移动系统可以是以下任意一种：个人数字助理（PDA）、便携式计算机、平板电脑、移动电话、智能电话、无线电话、膝上型电脑、存储卡、数字音乐系统和信息传送/接收系统。
在电子系统2710是能执行无线通信的设备的情况下，电子系统2710可以用于诸如CDMA（码分多址）、GSM（全球移动通信系统）、NADC（北美数字蜂窝）、E-TDMA（增强-时分多址）、WCDMA（宽带码分多址）、CDMA2000、LTE（长期演进）和Wibro（无线宽带因特网）的通信系统。
已经出于说明性的目的公开了实施例，本领域的技术人员将理解的是，各种修改、添加和替换都是可以的。
通过以上实施例可以看出，本申请提供了以下的技术方案。
技术方案1.一种叠层封装体，包括：
上芯片，所述上芯片在下芯片之上；
下通孔电极，所述下通孔电极大体穿过所述下芯片，并且包括从所述下芯片的背面表面突出的突出部；
背面钝化层，所述背面钝化层覆盖所述下芯片的所述背面表面，并且暴露出所述突出部；
背面凸块，所述背面凸块与所述突出部大体耦接；以及
正面凸块，所述正面凸块与所述上芯片的芯片接触部电耦接，并且还与所述背面凸块耦接，
其中，所述背面钝化层包括：
第一绝缘层，所述第一绝缘层被提供在所述突出部的侧壁和所述下芯片的背面表面之上；以及
第二绝缘层，所述第二绝缘层被提供在所述第一绝缘层之上。
技术方案2.如技术方案1所述的叠层封装体，其中，所述第一绝缘层是扩散阻挡层。
技术方案3.如技术方案2所述的叠层封装体，其中，所述第二绝缘层是绝缘缓冲层。
技术方案4.如技术方案1所述的叠层封装体，其中，所述背面钝化层还包括被提供在所述第二绝缘层的表面之上的第三绝缘层。
技术方案5.如技术方案4所述的叠层封装体，其中，所述第三绝缘层是扩散阻挡层。
技术方案6.如技术方案1所述的叠层封装体，其中，相比于所述下芯片，所述上芯片具有较小的尺寸。
技术方案7.如技术方案1所述的叠层封装体，其中，相比于所述下芯片，所述上芯片具有较大的尺寸。
技术方案8.如技术方案1所述的叠层封装体，还包括：
模塑件，被提供在所述下芯片的侧壁和所述上芯片的侧壁之上；
外连接端子，被设置在所述下芯片的正面表面之上，并且在所述模塑件的底表面之上延伸；以及
重布线，所述重布线将所述外连接端子与所述下通孔电极电耦接，并且被设置在所述下芯片的所述正面表面之上。
技术方案9.如技术方案8所述的叠层封装体，其中，所述模塑件在所述上芯片的背面表面之上延伸。
技术方案10.如技术方案8所述的叠层封装体，其中，所述模塑件暴露出所述上芯片的背面表面。
技术方案11.如技术方案8所述的叠层封装体，其中，所述重布线在所述模塑件的所述底表面之上延伸。
技术方案12.如技术方案1所述的叠层封装体，还包括在所述下芯片与所述上芯片之间的中间芯片，
其中，所述中间芯片包括：
中间正面凸块，所述中间正面凸块与所述下芯片电耦接；
中间通孔电极，所述中间通孔电极穿过所述中间芯片，并且包括从所述中间芯片的背面表面突出的突出部；
中间背面钝化层，所述中间背面钝化层被提供在所述中间芯片的所述背面表面之上，并且暴露出所述中间通孔电极的所述突出部；以及
中间背面凸块，所述中间背面凸块与所述中间通孔电极的所述突出部耦接，以及
其中，所述中间背面钝化层包括：
第一中间绝缘层，所述第一中间绝缘层被提供在所述中间通孔电极的所述突出部的侧壁之上和所述中间芯片的所述背面表面之上；以及
第二中间绝缘层，所述第二中间绝缘层被提供在所述第一中间绝缘层之上。
技术方案13.一种叠层封装体，包括：
上芯片，被设置在下通孔电极穿过的下芯片之上；
模塑件，被提供在所述下芯片的侧壁和所述上芯片的侧壁之上；
外连接端子，被设置在所述下芯片的正面表面之上和所述模塑件的底表面之上；以及
重布线，所述重布线将所述外连接端子与所述下通孔电极电耦接，并且被设置在所述下芯片的所述正面表面之上。
技术方案14.如技术方案13所述的叠层封装体，还包括：
背面钝化层，被提供在所述下芯片的背面表面之上，并且暴露出所述下通孔电极的突出部，所述突出部从所述下芯片的所述背面表面突出；
背面凸块，所述背面凸块与所述突出部大体耦接；以及
正面凸块，所述正面凸块与所述上芯片的芯片接触部电耦接，并且还与所述背面凸块耦接，
其中，所述背面钝化层包括：
第一绝缘层，所述第一绝缘层被提供在所述突出部的侧壁之上和所述下芯片的背面表面之上；以及
第二绝缘层，所述第二绝缘层被提供在所述第一绝缘层之上。
技术方案15.如技术方案14所述的叠层封装体，其中，所述背面钝化层还包括第三绝缘层，所述第三绝缘层被提供在所述第二绝缘层的表面之上。
技术方案16.如技术方案13所述的叠层封装体，其中，相比于所述下芯片，所述上芯片具有较小的尺寸。
技术方案17.如技术方案13所述的叠层封装体，其中，相比于所述下芯片，所述上芯片具有较大的尺寸。
技术方案18.如技术方案13所述的叠层封装体，其中，所述模塑件暴露出所述上芯片的背面表面。
技术方案19.如技术方案8所述的叠层封装体，其中，所述重布线在所述模塑件的底表面之上延伸。
技术方案20.如技术方案14所述的叠层封装体，其中，所述背面钝化层的厚度大体等于所述突出部的高度。

Claims (18)

1.一种叠层封装体，包括：
上芯片，所述上芯片在下芯片之上；
下通孔电极，所述下通孔电极穿过所述下芯片，并且包括从所述下芯片的背面表面突出的突出部；
背面钝化层，所述背面钝化层覆盖所述下芯片的所述背面表面，并且暴露出所述突出部；
背面凸块，所述背面凸块与所述突出部耦接；以及
正面凸块，所述正面凸块与所述上芯片的芯片接触部电耦接，并且还与所述背面凸块耦接，
其中，所述背面钝化层包括：
第一绝缘层，所述第一绝缘层被提供在所述突出部的侧壁和所述下芯片的背面表面之上；以及
第二绝缘层，所述第二绝缘层被提供在所述第一绝缘层之上，
其中，所述第一绝缘层是扩散阻挡层。
2.如权利要求1所述的叠层封装体，其中，所述第二绝缘层是绝缘缓冲层。
3.如权利要求1所述的叠层封装体，其中，所述背面钝化层还包括被提供在所述第二绝缘层的表面之上的第三绝缘层。
4.如权利要求3所述的叠层封装体，其中，所述第三绝缘层是扩散阻挡层。
5.如权利要求1所述的叠层封装体，其中，所述上芯片具有比所述下芯片更小的尺寸。
6.如权利要求1所述的叠层封装体，其中，所述上芯片具有比所述下芯片更大的尺寸。
7.如权利要求1所述的叠层封装体，还包括：
模塑件，被提供在所述下芯片的侧壁和所述上芯片的侧壁之上；
外连接端子，被设置在所述下芯片的正面表面之上，并且在所述模塑件的底表面之上延伸；以及
重布线，所述重布线将所述外连接端子与所述下通孔电极电耦接，并且被设置在所述下芯片的所述正面表面之上。
8.如权利要求7所述的叠层封装体，其中，所述模塑件在所述上芯片的背面表面之上延伸。
9.如权利要求7所述的叠层封装体，其中，所述模塑件暴露出所述上芯片的背面表面。
10.如权利要求7所述的叠层封装体，其中，所述重布线在所述模塑件的所述底表面之上延伸。
11.如权利要求1所述的叠层封装体，还包括在所述下芯片与所述上芯片之间的中间芯片，
其中，所述中间芯片包括：
中间正面凸块，所述中间正面凸块与所述下芯片电耦接；
中间通孔电极，所述中间通孔电极穿过所述中间芯片，并且包括从所述中间芯片的背面表面突出的突出部；
中间背面钝化层，所述中间背面钝化层被提供在所述中间芯片的所述背面表面之上，并且暴露出所述中间通孔电极的所述突出部；以及
中间背面凸块，所述中间背面凸块与所述中间通孔电极的所述突出部耦接，以及
其中，所述中间背面钝化层包括：
第一中间绝缘层，所述第一中间绝缘层被提供在所述中间通孔电极的所述突出部的侧壁之上和所述中间芯片的所述背面表面之上；以及
第二中间绝缘层，所述第二中间绝缘层被提供在所述第一中间绝缘层之上。
12.一种叠层封装体，包括：
上芯片，被设置在下通孔电极穿过的下芯片之上；
模塑件，被提供在所述下芯片的侧壁和所述上芯片的侧壁之上；
外连接端子，被设置在所述下芯片的正面表面之上和所述模塑件的底表面之上；以及
重布线，所述重布线将所述外连接端子与所述下通孔电极电耦接，并且被设置在所述下芯片的所述正面表面之上，
其中，所述模塑件暴露出所述下芯片的所述正面表面，
其中，所述重布线形成在所述下芯片的暴露出的所述正面表面上并直接延伸到所述模塑件的底表面上，
其中，所述重布线用绝缘层来覆盖，
其中，所述绝缘层暴露出所述重布线的接触部，以及
其中，所述外连接端子被附接至所述重布线的所述接触部。
13.如权利要求12所述的叠层封装体，还包括：
背面钝化层，被提供在所述下芯片的背面表面之上，并且暴露出所述下通孔电极的突出部，所述突出部从所述下芯片的所述背面表面突出；
背面凸块，所述背面凸块与所述突出部大体耦接；以及
正面凸块，所述正面凸块与所述上芯片的芯片接触部电耦接，并且还与所述背面凸块耦接，
其中，所述背面钝化层包括：
第一绝缘层，所述第一绝缘层被提供在所述突出部的侧壁之上和所述下芯片的背面表面之上；以及
第二绝缘层，所述第二绝缘层被提供在所述第一绝缘层之上。
14.如权利要求13所述的叠层封装体，其中，所述背面钝化层还包括第三绝缘层，所述第三绝缘层被提供在所述第二绝缘层的表面之上。
15.如权利要求12所述的叠层封装体，其中，所述上芯片具有比所述下芯片更小的尺寸。
16.如权利要求12所述的叠层封装体，其中，所述上芯片具有比所述下芯片更大的尺寸。
17.如权利要求12所述的叠层封装体，其中，所述模塑件暴露出所述上芯片的背面表面。
18.如权利要求13所述的叠层封装体，其中，所述背面钝化层的厚度等于所述突出部的高度。
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