CN104733428A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN104733428A
CN104733428A CN201410266102.8A CN201410266102A CN104733428A CN 104733428 A CN104733428 A CN 104733428A CN 201410266102 A CN201410266102 A CN 201410266102A CN 104733428 A CN104733428 A CN 104733428A
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China
Prior art keywords
electrode
layer
projection
substrate
semiconductor device
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CN201410266102.8A
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Inventor
郑来亨
柳炫圭
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication of CN104733428A publication Critical patent/CN104733428A/zh
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Abstract

一种半导体器件包括：穿通电极，穿通衬底使得穿通电极的第一端部从衬底的第一表面突出；钝化层，覆盖衬底的第一表面和穿通电极的第一端部的侧壁；凸块，具有穿通钝化层并且与穿通电极的第一端部耦接的下部；以及下金属层，被设置在凸块和穿通电极的第一端部之间。下金属层延伸至凸块的侧壁上并且具有凹面形状。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求在2013年12月23日向韩国知识产权局提交的申请号为10-2013-0161190的韩国专利申请优先权，其全部内容通过引用合并于此。
技术领域
本公开的实施例涉及半导体器件，并且更具体地涉及具有穿通电极的半导体器件及其制造方法。
背景技术
在电子系统中利用的半导体器件可以包括各种电子电路元件，并且电子电路元件可以被集成在半导体衬底中和/或上以组成半导体器件(也被称作为半导体芯片或半导体裸片)。存储器半导体芯片可以被封装并且用于电子系统中。这些半导体封装体可以用于例如计算机、移动系统或数据储存媒介的电子系统中。
随着诸如智能手机的移动系统变得更轻且更小，在移动系统中利用的半导体封装体已在不断地缩小。另外，随着多功能移动系统的发展，大容量的半导体封装体的需求不断增加。结合这些发展，已努力将多个半导体器件放入单个封装体中以提供诸如层叠封装体的大容量半导体封装体。此外，已提出了穿通半导体芯片的穿通硅通孔(TSV)电极，以实现将在单个层叠封装体中的半导体芯片彼此电连接的互连结构。
在制造互连结构时，已作出改善TSV电极和接触TSV电极的导电材料之间的结构和电可靠性的努力。通过在TSV的铜材料和焊接材料之间的化学反应可以产生金属间化合物材料，以降低互连结构的可靠性。
发明内容
各种实施例涉及具有穿通电极的半导体器件、制造具有穿通电极的半导体器件的方法、包括具有穿通电极的半导体器件的存储卡和包括具有穿通电极的半导体器件的电子系统。
根据一些实施例，一种半导体器件包括：穿通电极，穿通衬底使得穿通电极的第一端部从衬底的第一表面突出；钝化层，覆盖衬底的第一表面和穿通电极的第一端部的侧壁；凸块，具有穿通钝化层并且与穿通电极的第一端部耦接的下部；以及下金属层，具有设置在凸块和穿通电极的第一端部之间并且覆盖凸块的侧壁的凹面形状。
根据另外的实施例，一种半导体器件包括：穿通电极，穿通第一衬底使得穿通电极的第一端部从第一衬底的第一表面突出；钝化层，覆盖第一衬底的第一表面和穿通电极的第一端部的侧壁；第一凸块，具有穿通钝化层并且与穿通电极的第一端部耦接的下部；下金属层，具有设置在第一凸块和穿通电极的第一端部之间并且覆盖第一凸块的侧壁的凹面形状；第二衬底，层叠在第一衬底上；以及第二凸块，与第二衬底耦接并且与第一凸块结合。
根据另外的实施例，一种制造半导体器件的方法包括以下步骤：在衬底的第一表面上形成钝化层以覆盖穿通衬底的穿通电极的第一端部。穿通电极的第一端部从衬底的第一表面突出。在钝化层上形成模板图案以暴露出与穿通电极的第一端部垂直重叠的钝化层的部分。刻蚀钝化层的暴露出的部分来形成暴露出穿通电极的第一端部的开口。形成接触穿通电极的第一端部的下金属层。在下金属层包围的开口中形成凸块。去除模板图案。
根据另外的实施例，一种制造半导体器件的方法包括以下步骤：形成穿通衬底的穿通电极，使得穿通电极的第一端部从衬底的第一表面突出；形成覆盖衬底的第一表面和穿通电极的第一端部的侧壁的钝化层；在穿通电极的第一端部之上形成下金属层；形成具有穿通钝化层并且经由下金属层与穿通电极的第一端部耦接的下部的凸块。下金属层延伸至凸块的侧壁上并且具有凹面形状。
根据另外的实施例，一种存储卡包括存储器和适于控制存储器的操作的存储器控制器。存储器包括：穿通电极，穿通衬底使得穿通电极的第一端部从衬底的第一表面突出；钝化层，覆盖衬底的第一表面和穿通电极的第一端部的侧壁；凸块，具有被插入至钝化层中以接触穿通电极的第一端部的下部；以及下金属层，被设置在凸块和穿通电极的第一端部之间。下金属层被形成为延伸至凸块的侧壁上并且具有凹面形状。
根据另外的实施例，一种存储卡包括存储器和适于控制存储器的操作的存储器控制器。存储器包括：穿通电极，穿通第一衬底使得穿通电极的第一端部从第一衬底的第一表面突出；钝化层，覆盖第一衬底的第一表面和穿通电极的第一端部的侧壁；第一凸块，具有被插入至钝化层中以接触穿通电极的第一端部的下部；下金属层，被设置在第一凸块和穿通电极的第一端部之间，并且包围第一凸块的侧壁以具有凹面形状；第二衬底，被层叠在第一衬底上；以及第二凸块，与第二衬底连接并且与第一凸块结合。
根据另外的实施例，一种电子系统包括存储器和经由总线与存储器耦接的控制器。存储器或控制器包括：穿通电极，穿通衬底使得穿通电极的第一端部从衬底的第一表面突出；钝化层，覆盖衬底的第一表面和穿通电极的第一端部的侧壁；凸块，具有被插入至钝化层中以接触穿通电极的第一端部的下部；以及下金属层，被设置在凸块和穿通电极的第一端部之间。下金属层被形成为延伸至凸块的侧壁上并且具有凹面形状。
根据另外的实施例，一种电子系统包括存储器和经由总线与存储器耦接的控制器。存储器或控制器包括：穿通电极，穿通第一衬底使得穿通电极的第一端部从第一衬底的第一表面突出；钝化层，覆盖第一衬底的第一表面和穿通电极的第一端部的侧壁；第一凸块，具有被插入至钝化层中以接触穿通电极的第一端部的下部；下金属层，被设置在第一凸块和穿通电极的第一端部之间并且包围第一凸块的侧壁以具有凹面形状；第二衬底，层叠在第一衬底上；以及第二凸块，与第二衬底连接并且与第一凸块结合。
附图说明
结合附图和所附详细描述，本发明构思的实施例将更加显然，其中：
图1、图2和图3是说明根据一个实施例的半导体器件的截面图；
图4和图5是说明根据另一实施例的半导体器件的截面图；
图6至图13是说明根据一些实施例制造半导体器件的方法的截面图；
图14是说明利用包括根据一个实施例的半导体器件的存储卡的电子系统的框图；以及
图15是说明包括根据一个实施例的半导体器件的电子系统的框图。
具体实施方式
将理解的是，尽管在本文中可以使用术语第一、第二、第三等来描述各种元件，但这些元件不应限制于这些术语。这些术语仅用于区分一个元件与另一个元件。因而，在不脱离本发明构思的教导的情况下，在一些实施例中的第一元件在其他的实施例中可以被称作为第二元件。
还将理解的是，当一个元件涉及在另一元件“上”、“之上”、“下”或“之下”时，其可以分别直接在另一元件“上”、“之上”、“下”或“之下”，或还可以存在中间元件。因此，在本文中使用的诸如“上”、“之上”、“下”或“之下”的术语仅出于描述特定实施例的目的，并非旨在限制本发明构思。
还将理解的是，当一个元件涉及与另一元件“连接”或“耦接”时，其可以与另一元件直接连接或耦接，或可以存在中间元件。相反，当一个元件涉及与另一元件“直接连接”或“直接耦接”时，不存在中间元件。用来描述元件或层之间的关系的其他词应以相同的方式来解释。可以通过使用裸片切割工艺将诸如晶片的半导体衬底分成多个片来获得半导体芯片。
半导体芯片可以与存储芯片或逻辑芯片相对应。存储芯片可以包括集成在半导体衬底上和/或中的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、快闪存储器电路、磁性随机存取存储器(MRAM)电路、阻变随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)。逻辑芯片可以包括集成在半导体衬底上和/或中的逻辑电路。在一些情形下，本文中使用的术语“半导体衬底”可以被理解为形成有集成电路的半导体芯片或半导体裸片。
图1是说明根据一个实施例的半导体器件的截面图。图2和图3是说明图1中所示的半导体器件的第一导电凸块631的放大图。参见图1和图2，半导体器件10可以包括半导体衬底100和大体穿通半导体衬底100的穿通电极200。穿通电极200的第一端部220从半导体衬底100的第一表面103突出。第一钝化层500可以被设置在半导体衬底100的第一表面103上，以覆盖穿通电极200的第一端部220。
第一导电凸块631的下部632可以穿通第一钝化层500，以接触穿通电极200的第一端部220。因此，穿通电极200的第一端部220的侧壁和第一导电凸块631的下部632的侧壁可以被第一钝化层500包围。下金属层610可以被设置在每个穿通电极200的第一端部220和每个第一导电凸块631的下部632之间。另外，下金属层610可以延伸以包围第一导电凸块631的下部632的侧壁634。因而，下金属层610可以具有凹面形状。
半导体衬底100可以被配置成包括穿通电极200，并且如果半导体衬底100是硅衬底，则穿通电极200可以与穿通硅通孔(TSV)电极相对应。穿通电极200可以与从半导体衬底100的第二表面101(例如，前侧表面)朝向半导体衬底100的第一表面103(例如，后侧表面)延伸的导电通孔相对应。半导体衬底100可以是硅衬底，并且可以是单独的芯片或晶片。
参见图1，半导体衬底100的第二表面101可以是具有集成电路的有源层。第一表面103可以与第二表面101相对。诸如晶体管110的集成电路的电路元件可以被设置在第二表面101上。第一电介质层120覆盖电路元件，且第二夹层电介质层130形成在第一电介质层120上。内部互连结构140可以形成在第二电介质层130中作为多层互连。晶体管110可以用作组成存储器件的存储单元的单元晶体管，或可以组成逻辑器件的逻辑电路。
内部互连结构140可以包括互连线和连接通孔。用作外部连接端子的第二导电凸块可以被设置在与内部互连结构140电连接的接触焊盘150上。第二导电凸块400可以与穿通电极200电连接以用作前凸块。第二导电凸块400可以与设置在半导体衬底100的第一表面103上的第一导电凸块631相对。包括绝缘材料和用作前侧钝化层的第二钝化层300可以被设置在夹层电介质层130上，以暴露出第二导电凸块400。第二导电凸块400可以经由第二钝化层300的开口301与接触焊盘150连接。
如图1中所示，穿通电极200可以经由内部互连结构140与第二导电凸块400电连接。然而，在一些实施例中，穿通电极200可以与第二导电凸块400直接连接，或在其之间没有任何异质结的情况下，穿通电极200和相对应的第二导电凸块400中的每个可以构成单个统一体。第二导电凸块400可以包括诸如铜材料或含铜的合金材料的金属材料。
导电附着部430可以被设置在第二导电凸块400上以改善第二导电凸块400和其他的连接端子之间的接触可靠性。导电附着部430可以包括焊接材料。焊接材料可以包括锡(Sn)。界面层(未示出)可以被另外地设置在导电附着部430和第二导电凸块400之间。界面层可以用作抑制第二导电凸块400污染或氧化的润湿层或阻挡层。界面层可以包括镍材料、金材料或它们的组合。
可以使用用于形成TSV电极的工艺技术来制造穿通电极200。穿通电极200的每个可以包括诸如铜材料或含硅的铜合金材料的金属材料。在一些实施例中，穿通电极200的每个可以包括镓(Ga)、铟(In)、锡(Sn)、银(Ag)、铋(Bi)、铅(Pb)、金(Au)、锌(Zn)、铝(Al)或包括这些元素中的至少一种的合金。穿通电极200的每个可以穿通半导体衬底100并且具有通孔形状，以及第一端部220(与穿通电极200的后侧端部相对应)可以从半导体衬底100与第二表面101相对的第一表面103突出。电极绝缘层210可以包围穿通电极200的侧壁以将穿通电极200与半导体衬底100电绝缘。电极绝缘层210可以防止穿通电极200中的铜离子扩散或迁移至半导体衬底100中。
再次参见图1，穿通电极200的第一端部220可以从半导体衬底100的第一表面103突出，以被插入至覆盖半导体衬底100的第一表面103的第一钝化层500中。第一端部220的凸出的高度可以根据衬底100上的位置而彼此不同。第二穿通电极203的第一端部220的高度H2可以比第一穿通电极201的第一端部220的高度H1更大，并且第三穿通电极205的第一端部220的高度H3可以比第一穿通电极201的第一端部220的高度H1更小。高度的差异可以由于用于形成穿通电极200的制造工艺的非均匀性。
再次参见图1和图2，第一钝化层500可以覆盖半导体衬底100的第一表面103。第一钝化层500可以具有比穿通电极200的第一端部220的任意高度更大的厚度。第一钝化层500可以包括有机材料或聚合物材料。第一钝化层500可以包括聚酰亚胺层。可替选地，第一钝化层500可以包括诸如氧化硅(SiO2)、氮化硅(Si3N4)或氮氧化硅(SiON)的无机材料。
第一钝化层500可以具有包括具有不同介电常数的多个电介质层的多层结构。第一钝化层500可以包括第一电介质层530和第二电介质层510。第二电介质层510可以覆盖半导体衬底100的第一表面103并且可以垂直地延伸至第一端部220的侧壁221上以形成保护环部511。保护环部511可以包围第一端部220的侧壁221，保护环部511可以具有圆形，正方形，矩形，或其它几何轮廓。第二电介质层510可以是保形内衬层。
第一电介质层530可以被设置在第二电介质层510上。第一电介质层530可以沉积在第二电介质层510上并且可以填充在端部220的侧壁上由第二电介质层510的部分所包围的空间。另外，第一电介质层530可以作为绝缘缓冲层以及用作提供第一钝化层500的表面平坦度的平坦化层。即，第一电介质层530可以提供第一钝化层500的大体平的上表面501。当应力被施加至第一钝化层500时，第一电介质层可以是应力缓冲层。因此，当在凸块连接结构形成期间应力被施加到第一钝化层500(参见图5)时，第一电介质层530可以防止凸块连接结构的机械特性降低。第一电介质层530可以包括氧化硅(SiO2)层。
第二电介质层510可以用作阻挡包括在穿通电极200的第一端部220中的铜离子横向扩散或横向迁移的扩散阻挡层。第二电介质层510可以包括氮化硅(Si3N4)或氮氧化硅(SiON)来有效阻挡金属离子的扩散或迁移。如果包括在穿通电极200中的铜离子被扩散至半导体衬底100的第一表面103上，则铜离子可以与半导体衬底100中的硅原子化学反应，以产生铜-硅化合物。另外，如果包括在穿通电极200中的铜离子扩散至半导体衬底100中，则铜离子可以降低组成形成在半导体衬底100中的集成电路的电路元件(例如，晶体管)的特性。
例如，铜离子可以降低晶体管的阈值电压特性或泄漏电流特性，以导致存储器件的不良刷新特性或不良待机电流特性。然而，根据本实施例，第二电介质层510可以有效阻止包括在穿通电极200中的铜离子扩散至半导体衬底100中。因此，第二电介质层510可以抑制半导体衬底100的铜污染。第一钝化层500还可以包括设置在第一电介质层530和第二电介质层510上的另外的扩散阻挡层或另外的应力缓冲层。在这种情况下，另外的扩散阻挡层可以包括氮化硅(Si3N4)或氮氧化硅(SiON)，而另外的应力缓冲层可以包括氧化硅(SiO2)。
第一电介质层530可以具有比穿通电极200的第一端部220的任意高度更大的厚度，并且第二电介质层510可以具有比穿通电极200的第一端部220的高度更小的厚度。第一电介质层530可以包围第一凸块631的下部632的侧壁634，并且第二电介质层510可以被设置在第一电介质层530和半导体衬底100的第一表面103之间，以及被设置在第一电介质层530和穿通电极200的第一端部220的侧壁221之间。
再次参见图1和图2，第一凸块631的下部632可以被嵌入在第一钝化层500中以接触穿通电极200的第一端部220。如上所述，下金属层610可以被设置在第一导电凸块631和第一端部220之间，并且可以延伸以覆盖第一导电凸块631的下部632的侧壁634。另外，如图2中所示，下金属层610可以延伸以覆盖第一导电凸块631的上部633的侧壁635。因而，下金属层610可以具有包围第一导电凸块631的每个的底表面和侧壁的凹面形状。
第一导电凸块631的每个的下部632可以与嵌入在第一钝化层500中的部分相对应，而第一导电凸块631的每个的上部633可以与从第一钝化层500的顶表面501突出的部分相对应。因而，第一导电凸块631的上部633的侧壁635可以延伸至第一钝化层500的顶表面501之上。下金属层610可以延伸至第一导电凸块631的上部633的侧壁635上以保护第一导电凸块631的上部633。
再次参见图2，下金属层610可以包括设置在第一导电凸块631之下的下凸块金属(UBM)层。当使用电镀工艺来形成第一导电凸块631时，下金属层610可以包括或用作晶种层。当第一导电凸块631使用电镀工艺由铜层形成时，下金属层610用作晶种层，其可以是钛(Ti)层、钛合金层、或钛(Ti)层和铜(Cu)层的组合层。可替选地，当第一导电凸块631使用电镀工艺由镍层形成时，下金属层610用作晶种层，其可以是钛(Ti)层、或钛(钛)层和铜(Cu)层的组合层。
参见图3，下金属层610可以包括电镀工艺中的晶种层611。下金属层610还可以包括在晶种层611和第一导电凸块631之间的扩散阻挡层613。扩散阻挡层613可以被引入来阻挡诸如铜离子的金属离子在第一导电凸块631和第一端部220之间的扩散。扩散阻挡层613可以包括具有约500埃至约2000埃的厚度的镍(Ni)层。在一些实施例中，扩散阻挡层613还可以包括诸如在镍(Ni)层上的金(Au)层的抗氧化层。可替选地，扩散阻挡层613可以包括：钯(Pd)层、钴(Co)层、铬(Cr)层、铑(RD)层、或包括这些材料中的至少两种的合金层。第一导电凸块631可以包括镍(Ni)、铜(Cu)、或镍(Ni)和铜(Cu)的组合。例如，第一导电凸块631可以包括具有约3000埃至约20000埃的厚度的镍(Ni)图案、具有约1000埃至约3000埃的厚度的铜(Cu)图案、或它们的组合。
在扩散阻挡层613包括镍(Ni)的实施例中，第一导电凸块631可以包括锡(Sn)。当晶种层611包括钛(Ti)层时，晶种层611难以防止在穿通电极200的第一端部220中的铜离子扩散至包括锡(Sn)的第一导电凸块631中。因而，包括镍(Ni)层的扩散阻挡层613可以被另外地引入以有效防止或抑制铜离子在第一导电凸块631和第一端部220之间的扩散。
图4是说明根据一个实施例的半导体器件20的截面图，以及图5是说明图4中所示的半导体器件20的凸块连接结构的放大图。参见图4和图5，半导体器件20可以包括第一半导体器件21和层叠在第一半导体器件21上的第二半导体器件23。第一半导体器件21和第二半导体器件23中的每个可以具有与参照图1、图2和图3所述的半导体器件10大体相同的配置。即，第一半导体器件21和第二半导体器件23中的每个可以包括：第一钝化层500，包围穿通衬底100的穿通电极200的第一端部220的侧壁；以及下金属层610，包围第一凸块631的底表面和侧壁。
使用导电附着部430，第一半导体器件21的第一导电凸块631可以与第二半导体器件23的第二导电凸块400结合。导电附着部430可以将第一半导体器件21的第一导电凸块631与第二半导体器件23的第二导电凸块400结合，以提供半导体器件20的机械和电凸块连接结构。
尽管在附图中未示出，但是半导体器件20可以包括三个或更多个层叠的半导体器件。另外，尽管在附图中未示出，但是半导体器件20可以被安装在诸如印刷电路板(PCB)或插板等的封装衬底上。可替选地，半导体器件20可以被嵌入在嵌入衬底上。半导体器件20可以被诸如环氧模塑化合物(EMC)的保护层(未示出)覆盖。
图6至图13是说明根据一些实施例的制造半导体器件的方法的截面图。参见图6，可以形成穿通半导体衬底100的穿通电极200。穿通电极200可以被形成为从半导体衬底100的第二表面101(即，前侧表面)朝向半导体衬底100的第三表面104(即，初始后侧表面)延伸。使用用于在晶片级形成穿通硅通孔(TSV)电极的工艺可以形成穿通电极200。电极绝缘层210可以形成在穿通电极200和半导体衬底100之间以将穿通电极200与半导体衬底100电绝缘。电极绝缘层210可以包括氧化硅材料或氮化硅材料。
在形成穿通电极200之前，组成集成电路的诸如晶体管110的电路元件可以形成在半导体衬底100的第二表面101上(与有源层的表面相对应)。可以通过沉积诸如铜(Cu)材料的导电材料来形成穿通电极200。在形成穿通电极200之前，可以形成电极绝缘层210。
在形成穿通电极200之后，夹层电介质层130和多层的内部互连结构140可以形成在半导体衬底100的第二表面101上。内部互连结构140可以包括互连线和将互连线彼此电连接的通孔插塞。接触焊盘150可以形成在夹层电介质层130与半导体衬底100相对的底表面上。第二钝化层300可以形成在夹层电介质层130的底表面上，以具有暴露出与内部互连结构140电连接的接触焊盘150的开口301。
第二导电凸块400可以形成在暴露出的接触焊盘150上以提供外部连接端子。第二导电凸块400可以用作与穿通电极200电连接的前凸块。导电附着部430可以另外地形成在第二导电凸块400上。导电附着部430的每个可以包括焊接层。焊接层可以由包括锡(Sn)材料的锡类焊接材料形成。
使用粘附剂800可以将包括第二导电凸块400的衬底与诸如载体衬底的辅助衬底900附接。辅助衬底900可以与导电附着部430附接，使得半导体衬底100的第三表面104被暴露出。可以将凹陷工艺R应用到半导体衬底100的第三表面104，以形成暴露出穿通电极200的第一端部220的第一表面103。
更详细地，可以使用粘附剂800将包括导电附着部430的半导体衬底100与辅助衬底900附接，并且可以将半导体衬底100的后侧部去除预定的厚度。可以使用干法刻蚀工艺、湿法刻蚀工艺和背面研磨工艺中的至少一种来去除半导体衬底100的后侧部。作为凹陷工艺R的结果，穿通电极200的第一端部220可以从半导体衬底100的第一表面103突出。
从半导体衬底100的第一表面103突出的第一端部220的高度可以根据半导体衬底100上的位置而彼此不同。即，当穿通电极200形成在半导体衬底100中时，由于在形成穿通孔(穿通电极位于其中)时使用的刻蚀工艺的非均匀性，所以穿通电极200的深度可以根据半导体衬底100上的位置而彼此不同。因而，第二穿通电极203的第一端部220可以具有比第一穿通电极201的第一端部220的高度H1更大的高度H2，并且第三穿通电极205的第一端部220可以具有比第一穿通电极201的第一端部220的高度H1更小的高度H3。
如果穿通电极200的第一端部220具有不同的突出高度，则在后续工艺中，当将覆盖穿通电极200的钝化层平坦化以暴露出至少第三穿通电极205的第一端部220时，可以将应力施加至第二穿通电极203的第一端部220。换言之，当第一端部220具有不均匀的高度时，暴露出第一端部220的表面的工艺将在较短的第一端部仍被掩埋的同时暴露出较高的第一端部。较高的、暴露出的第一端部220可以经历诸如来自去除工艺的横向应力的机械应力。如果将过度的应力施加至第二穿通电极203的第一端部220，则第二穿通电极203可能被损坏或破坏，这可降低在后续工艺中第二穿通电极203和与第二穿通电极203连接的第一导电凸块之间的连接。然而，本公开的实施例可以在平坦化工艺期间抑制或防止诸如第二穿通电极203的最高穿通电极200的破坏。
参见图7，第一钝化层500可以形成在半导体衬底100的第一表面103上以覆盖穿通电极200的第一端部220。可以通过顺序地层叠第二电介质层510和第一电介质层530来形成第一钝化层500。第一钝化层500可以包括有机材料层或无机材料层。第二电介质层510可以是氮化硅层或氮氧化硅层，并且可以通过将氧化硅层沉积在第二电介质层510上来形成第一电介质层530。第一电介质层530可以比第二电介质层510更厚，使得第一钝化层500覆盖第二电介质层510和第一端部220，并且第一电介质层530可以提供大体均匀的顶表面。在一些实施例中，当第一钝化层500具有不均匀的表面时，第一电介质层530可以在不暴露出穿通电极200的第一端部220的情况下被平坦化。在另一实施例中，可以省略施加至第一电介质层530的平坦化工艺。
参见图8，模板图案570可以形成在第一钝化层500上。模板图案570可以被形成为具有与穿通电极200的第一端部220对齐或垂直重叠的第一开口571。第一开口571的每个可以具有比每个第一端部220的宽度更大的宽度。模板图案570可以由相对于在其之下的第一钝化层500具有刻蚀选择性的电介质层形成。例如，可以通过将光致抗蚀剂层涂覆在第一钝化层500上并且通过使用曝光步骤和显影步骤来图案化光致抗蚀剂层来形成模板图案570。可替选地，可以通过将电介质层沉积在第一钝化层500上并且通过使用光刻工艺和刻蚀工艺来将电介质层图案化来形成模板图案570。
参见图9，可以使用模板图案570作为刻蚀掩模来刻蚀第一钝化层500，以形成至少暴露出第一端部220的顶表面的第二开口505。即，通过选择性地刻蚀第一钝化层500由模板图案570的第一开口571暴露出的部分来形成第二开口505。在第二电介质层510由相对于第一电介质层530具有刻蚀选择性的氮化硅层或氮氧化硅层来形成的实施例中，可以刻蚀第一电介质层530由第一开口571暴露出的部分以暴露出第二电介质层510的部分，并且可以去除第二电介质层510的暴露出的部分以形成第二开口505。在这个实施例中，在使用模板图案570作为刻蚀掩模来刻蚀第一电介质层530时，第二电介质层510可以用作刻蚀停止层。
当通过选择性的刻蚀工艺来形成第二开口505时，即使当第一端部220的高度H1、H2和H3彼此不同时，在不将任何显著的机械应力施加在第一端部220的情况下，所有的第一端部220可以被第二开口505暴露出。因而，可以暴露出所有的第一端部220而不具有与使用将第一钝化层500平坦化的工艺以暴露出第一端部220的相关的缺点。
参见图10，下金属层610可以形成在模板图案570上和第二开口505中。下金属层610可以覆盖穿通电极200的第一端部220由第二开口505暴露出的暴露表面。下金属层610可以由钛(Ti)、铜(Cu)、镍(Ni)或金(Au)形成。可替选地，下金属层610可以包括至少包括钛(Ti)、铜(Cu)、镍(Ni)和金(Au)中的两种的材料的组合。可以使用溅射工艺来形成下金属层610。下金属层610可以覆盖第二开口505的侧壁和模板图案570的顶表面。
参见图11，导电层630可以形成在下金属层610上以填充第二开口505。可以使用电镀工艺来形成导电层630，并且在电镀工艺期间下金属层610可以作为晶种层。当导电层630使用电镀工艺由单层铜形成时，用作晶种层的下金属层610可以是钛(Ti)层、钛合金层、或钛(Ti)层和铜(Cu)层的组合。可替选地，在导电层630使用电镀工艺由单层镍形成的实施例中，用作晶种层的下金属层610可以是钛(Ti)层、或钛(Ti)层和铜(Cu)层的组合。
在一些实施例中，下金属层610可以用作除了晶种层之外的扩散阻挡层。可以引入扩散阻挡属性以防止诸如穿通电极200的第一端部220中的铜离子扩散至导电层630。扩散阻挡层可以被形成为包括具有约500埃至约2000埃厚度的镍(Ni)层。诸如金(Au)层的抗氧化层可以另外地形成在扩散阻挡层上。
在一些实施例中，扩散阻挡层可以包括：钯(Pd)、钴(Co)、铬(Cr)、铑(Rd)、或者包括这些材料中的至少两种的合金层。导电层630可以包括：镍(Ni)层、铜(Cu)层、或镍(Ni)层和铜(Cu)层的组合层。例如，导电层630可以被形成为包括具有约3000埃至约20000埃厚度的镍(Ni)层、具有约1000埃至约3000埃厚度的铜(Cu)层、或它们的组合。
在下金属层610包括镍(Ni)层的实施例中，导电层630可以包括锡(Sn)层。当晶种层包括钛(Ti)层时，晶种层难以防止穿通电极200的第一端部220中的铜离子扩散出去。因而，可以另外地引入包括镍(Ni)层的扩散阻挡层613以有效地防止或抑制第一端部220中的铜离子扩散至包括锡(Sn)层的导电层630。
参见图12，可以将导电层630平坦化直到暴露出模板图案570的顶表面上的下金属层610。可以使用化学机械抛光(CMP)工艺来将导电层630平坦化。结果，导电层630可以被分成保留在第二开口505中的多个第一导电凸块631。可以使用湿法刻蚀工艺来选择性地去除模板图案570的顶表面上的下金属层610的部分，以暴露出模板图案570的顶表面。
在一些实施例中，在导电层630的平坦化期间，可以去除在模板图案570的顶表面上的下金属层610。因此，下金属层610可以被分成多个图案，并且每个下金属图案610可以具有覆盖每个第一导电凸块631的底表面和侧壁的凹面形状。下金属图案610的包围第一导电凸块631的下部的下部可以被第一钝化层500覆盖。因而，第一钝化层500可以防止下金属图案610的下部被刻蚀。即，第一钝化层500可以防止在第一导电凸块631之下形成底切区域。
参见图13，可以去除模板图案570以暴露出第一钝化层500的顶表面。在模板图案570是光致抗蚀剂层的实施例中，可以使用灰化工艺来去除模板图案570。
参见图14，根据实施例的半导体器件可以采用存储卡1800的形式来提供。例如，存储卡1800可以包括诸如非易失性存储器件的存储器1810和存储器控制器1820。存储器1810和存储器控制器1820可以储存数据或读取储存的数据。
存储器1810可以包括应用实施例的技术的任何一种非易失性存储器件。存储器控制器1820可以控制存储器1810，使得响应于来自主机1830的读取/写入请求而读出储存的数据或者储存数据。
参见图15，根据一个实施例的半导体器件可以被应用于电子系统2710。电子系统2710可以包括：控制器2711、输入/输出单元2712和存储器2713。控制器2711、输入/输出单元2712和存储器2713可以经由提供数据移动的路径的总线2715来彼此耦接。
例如，控制器2711可以包括：至少一个微处理器、至少一个数字信号处理器、至少一个微控制器、或能够执行与这些部件相同的功能的逻辑器件。控制器2711或存储器2713可以包括根据一个实施例的至少一个半导体器件。输入/输出单元2712可以包括键区、键盘、显示设备、触摸屏等中的至少一种。存储器2713是用于储存数据的器件。存储器2713可以储存数据和/或要被控制器2711执行的命令等。
存储器2713可以包括诸如DRAM的易失性存储器件和/或诸如快闪存储器的非易失性存储器件。例如，快闪存储器可以被安装至诸如移动终端或笔记本计算机的信息处理系统。快闪存储器可以组成固态驱动器(SSD)。在这种情况下，电子系统2710可以将大量的数据稳定地储存在快闪存储系统中。
电子系统2710还可以包括被配置成将数据发送至通信网络和从通信网络接收数据的接口2714。接口2714可以是有线类型或无线类型。例如，接口2714可以包括天线、或者有线或无线收发器。
电子系统2710可以被实现为移动系统、个人计算机、工业计算机、或执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任何一种。
在电子系统2710是能够执行无线通信的设备的情况下，电子系统2710可以用于诸如CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强-时分多址)、WCDAM(宽带码分多址)、CDMA2000、LTE(长期演进)和WiBro(无线宽带因特网)的通信系统中。
以上已经出于说明的目的公开了实施例。本领域中的技术人员将理解的是，在不脱离所附权利要求的范围和精神的情况下，可以进行各种修改、增加和删减。
通过以上实施例可以看出，本申请提供了以下的技术方案。
技术方案1.一种半导体器件，包括：
穿通电极，穿通衬底并且具有从所述衬底的第一表面突出的第一端部；
钝化层，覆盖所述穿通电极的所述第一端部的侧壁并且在所述衬底的所述第一表面之上延伸；
凸块，具有穿通所述钝化层并且与所述穿通电极的所述第一端部耦接的下部；以及
下金属层，具有凹面形状，被设置在所述凸块和所述穿通电极的所述第一端部之间并且覆盖所述凸块的侧壁。
技术方案2.如技术方案1所述的半导体器件，其中，所述凸块的上部从所述钝化层的顶表面突出。
技术方案3.如技术方案2所述的半导体器件，其中，所述下金属层覆盖所述凸块的所述上部的侧壁。
技术方案4.如技术方案1所述的半导体器件，其中，所述下金属层包括选自钛Ti、铜Cu、镍Ni和金Au的材料。
技术方案5.如技术方案4所述的半导体器件，其中，所述凸块包括选自铜Cu、镍Ni和锡Sn的材料。
技术方案6.如技术方案1所述的半导体器件，其中，所述钝化层包括：
第一电介质层，包围所述凸块的所述下部的侧壁；以及
第二电介质层，被设置在所述第一电介质层和所述衬底的所述第一表面之间，以及被设置在所述第一电介质层和所述穿通电极的所述第一端部的侧壁之间。
技术方案7.如技术方案6所述的半导体器件，
其中，所述第一电介质层具有比所述穿通电极的所述第一端部的高度更大的厚度，以及
其中，所述第二电介质层具有比所述穿通电极的所述第一端部的高度更小的厚度。
技术方案8.如技术方案6所述的半导体器件，其中，所述第二电介质层覆盖所述衬底的所述第一表面，并且垂直地延伸至所述第一端部的侧壁上以形成保护环部。
技术方案9.如技术方案6所述的半导体器件，
其中，所述第二电介质层包括氮化硅层或氮氧化硅层；以及
其中，所述第一电介质层包括氧化硅层。
技术方案10.一种半导体器件，包括：
穿通电极，穿通第一衬底使得所述穿通电极的第一端部从所述第一衬底的第一表面突出；
钝化层，覆盖所述第一衬底的所述第一表面和所述穿通电极的所述第一端部的侧壁；
第一凸块，具有穿通所述钝化层并且与所述穿通电极的所述第一端部耦接的下部；
下金属层，具有凹面形状，被设置在所述第一凸块和所述穿通电极的所述第一端部之间并且覆盖所述第一凸块的侧壁；
第二衬底，层叠在所述第一衬底上；以及
第二凸块，与所述第二衬底耦接并且与所述第一凸块结合。
技术方案11.如技术方案10所述的半导体器件，其中，所述第一凸块包括从所述钝化层的顶表面向上突出的上部。
技术方案12.如技术方案11所述的半导体器件，其中，所述下金属层覆盖所述第一凸块的所述上部的侧壁。
技术方案13.一种制造半导体器件的方法，所述方法包括以下步骤：
形成穿通衬底的穿通电极，使得所述穿通电极的第一端部从所述衬底的第一表面突出；
形成钝化层，所述钝化层覆盖所述衬底的所述第一表面和所述穿通电极的所述第一端部的侧壁；
在所述穿通电极的所述第一端部之上形成下金属层；以及
形成凸块，所述凸块具有穿通所述钝化层并且经由所述下金属层与所述穿通电极的第一端部耦接的下部；
其中，所述下金属层延伸至所述凸块的侧壁上并且具有凹面形状。
技术方案14.如技术方案13所述的方法，其中，所述凸块包括从所述钝化层的顶表面突出的上部。
技术方案15.如技术方案14所述的方法，其中，所述下金属层延伸至所述凸块的所述上部的侧壁上。
技术方案16.如技术方案13所述的方法，其中，所述下金属层包括选自钛Ti、铜Cu、镍Ni和金Au的材料。
技术方案17.如技术方案13所述的方法，其中，所述凸块包括选自铜Cu、镍Ni和锡Sn的材料。
技术方案18.如技术方案13所述的方法，其中，所述钝化层包括：第一电介质层，包围所述凸块的所述下部的侧壁；以及第二电介质层，被设置在所述第一电介质层和所述衬底的所述第一表面之间以及被设置在所述第一电介质层和所述穿通电极的所述第一端部的侧壁之间。
技术方案19.如技术方案18所述的方法，
其中，所述第一电介质层具有比所述穿通电极的所述第一端部的高度更大的厚度；以及
其中，所述第二电介质层具有比所述穿通电极的所述第一端部的高度更小的厚度。
技术方案20.如技术方案18所述的方法，其中，所述第二电介质层覆盖所述衬底的所述第一表面并且垂直地延伸至所述第一端部的所述侧壁上。

Claims (10)

1.一种半导体器件，包括：
穿通电极，穿通衬底并且具有从所述衬底的第一表面突出的第一端部；
钝化层，覆盖所述穿通电极的所述第一端部的侧壁并且在所述衬底的所述第一表面之上延伸；
凸块，具有穿通所述钝化层并且与所述穿通电极的所述第一端部耦接的下部；以及
下金属层，具有凹面形状，被设置在所述凸块和所述穿通电极的所述第一端部之间并且覆盖所述凸块的侧壁。
2.如权利要求1所述的半导体器件，其中，所述凸块的上部从所述钝化层的顶表面突出。
3.如权利要求2所述的半导体器件，其中，所述下金属层覆盖所述凸块的所述上部的侧壁。
4.如权利要求1所述的半导体器件，其中，所述下金属层包括选自钛Ti、铜Cu、镍Ni和金Au的材料。
5.如权利要求4所述的半导体器件，其中，所述凸块包括选自铜Cu、镍Ni和锡Sn的材料。
6.如权利要求1所述的半导体器件，其中，所述钝化层包括：
第一电介质层，包围所述凸块的所述下部的侧壁；以及
第二电介质层，被设置在所述第一电介质层和所述衬底的所述第一表面之间，以及被设置在所述第一电介质层和所述穿通电极的所述第一端部的侧壁之间。
7.如权利要求6所述的半导体器件，
其中，所述第一电介质层具有比所述穿通电极的所述第一端部的高度更大的厚度，以及
其中，所述第二电介质层具有比所述穿通电极的所述第一端部的高度更小的厚度。
8.如权利要求6所述的半导体器件，其中，所述第二电介质层覆盖所述衬底的所述第一表面，并且垂直地延伸至所述第一端部的侧壁上以形成保护环部。
9.一种半导体器件，包括：
穿通电极，穿通第一衬底使得所述穿通电极的第一端部从所述第一衬底的第一表面突出；
钝化层，覆盖所述第一衬底的所述第一表面和所述穿通电极的所述第一端部的侧壁；
第一凸块，具有穿通所述钝化层并且与所述穿通电极的所述第一端部耦接的下部；
下金属层，具有凹面形状，被设置在所述第一凸块和所述穿通电极的所述第一端部之间并且覆盖所述第一凸块的侧壁；
第二衬底，层叠在所述第一衬底上；以及
第二凸块，与所述第二衬底耦接并且与所述第一凸块结合。
10.一种制造半导体器件的方法，所述方法包括以下步骤：
形成穿通衬底的穿通电极，使得所述穿通电极的第一端部从所述衬底的第一表面突出；
形成钝化层，所述钝化层覆盖所述衬底的所述第一表面和所述穿通电极的所述第一端部的侧壁；
在所述穿通电极的所述第一端部之上形成下金属层；以及
形成凸块，所述凸块具有穿通所述钝化层并且经由所述下金属层与所述穿通电极的第一端部耦接的下部；
其中，所述下金属层延伸至所述凸块的侧壁上并且具有凹面形状。
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CN113555342B (zh) * 2020-04-24 2024-03-29 南亚科技股份有限公司 半导体结构与其制备方法

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