CN103021987A - 半导体芯片和半导体封装件及其制造方法 - Google Patents

半导体芯片和半导体封装件及其制造方法 Download PDF

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CN103021987A
CN103021987A CN2012103568421A CN201210356842A CN103021987A CN 103021987 A CN103021987 A CN 103021987A CN 2012103568421 A CN2012103568421 A CN 2012103568421A CN 201210356842 A CN201210356842 A CN 201210356842A CN 103021987 A CN103021987 A CN 103021987A
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layer
path
substrate
soakage
semiconductor device
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崔朱逸
朴正祐
秦正起
金炯奭
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN103021987A publication Critical patent/CN103021987A/zh
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Abstract

本发明提供了半导体芯片、半导体器件、半导体封装件及其制造方法，所述半导体器件包括衬底和穿过该衬底的通路。该通路在其第一端具有从所述衬底的第一表面延伸出来的凸出部分，并且该通路的第二端与邻近所述衬底的相对的第二表面的互连线接触。浸润层位于所述通路与所述衬底之间并且在所述通路的凸出部分上延伸。所述浸润层包括这样的材料，该材料选择成在焊球耦接到在所述通路的凸出部分上延伸的所述浸润层时提高所述浸润层与接触所述浸润层的焊球之间的粘合强度。

Description

半导体芯片和半导体封装件及其制造方法
相关申请的交叉引用
本申请要求2011年9月23日在韩国知识产权局提交的韩国专利申请No.10-2011-0096486的优先权,该韩国专利申请的全部内容通过引用的方式结合于本申请中。
技术领域
本发明思想的实施例涉及半导体芯片、包括半导体芯片的半导体封装件以及它们的制造方法。
背景技术
封装技术正在持续发展以满足小尺寸且高可靠性的半导体产品的要求。这种技术包括层叠技术，其中两个或更多个芯片或者两个或更多个封装件沿着垂直方向层叠，层叠技术已经被深入开发以满足小尺寸、高性能的电子产品的要求。
由于层叠技术的使用，例如，有可能实现容量增加的存储装置，增加后的容量可以是集成每一个半导体芯片的工艺所实现的芯片级容量的两倍或者更多倍。除了容量增加以外，通过层叠技术制造的半导体封装件还可以实现各种技术优点，例如，封装密度和/或封装面积的高效率。
同时，对于倒装芯片接合技术的需求也在增加，这是因为它能够提高层叠型半导体封装件的信号传输速度。在通过倒装芯片接合技术制造的层叠结构中，可以使用穿硅通路（through-silicon via）来在芯片之间或其封装件之间传输信号。
发明内容
一些实施例提供了包括衬底和穿过该衬底的通路的半导体器件。该通路在其第一端具有从所述衬底的第一表面延伸出来的凸出部分，并且该通路的第二端与邻近所述衬底的相对的第二表面的互连线接触。浸润层位于所述通路与所述衬底之间并且在所述通路的凸出部分上延伸。所述浸润层包括这样的材料，该材料选择成在焊球耦接到在所述通路的凸出部分上延伸的所述浸润层时提高所述浸润层与接触所述浸润层的焊球之间的粘合强度。
在一些实施例中，所述浸润层包括金（Au）、钯（Pd）和铂（Pt）中的至少一种，并且所述半导体器件还包括第一阻挡层和第二阻挡层。所述第一阻挡层夹在所述浸润层与所述衬底之间。所述第一阻挡层不在所述凸出部分的至少一部分上延伸。所述第二阻挡层夹在所述浸润层与所述通路之间。所述第一阻挡层和第二阻挡层包括选择成限制金（Au）、钯（Pd）和铂（Pt）从所述浸润层扩散的材料。
在另一些实施例中，所述第一阻挡层仅在所述凸出部分的侧壁的下部上延伸而不在所述凸出部分的侧壁的上部或所述凸出部分的上表面上延伸，使得所述焊球接触所述凸出部分的上表面上的和侧壁的上部上的浸润层。
在其它实施例中，所述半导体器件包括位于所述通路与所述第二阻挡层之间的种子层。所述种子层和所述通路中的至少一个包括铜。所述第二阻挡层包括选择成限制铜从所述种子层和所述通路中的所述至少一个扩散的材料。所述第一阻挡层和所述第二阻挡层可以包括钛、氮化钛、钽和氮化钽中的至少一种。该半导体器件还可以包括位于所述种子层和所述通路中的所述至少一个与所述互连线之间的接触阻挡层。所述接触阻挡层可以是选择成限制铜从所述种子层和所述通路中的所述至少一个扩散的材料。
在另一些实施例中，半导体封装件包括如上所述的半导体器件作为第一半导体器件。该半导体封装件还包括第二半导体器件，其层叠在所述第一半导体器件上并且具有邻近所述通路的凸出部分布置的导电部件。所述焊球位于所述浸润层与所述第二半导体器件的导电部件之间并且在所述通路与所述导电部件之间形成包括金属间化合物（IMC）层的电连接，所述金属间化合物层由所述浸润层与所述焊球之间的融合形成。所述IMC层可以延伸以覆盖上面具有所述浸润层的所述通路的凸出部分的侧壁的至少一部分。
在其它实施例中，所述第二半导体器件包括穿过该第二半导体器件的衬底并且具有凸出部分的通路。所述第二半导体器件的通路的凸出部分邻近所述第一半导体器件的通路的凸出部分布置，所述焊球和所述IMC层位于这两个凸出部分之间。
在另一些实施例中，所述第二半导体器件包括穿过该第二半导体器件的衬底并且在其第一端处具有凸出部分的通路、以及邻近该通路的相对的第二端的互连线。所述焊球位于所述第一半导体器件的凸出部分与所述第二半导体器件的互连线之间。
在又一些实施例中，一种形成半导体器件的方法，包括步骤：在所述半导体器件的衬底中形成孔；以及使用沉积工艺顺序地、共形地在所述孔中形成第一阻挡层、浸润层和第二阻挡层。在所述第二阻挡层上形成通路以填充所述孔。回蚀所述衬底的表面以限定所述通路从所述衬底的该表面延伸出来的凸出部分。回蚀所述表面的步骤包括从所述凸出部分的上表面和侧壁的一部分除去所述第一阻挡层而不除去所述浸润层。所述浸润层包括这样的材料，该材料选择成在焊球耦接到在所述通路的凸出部分上延伸的所述浸润层时提高所述浸润层与接触所述浸润层的焊球之间的粘合强度。
在其它实施例中，在形成所述孔之前在所述衬底的相对的第二表面上形成其中包含集成电路的层间电介质层。形成所述孔的步骤包括穿过所述层间电介质层形成所述孔。顺序地、共形地形成步骤包括在所述层间电介质层的上表面上形成所述第一阻挡层、所述浸润层和所述第二阻挡层。形成所述通路的步骤包括形成填充所述孔并且在所述层间电介质层的上表面上延伸的通路。在形成所述通路之后，平坦化所述层间电介质层的上表面以暴露所述层间电介质层的上表面。在所述层间电介质层的上表面上形成互连线，所述互连线将所述孔中的所述通路电耦接到所述层间电介质层中的集成电路。在所述层间电介质层的上表面上形成与所述通路对齐并且电连接到所述互连线和所述通路的、包含焊球的导电凸块。
附图说明
通过下面结合附图的简要说明将更清楚地理解示例性实施例。
图1至图16表示本申请中描述的非限制性示例性实施例。
图1是根据本发明思想的示例性实施例的半导体芯片的横截面视图；
图2是图1的部分A的放大横截面视图；
图3至图9是示出了根据一些实施例制造图2的半导体芯片的方法的横截面视图；
图10和图11是示出了根据本发明思想的示例性实施例制造半导体封装件的方法的横截面视图；
图12是图11的部分B的放大横截面视图；
图13是根据本发明思想的另一些示例性实施例的半导体芯片的放大横截面视图；
图14是根据本发明思想的另一些示例性实施例的半导体封装件的横截面视图；
图15是包括根据本发明思想的示例性实施例的半导体器件的存储卡的示意性框图；以及
图16是包括根据本发明思想的示例性实施例的半导体器件的信息处理系统的示意性框图。
具体实施方式
通过参考下面对优选实施例的详细描述以及附图，将更容易理解本发明思想的优点和特征以及实现这些优点和特征的方法。然而，本发明思想可以以多种不同形式实现，不应当理解为限于此处阐述的实施例。更确切地，提供这些实施例是为了使得本公开是彻底的且完整的，并且将向本领域技术人员充分传达本发明思想，本发明思想仅由所附权利要求限定。
本文中使用的术语仅仅是为了描述特定实施例，并不意图限制本发明。如本文中所使用的，单数形式的“一”、“一个”和“该”也意图包含复数形式，除非上下文中另外明确指出。还应当理解，如果在本说明书中使用了术语“包含”和/或“包括”，则指明存在所述的特征、整体、步骤、操作、元件和/或部件，但是不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、部件和/或它们的组。
应当理解，当一个元件或层被称为位于另一个元件或层上或“连接”或“耦接”到另一个元件或层时，所述一个元件或层可以直接位于所述另一元件或层上或直接连接或耦接到所述另一元件或层，或者可以存在插入元件或层。相反，当一个元件被称为直接在另一个元件或层“上”或“直接连接”或“直接耦接”到另一个元件或层时，不存在插入元件或层。本文中所使用的术语“和/或”包括相关列出项中的一个或多个的任何和所有组合。
应当理解，尽管在此处使用术语“第一”、“第二”等描述各种元件、部件、区域、层和/或部分，然而这些元件、部件、区域、层和/或部分不应当理解为受这些术语的限制。这些术语仅用于将一个元件、部件、区域、层或部分与另一个区域、层或部分区分开。因此，在不脱离本发明思想的教导的情况下，下面讨论的第一元件、部件、区域、层或部分可以命名为第二元件、部件、区域、层或部分。
为了便于说明书描述图中所示的一个元件或特征与另一个（或多个）元件或特征的关系，本申请中可能使用了空间相对术语，例如“在……之下”、“在……下方”、“下……”、“在……上”、“上……”等。应当理解，这些空间相对术语除了包含图中所示的取向外还意图包含在使用或工作中的器件的不同取向。例如，如果图中的器件翻转，描述为在其它元件或特征“之下”或“下方”的元件则取向为在所述其它元件或特征“上”。因此，示例性术语“在……之下”可以包含上和下的取向。器件可以以其它方式取向（旋转90度或呈其它取向），并相应地理解本文中使用的空间相对术语。
在本文中实施例是参考横截面图描述的，这些横截面图是理想化实施例（和中间结构）的示意性图示。因此，例如由于制造技术和/或容差导致的相对于这些图示中形状的变化是能预期的。因此，这些实施例不应当理解为限于本申请中所示的区域的特定形状，而是包含例如由于制造导致的形状的偏差。例如，示为矩形的注入区在其边缘通常将具有圆角特征或弯曲特征和/或注入浓度的梯度，而不是从注入区到非注入区的二元变化。类似地，通过注入形成的掩埋区域可以导致掩埋区域和穿过其发生该注入的表面之间的区域中的一些注入。因此，图中示出的区域实质上是示意性的，它们的形状并不意图图示出器件的区域的真实形状并且并不意图限制本发明思想的范围。
除非另外定义，本申请中使用的所有术语（包括技术术语和科学术语）的意思与本发明思想所属领域的普通技术人员一般理解的意思相同。还应当理解，术语（例如在常用字典中定义的那些术语）应当解释具有与它们在相关技术的和本说明书的上下文中的意思相一致的意思，不应当解释为理想的或过度形式上的意义，除非本文中明确地这样进行定义。
图1是示例性地示出根据本发明思想的示例性实施例的、具有通路中间结构的半导体芯片的横截面视图，并且图2是图1的部分A的放大横截面视图。
参考图1和图2，半导体芯片100可以包括衬底1和垂直穿过衬底1并且用作传输电信号的电路径的通路19a。衬底1可以是半导体衬底。衬底1可以包括彼此面对的第一表面1a（例如，正面）和第二表面1b（例如，背面）。第一表面1a可以是上面形成集成电路图案的有源表面。例如，可以在第一表面1a上提供包括多个晶体管的集成电路3。集成电路3可以包括存储器电路、逻辑电路或它们的任何组合。集成电路3可以被第一层间电介质5覆盖。第一层间电介质5可以由选自包括如下材料的组中的至少一种材料形成：氧化硅（例如，SiO2）、氮化硅（例如,SiN或Si3N4）以及氧氮化硅（例如,SiON）。第一层间电介质5可以形成为具有单层结构或多层结构。第一层间电介质5可以被第二层间电介质23覆盖。可以在第二层间电介质23中形成互连线21,互连线21可以布置在一个或多个水平面上。第二层间电介质23可以形成为具有单层结构或多层结构。通路19a可以穿过第一层间电介质5来与互连线21的一部分接触。可以在通路19a与互连线21之间插入扩散阻挡层以限制或者甚至阻止铜元素扩散。第二层间电介质23可以被钝化层27覆盖。可以在第二层间电介质23与钝化层27之间提供电连接到互连线21的最上面的互连线25。最上面的互连线25可以连接到穿过钝化层27的导电凸块29。导电凸块29可以包括导电焊盘29a和焊球29b。焊球29b可以由锡和银的合金（例如，SnAg）形成。钝化层27可以由氮化硅层或绝缘聚合材料等形成。
参考图1和图2，通路19a可以包括从衬底1的第二表面1b向外凸出的部分。在一些实施例中，通路19a的宽度W1可以等于或大于通路19a的凸出部分的高度H1。例如，通路19a可以形成为具有约5μm的高度H1和约7μm至8μm的宽度W1。通路19a可以形成为包括铜或钨。可以在通路19a和衬底1之间插入绝缘衬垫9a。绝缘衬垫9a可以由氧化硅层形成，例如可以在约200℃至300℃的温度条件下形成该氧化硅层。可以在绝缘衬垫9a与通路19a之间插入浸润图案（层）13a。浸润图案13a可以由抗氧化材料形成，并且例如包括选自包括金（Au）、钯（Pd）和铂（Pt）的组的至少一种材料。在一些实施例中，可以使用物理气相沉积方法形成浸润图案13a以使其具有约0.2μm或更小的厚度。例如，浸润图案13a可以具有从约0.01μm至约0.05μm的厚度。在其它实施例中，浸润图案13a可以形成为具有原子单层厚度或者从约0.001μm至约0.005μm的厚度。
可以在浸润图案13a与通路19a之间提供种子图案（层）17a。种子图案17a可以由包括铜的材料形成。可以在浸润图案13a与绝缘衬垫9a之间提供第一阻挡图案（层）11a，可以在浸润图案13a与种子图案17a之间提供第二阻挡图案（层）15a。第一阻挡图案11a和第二阻挡图案15a可以由包括选自包括钛、氮化钛、钽和氮化钽的组的至少一种的材料形成。第二阻挡图案15a可以构造成限制或者甚至阻止种子图案17a以及通路19a中可能包含的铜元素扩散。此外，第一阻挡图案11a和第二阻挡图案15a可以构造成限制或者甚至阻止浸润图案13a中可能包含的金元素扩散。第一阻挡图案11a可以夹在浸润图案13a与绝缘衬垫9a之间以用作粘合层。浸润图案13a、第二阻挡图案15a以及种子图案17a可以延伸以覆盖通路19a的凸出表面。在一些实施例中，第一阻挡图案11a和绝缘衬垫9a可以形成为在它们从衬底1的第二表面1b向外凸出时暴露浸润图案13a的侧壁。
在参考图1和图2描述的半导体芯片100中，从衬底1的第二表面1b向外凸出的通路19a的端部可以用作导电焊盘或者导电凸块。因此，无需在衬底1的第二表面1b（或背面）上形成额外的导电焊盘或者凸块。这可以简化半导体芯片100的结构并且减小半导体芯片100的厚度。此外，优点还在于有可能实现密度或容量增加的半导体器件或封装件。由于通路19a的凸出的端部被具有抗氧化属性的浸润图案13a覆盖，因此有可能在随后将浸润图案13a与焊球结合时限制或阻止在焊球与浸润图案13a之间形成自然氧化物层。这可以改善焊球的浸润属性。换而言之，焊球可以在没有自然氧化物层的情况下牢固地贴附于浸润图案13a，由此减小焊球与浸润图案13a之间的电阻。这可以使半导体芯片100或半导体器件或半导体封装件的可靠性得到改善。此外，根据本发明思想的示例性实施例，由于可以由含铜材料形成的种子图案17a和通路19a两者都被浸润图案13a和第二阻挡图案15a密封，因此有可能有效地限制或者甚至阻止铜元素扩散。因此，有可能限制或者甚至阻止半导体芯片被铜元素污染。这可以进一步提高半导体芯片100或半导体器件或半导体封装件的可靠性。
图3至图9是示出了制造图2的半导体芯片的方法的横截面视图。
首先参考图3，可以提供具有第一表面1a和第二表面1b的衬底1。可以在第一表面1a上形成集成电路3。可以在第一表面1a上沉积第一层间电介质5以覆盖集成电路3。
参考图4，可以图案化第一层间电介质5和衬底1以形成通孔7。此处，通孔7可以形成为具有与第二表面1b间隔开的下表面。
参考图5，可以在衬底1的具有通孔7的第一表面1a上顺序地且共形地形成绝缘衬垫层9、第一阻挡层11、浸润层13、第二阻挡层15和种子层17。可以使用沉积工艺形成绝缘衬垫层9、第一阻挡层11、浸润层13、第二阻挡层15和种子层17。绝缘衬垫层9可以是氧化硅层，例如，它可以在约200℃至300℃的温度条件下形成。浸润图案13a可以由抗氧化材料形成，并且例如包括选自包括金（Au）、钯（Pd）和铂（Pt）的组的至少一种材料。在一些实施例中，可以使用物理气相沉积（PVD）或原子层沉积（ALD）方法形成浸润层13。这可以提高浸润层13的厚度均匀性和粘性，即使在浸润层13很薄的情况下也是如此。
第一阻挡层11和第二阻挡层15可以由包括选自包括钛、氮化钛、钽和氮化钽的组的至少一种的材料形成。例如，种子层17可以由铜形成。例如可以使用化学气相沉积、物理气相沉积或原子层沉积方法来执行沉积工艺。在一些实施例中，可以使用一条制造线或单个设备来执行绝缘衬垫层9、第一阻挡层11、浸润层13、第二阻挡层15和种子层17的沉积工艺。这可以降低成本并改善制造周转时间。可以在种子层17上形成导电层19以填充设有绝缘衬垫层9、第一阻挡层11、浸润层13、第二阻挡层15和种子层17的通孔7。在一些实施例中，可以使用电镀工艺或者无电镀工艺形成所述导电层19。
参考图6，可以对图5所得到的结构执行平坦化工艺，以暴露第一层间电介质5的上表面，由此形成留在通孔7中的绝缘衬垫层9a、第一阻挡图案11a、浸润图案13a、第二阻挡图案15a、种子图案17a以及通路19a。
参考图7，可以在第一层间电介质5上形成互连线21和第二层间电介质23。可以在第二层间电介质23上形成最上面的互连线25以电连接到互连线21。第一层间电介质5和第二层间电介质23中的每一个都可以由氧化硅层形成。互连线21和25可以由掺杂多晶硅或含金属的导电材料形成。可以在第二层间电介质23上形成钝化层27，该钝化层27暴露最上面的互连线25的一部分。钝化层27可以由氮化硅层或绝缘聚合材料形成。可以在钝化层27上形成与最上面的互连线25接触的导电凸块29。导电凸块29可以包括导电焊盘29a和焊球29b，并且可以通过连续执行两次镀层工艺来形成导电凸块29。导电焊盘29a可以由金属材料（例如，由铜）形成。焊球29b可以包括锡银合金中的至少一种。在形成导电凸块29之后，可以在衬底1的第一表面1a上或者在钝化层27上附着支撑结构31。支撑结构31可以由硬材料（例如，玻璃基板、硅基板、金属基板、聚合物基板）或软材料（例如，弹性带）形成。在一些实施例中，由于存在支撑结构31，所以可以限制或者甚至防止衬底1的第一表面1a受损。
参考图8和图9，可以翻转设有支撑结构31的衬底1使得第二表面1b面向上。之后，可以对衬底1的整个第二表面1b执行回蚀工艺以将衬底1的背部除去第一厚度T1。在一些实施例中，可以除去绝缘衬垫9a和第一阻挡图案11a的覆盖了通路19a的底面的部分以暴露浸润图案13a。绝缘衬垫9a的顶面可以位于与第一阻挡图案11a的顶面相同的水平面或低于第一阻挡图案11a的顶面。此时，通路19a可以从衬底1的第二表面1b向外凸出。
之后，可以除去支撑结构31，如图2所示。
下文中，将参考图10和图11描述封装半导体芯片100的工艺。
图10和图11是示出了根据本发明思想的示例性实施例制造半导体封装件的方法的横截面视图，并且图12是图11的部分B的放大横截面视图。
参考图10至图12，可以在封装衬底200上层叠第一半导体芯片100a和第二半导体芯片100b。第一芯片100a和第二芯片100b可以构造成具有与图1的半导体芯片相同的技术特征。在一些实施例中，第一半导体芯片100a的浸润图案13a可以与第二半导体芯片100b的焊球29b接触。封装衬底200可以包括第一焊盘202、第二焊盘206以及连接第一焊盘202和第二焊盘206的通路204。在一些实施例中，封装衬底200可以是印刷电路板。可以执行热处理来向该层叠结构施加热，使得焊球29b可以被所施加的热熔化并与浸润图案13a融合。由于该融合的结果，可以在焊球29b与浸润图案13a之间形成金属间化合物（IMC）层129（图12）。在一些实施例中，在金属间化合物层129与焊球29b之间没有明确的界面。金属间化合物层129的一部分可以形成在浸润图案13a的上部中以部分地覆盖第二阻挡图案15a的侧壁。焊球29b可以形成为部分覆盖浸润图案13a的侧壁。由于浸润图案13a由抗氧化材料形成，因此在焊球29b和浸润图案13a二者之间没有自然氧化物层的情况下，焊球29b可以牢固地附着于浸润图案13a。换而言之，焊球29b可以牢固地附着于浸润图案13a，使得可以减小焊球29b与浸润图案13a之间的界面电阻。这可以提高半导体封装件的可靠性。接下来，如图11中所见，可以将外部焊球208附着于封装衬底200的第二焊盘206，并且可以形成模制层210以密封半导体芯片100a和100b。
在一些实施例中，第二半导体芯片100b可以不同于图1的半导体芯片100。
图13是根据本发明思想的另一些示例性实施例的最终通路结构的半导体芯片的放大横截面视图。
参考图13，可以形成穿过衬底1、第一层间电介质5和第二层间电介质23并且与重新分布线33接触的通路19a。重新分布线33可以形成为将通路19a与最上面的互连线25电连接。可以通过形成第二层间电介质23和最上面的互连线25、形成通路19a、然后形成重新分布线33来形成图13所示的半导体芯片。除此之外，可以使用与参考图2描述的制造方法基本相同的制造方法来形成图13的半导体芯片，并且该半导体芯片可以具有与图2的构造和/或结构基本相同的构造和/或结构。
图14是根据本发明思想的另一些示例性实施例的半导体封装件的横截面视图。
参考图14，可以在封装衬底200上层叠第一半导体芯片100a和第二半导体芯片100b。根据所示的这些实施例，第一芯片100a和第二芯片100b可以构造成具有与图1的半导体芯片相同的技术特征，但是可以以翻转的姿态来执行第二半导体芯片100b的层叠。即，第一半导体芯片100a的浸润图案13a可以布置成面对第二半导体芯片100b的浸润图案13a。之后，可以将内部焊球35置于第一体芯片100a和第二半导体芯片100b的浸润图案13a之间，并且可以对所得到的结构进行加热。因此，内部焊球35可以熔化并且附着于浸润图案13a。内部焊球35可以是球形焊球，或者可以使用自组装焊料接合工艺来形成内部焊球35。在自组装焊料接合工艺中，可以在第一半导体芯片100a和第二半导体芯片100b的浸润图案13a之间涂敷含有焊料颗粒和粘性树脂的混合物,并且将该混合物加热到焊料颗粒的熔点或更高的温度。在这种情况下，焊料颗粒可以流入粘性树脂、移动到浸润图案13a的表面、然后附着于浸润图案13a的表面。
图15是包括根据本发明思想的示例性实施例的半导体器件的存储卡的框图。
参考图15，存储卡1200可以包括控制主机1230与存储器装置1210之间的一般数据交换的存储器控制器1220。静态随机存取存储器（SRAM）1221可以用作处理单元（CPU）1222的操作存储器。主机接口1223可以包括连接到存储卡1200的主机1230的数据交换协议。错误校正块/电路（ECC）1224可以检测并校正从多位存储器装置1210中读取的数据中包含的错误。存储器接口1225可以与存储器装置1210对接。处理单元1222可以执行针对存储器控制器1220的数据交换的一般控制操作。可以使用包括根据本发明思想的示例性实施例的半导体芯片100和半导体封装件中的至少一个的存储器装置1210来实现存储卡1200。
图16是包括根据本发明思想的示例性实施例的半导体器件的信息处理系统的框图。
参考图16，可以使用包括根据本发明思想的示例性实施例的半导体芯片100和半导体封装件中的至少一个的存储系统1310来实现信息处理系统1300。例如，信息处理系统1300可以是移动设备和/或桌上计算机。在一些实施例中，除了存储系统1310之外，信息处理系统1300还可以包括电连接到系统总线1360的调制解调器1320、中央处理器（CPU）1330、随机存取存储器（RAM）1340以及用户界面1350。存储系统1310可以包括存储器装置1311和存储器控制器1312。在一些实施例中，存储系统1310可以与参考图15描述的存储卡1200基本相同地配置。由CPU 1330处理的和/或从外部输入的数据可以存储在存储系统1310中。在一些实施例中，存储系统1310可以用作固态盘（SSD）的一部分，在这种情况下，信息处理系统1300可以稳定且可靠地在存储系统1310中存储大量数据。尽管未示出，但是对于本领域技术人员显而易见的是，在根据本发明思想的信息处理系统1300中还可以包括例如应用程序芯片组、照相机图像传感器、照相机图像信号处理器（ISP）、输入/输出装置等。
根据本发明思想的示例性实施例，半导体芯片的凸出的通路被浸润层覆盖，因此没有必要另外形成导电焊盘和浸润层。这可以减小半导体芯片的厚度并且简化半导体芯片的结构。因此，有可能实现密度或容量增加的半导体器件或封装件。
在一些实施例中，焊球形成为与对凸出的通路进行密封的浸润层接触。这可以提高焊球与浸润层之间的粘合强度。此外，焊球和浸润层可以在它们二者之间没有自然氧化物层情况下彼此附着，这可以提高半导体封装件的可靠性。
在一些实施例中，制造半导体芯片的方法包括使用化学气相沉积方法形成绝缘衬垫，以及使用物理沉积方法形成第一阻挡层、浸润层、第二阻挡层和种子层。这可以降低成本并且改善制造周转时间。
如上所述，本发明思想的实施例可以提供可靠性高且密度高的半导体芯片及包含该半导体芯片的半导体封装件。
本发明思想的另一些实施例可以提供能够降低成本并且改善制造周转时间的半导体芯片的制造方法。
根据本发明思想的示例性实施例，半导体芯片可以包括衬底、穿过所述衬底的通路、夹在所述通路与所述衬底之间的浸润层、以及夹在所述浸润层与所述通路之间的种子层。
在一些实施例中，所述通路可以包括从所述衬底的表面向外凸出的部分。此时，所述通路的宽度可以等于或大于所述通路的凸出部分的高度。
在一些实施例中，所述芯片还可以包括夹在所述浸润层与所述衬底之间的第一阻挡层以及夹在所述浸润层与所述种子层之间的第二阻挡层。
在一些实施例中，所述浸润层、所述第二阻挡层和所述种子层可以延伸以覆盖所述通路的顶面，并且所述第一阻挡层可以形成为部分暴露所述浸润层的侧壁。
在一些实施例中，所述种子层和所述通路可以由含铜的材料形成，并且所述浸润层可以由包括选自包括金（Au）、钯（Pd）和铂（Pt）的组的至少一种的材料形成。
根据本发明思想的示例性实施例，半导体封装件可以包括封装衬底、层叠在所述封装衬底上的多个半导体芯片以及夹在所述多个半导体芯片之间以将所述多个半导体芯片彼此电连接的焊球。所述多个半导体芯片中的至少一个半导体芯片可以包括第一衬底、穿过所述第一衬底并且从所述第一衬底凸出的第一通路、夹在所述第一衬底与所述第一通路之间的第一浸润层、以及夹在所述第一浸润层与所述第一通路之间的第一种子层。此外，所述焊球和所述第一浸润层可以通过夹在二者之间的金属间化合物层彼此连接。
在一些实施例中，所述多个半导体芯片中的剩余的半导体芯片中的至少一个半导体芯片可以包括导电焊盘，并且所述焊球可以与所述金属间化合物层和所述导电焊盘都接触。
在一些实施例中，所述金属间化合物层可以延伸以覆盖所述第一种子层的侧壁的至少一部分。
在一些实施例中，所述多个半导体芯片中的剩余的半导体芯片中的至少一个半导体芯片可以包括第二衬底、穿过所述第二衬底的第二通路、夹在所述第二衬底与所述第二通路之间的第二浸润层、以及夹在所述第二浸润层与所述通路之间的第二种子层。所述焊球可以与所述第一浸润层和所述第二浸润层都接触。
在一些实施例中，制造半导体芯片的方法可以包括步骤：在衬底中形成孔；在所述孔中共形地形成浸润层；在所述浸润层上共形地形成种子层；在所述种子层上形成通路以填充所述孔；以及，然后除去所述衬底的下部以暴露所述浸润层。
在一些实施例中，可以使用沉积工艺形成所述浸润层和所述种子层，并且可以使用镀层工艺形成所述通路。
前面是本发明思想的说明，不应当将其理解为对本发明思想的限制。尽管已经描述了本发明思想的若干实施例，然而本领域技术人员容易理解，在本质上不脱离本发明思想的新颖教导和优点的情况下,可能对所述实施例进行很多修改。因此，所有这些修改都意图包含在权利要求所限定的本发明思想的范围内。因此，应当理解，前面的描述是对本发明思想的说明，而不应当理解为限于所公开的特定实施例，并且对所公开实施例的修改以及其它实施例都意图包含在所附权利要求的范围内。本发明思想由权利要求及其等效物限定。

Claims (24)

1.一种半导体器件，包括：
衬底；
穿过所述衬底的通路，该通路在其第一端具有从所述衬底的第一表面延伸出来的凸出部分，并且该通路的第二端与邻近所述衬底的相对的第二表面的互连线接触；以及
浸润层，其位于所述通路与所述衬底之间并且在所述通路的凸出部分上延伸，其中所述浸润层包括这样的材料，该材料选择成在焊球耦接到在所述通路的凸出部分上延伸的所述浸润层时提高所述浸润层与接触所述浸润层的焊球之间的粘合强度。
2.权利要求1的半导体器件，其中所述浸润层包括金、钯和铂中的至少一种，并且其中该半导体器件还包括：
夹在所述浸润层与所述衬底之间的第一阻挡层，其中所述第一阻挡层不在所述凸出部分的至少一部分上延伸；以及
夹在所述浸润层与所述通路之间的第二阻挡层，其中所述第一阻挡层和第二阻挡层包括选择成限制金、钯和铂从所述浸润层扩散的材料。
3.权利要求2的半导体器件，其中所述第一阻挡层仅在所述凸出部分的侧壁的下部上延伸而不在所述凸出部分的侧壁的上部或所述凸出部分的上表面上延伸，使得所述焊球接触所述凸出部分的上表面上的和侧壁的上部上的浸润层。
4.权利要求3的半导体器件，还包括位于所述通路与所述第二阻挡层之间的种子层，其中所述种子层和所述通路中的至少一个包括铜，并且其中所述第二阻挡层包括选择成限制铜从所述种子层和所述通路中的所述至少一个扩散的材料。
5.权利要求4的半导体器件，其中所述第一阻挡层和所述第二阻挡层包括钛、氮化钛、钽和氮化钽中的至少一种，并且其中所述半导体器件还包括位于所述种子层和所述通路中的所述至少一个与所述互连线之间的接触阻挡层，其中所述接触阻挡层包括选择成限制铜从所述种子层和所述通路中的所述至少一个扩散到所述互连线的材料。
6.一种包括权利要求1的半导体器件作为第一半导体器件的半导体封装件，该半导体封装件还包括：
第二半导体器件，其层叠在所述第一半导体器件上并且具有邻近所述通路的凸出部分布置的导电部件，并且
所述焊球位于所述浸润层与所述第二半导体器件的导电部件之间并且在所述通路与所述导电部件之间形成包括金属间化合物层的电连接，所述金属间化合物层由所述浸润层与所述焊球之间的融合形成。
7.权利要求6的半导体封装件，其中所述金属间化合物层延伸以覆盖上面具有所述浸润层的所述通路的凸出部分的侧壁的至少一部分。
8.权利要求6的半导体封装件，其中所述第二半导体器件包括穿过该第二半导体器件的衬底并且具有凸出部分的通路，并且其中所述第二半导体器件的通路的凸出部分邻近所述第一半导体器件的通路的凸出部分布置，所述焊球和所述金属间化合物层位于这两个凸出部分之间。
9.权利要求6的半导体封装件，其中所述第二半导体器件包括穿过该第二半导体器件的衬底并且在其第一端处具有凸出部分的通路、以及邻近该通路的相对的第二端的互连线，其中所述焊球位于所述第一半导体器件的凸出部分与所述第二半导体器件的互连线之间。
10.一种形成半导体器件的方法，包括如下步骤：
在所述半导体器件的衬底中形成孔；
使用沉积工艺顺序地、共形地在所述孔中形成第一阻挡层、浸润层和第二阻挡层；
在所述第二阻挡层上形成通路以填充所述孔；
回蚀所述衬底的表面以限定所述通路从所述衬底的该表面延伸出来的凸出部分，其中回蚀所述表面的步骤包括从所述凸出部分的上表面和侧壁的一部分除去所述第一阻挡层而不除去所述浸润层，其中所述浸润层包括这样的材料，该材料选择成在焊球耦接到在所述通路的凸出部分上延伸的所述浸润层时提高所述浸润层与接触所述浸润层的焊球之间的粘合强度。
11.权利要求10的方法，其中在形成所述孔之前在所述衬底的相对的第二表面上形成其中包含集成电路的层间电介质层，其中形成所述孔的步骤包括穿过所述层间电介质层形成所述孔，并且其中顺序地、共形地形成步骤包括在所述层间电介质层的上表面上形成所述第一阻挡层、所述浸润层和所述第二阻挡层，并且形成所述通路的步骤包括形成填充所述孔并且在所述层间电介质层的上表面上延伸的通路，并且其中在形成所述通路之后：
平坦化所述层间电介质层的上表面以暴露所述层间电介质层的上表面；
在所述层间电介质层的上表面上形成互连线，所述互连线将所述孔中的所述通路电耦接到所述层间电介质层中的集成电路；并且
在所述层间电介质层的上表面上形成与所述通路对齐并且电连接到所述互连线和所述通路的、包含焊球的导电凸块。
12.一种半导体芯片，包括：
衬底；
穿过所述衬底的通路；
夹在所述通路与所述衬底之间的浸润层；以及
夹在所述浸润层与所述通路之间的种子层。
13.权利要求12的半导体芯片，其中所述通路包括从所述衬底的表面向外凸出的部分。
14.权利要求13的半导体芯片，其中所述通路的宽度等于或大于所述通路的凸出部分的高度。
15.权利要求13的半导体芯片，还包括：
夹在所述浸润层与所述衬底之间的第一阻挡层；以及
夹在所述浸润层与所述种子层之间的第二阻挡层。
16.权利要求15的半导体芯片，其中所述浸润层、所述第二阻挡层和所述种子层延伸以覆盖所述通路的顶面，并且
所述第一阻挡层形成为部分暴露所述浸润层的侧壁。
17.权利要求12的半导体芯片，其中所述种子层和所述通路包括铜，并且
所述浸润层由包括选自包含金、钯和铂的组的至少一种的材料形成。
18.一种半导体封装件，包括：
封装衬底；
层叠在所述封装衬底上的多个半导体芯片；以及
夹在所述多个半导体芯片之间以将所述多个半导体芯片彼此电连接的焊球，
其中所述多个半导体芯片中的一个半导体芯片包括第一衬底、穿过所述第一衬底并且从所述第一衬底凸出的第一通路、夹在所述第一衬底与所述第一通路之间的第一浸润层、以及夹在所述第一浸润层与所述第一通路之间的第一种子层，并且
所述焊球和所述第一浸润层通过夹在二者之间的金属间化合物层彼此连接。
19.权利要求18的半导体封装件，其中所述多个半导体芯片中的另一个半导体芯片包括导电焊盘，并且所述焊球与所述金属间化合物层和所述导电焊盘都接触。
20.权利要求18的半导体封装件，其中所述金属间化合物层延伸以覆盖所述第一种子层的侧壁的至少一部分。
21.权利要求18的半导体封装件，其中所述多个半导体芯片中的所述另一个包括第二衬底、穿过所述第二衬底的第二通路、夹在所述第二衬底与所述第二通路之间的第二浸润层、以及夹在所述第二浸润层与所述通路之间的第二种子层，并且
所述焊球与所述第一浸润层和所述第二浸润层都接触。
22.一种制造半导体芯片的方法，包括步骤：
在衬底中形成孔；
在所述孔中共形地形成浸润层；
在所述浸润层上共形地形成种子层；
在所述种子层上形成通路以填充所述孔；以及
除去所述衬底的下部以暴露所述浸润层。
23.权利要求22的方法，其中使用物理气相沉积工艺或原子层沉积工艺形成所述浸润层。
24.一种制造半导体芯片的方法，包括步骤：
提供半导体芯片，该半导体芯片包括第一衬底、穿过所述第一衬底并且从所述第一衬底凸出的通路、夹在所述第一衬底与所述通路之间以覆盖凸出的通路的浸润层、以及夹在所述浸润层与所述通路之间的种子层，以及
使用夹在所述半导体芯片与第二衬底之间的焊球将所述半导体芯片安装到所述第二衬底上，
其中所述焊球和所述第一浸润层通过夹在二者之间的金属间化合物层彼此连接。
CN2012103568421A 2011-09-23 2012-09-21 半导体芯片和半导体封装件及其制造方法 Pending CN103021987A (zh)

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