CN102569208A - 半导体封装及其制造方法 - Google Patents
半导体封装及其制造方法 Download PDFInfo
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- CN102569208A CN102569208A CN201110459218XA CN201110459218A CN102569208A CN 102569208 A CN102569208 A CN 102569208A CN 201110459218X A CN201110459218X A CN 201110459218XA CN 201110459218 A CN201110459218 A CN 201110459218A CN 102569208 A CN102569208 A CN 102569208A
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Abstract
本发明提供一种半导体封装及其制造方法。在一个实施方式中,为了制造半导体封装,提供其中制造有半导体芯片的晶片。散热层形成在整个晶片上方。散热层接触半导体芯片的顶表面。之后,从晶片分割多个半导体芯片。
Description
技术领域
本公开在此涉及半导体,更具体地,涉及半导体封装及其制造方法。
背景技术
集成电路封装技术不断提高以满足对于半导体封装小型化和更高的安装可靠性的需求。特别地,提高安装工艺的效率以及提高在安装之后的机械和电可靠性已成为半导体产业的重要目标。如果处理不当,由于半导体器件操作期间的大功率消耗所引起的过量热生成会使半导体封装的可靠性退化。
发明内容
本公开提供一种具有提高的可靠性的半导体封装及其制造方法。
在一个实施方式中,一种制造半导体封装的方法包括:提供在其中制造有半导体芯片的晶片;在晶片上方形成散热层,该散热层接触半导体芯片的顶表面;以及之后,由该晶片分割(singulating)多个半导体芯片。
附图说明
包括附图以提供对本发明构思的进一步理解,并且附图结合入本说明书中且组成本说明书的一部分。附图示出本发明构思的示例性实施方式,并且与说明一起,用于解释本发明构思的原理。在图中:
图1A至图1K是剖视图,示出根据本发明构思的一实施方式的半导体封装的制造方法;
图1L是根据本发明构思的一实施方式的半导体封装的制造方法中散热层的透视图;
图1M是流程图,示出本发明构思的一实施方式的半导体封装的制造方法;
图1N是剖视图,示出本发明构思的一实施方式的半导体封装的制造方法;
图2A至图2F是剖视图,示出根据本发明构思的另一实施方式的半导体封装的制造方法;
图2G和图2H是根据本发明构思的又一实施方式的半导体封装的制造方法中散热层的透视图;
图3A至图3E是剖视图,示出根据本发明构思的再一实施方式的半导体封装的制造方法;
图4A至图4G是剖视图,示出根据本发明构思的一实施方式的半导体封装的制造方法;
图5A至图5E是剖视图,示出根据本发明构思的另一实施方式的半导体封装的制造方法;
图6A是方框图,示出具有根据本发明构思的一个或多个实施方式的半导体封装的存储卡;
图6B是方框图,示出具有根据本发明构思的一个或多个实施方式的应用的半导体封装的信息处理系统;以及
图6C是根据本发明构思的一实施方式的存储卡的方框图。
具体实施方式
在下文中,将参考附图详细描述本发明构思的示例性实施方式。
将参考附图在以下更详细地描述本发明构思的示例性实施方式。然而,本发明构思可以以不同形式实现且不应被理解为限于在此阐述的实施方式。而是,提供这些实施方式使得本公开将透彻和完整,并且将向本领域的技术人员全面传达本发明构思的范围。
在本说明书中使用的术语仅用于说明具体实施方式,且不旨在限制本发明构思。以单数形式使用的表述包括复数表述,除非在上下文中具有清楚地不同含义。在本说明书中,将理解,术语诸如“包括”或“具有”等旨在表明在该说明书中所公开的特征、数字、步骤、动作、组分、部件或其组合的存在,不旨在排除一个或多个其它特征、数字、步骤、动作、组分、部件或其组合可能存在或可能被添加的可能性。
除非另外地定义,在此使用的所有术语(包括技术和科学术语)具有与本发明构思所属的领域中的普通技术人员通常理解的相同含义。还将理解,术语(诸如在通常使用的字典中所定义的那些)应被理解为具有与在相关领域的背景中的含义一致的含义,将不被理解为理想化或过度正式的意义,除非在此清楚地如此定义。
实施方式1
图1A至图1K是剖视图,示出根据本发明构思的一实施方式的半导体封装的制造方法。图1L是根据本发明构思的另一实施方式的半导体封装的制造方法中散热层的透视图。
参考图1A,第二半导体芯片(chip)200可以层叠在第一半导体芯片100上。可以提供载体90以容易地操作(handle)第一和第二半导体芯片100和200并减少翘曲和/或损坏。作为一个示例,第一半导体芯片100可以利用插置在其间的粘合层95安装在载体90上以及第二半导体芯片200可以层叠在第一半导体芯片100上。载体90可以包括硅、金属、玻璃等等。
第一半导体芯片100和第二半导体芯片200可以是相同的芯片或不同的芯片。作为一个示例,第一半导体芯片100可以是逻辑芯片以及第二半导体芯片200可以是存储器芯片,反之亦然。
第一半导体芯片100可以是包括在晶片中没有被分割(即,处于晶片级)的半导体芯片。因此,当半导体芯片在分割之前包括在晶片中时,半导体芯片100可以被称为处于晶片级。另一方面,第二半导体芯片200可以被称为处于芯片级,即,第二半导体芯片200是分割后的半导体芯片或裸片(die)。根据一个实施方式,芯片级的多个存储芯片200可以层叠在晶片级的第一半导体芯片100上。如果第二半导体芯片200(之前已经确定为合格裸片(knowngood die,KGD))被提供在第一半导体芯片100上,则可以提高总产率。外部连接端子诸如焊球110可以提供在第一半导体芯片100上。焊球110可以将逻辑和存储芯片100和200电连接到诸如图1J的印刷电路基板80的电器件。
第一半导体芯片100和第二半导体芯片200可以通过导电凸块(bump)或导电球诸如焊球210电互连,其将参考图1B或1C随后描述。根据该应用,围绕焊球210的下填充层250可以提供在第一半导体芯片100和第二半导体芯片200之间以改善焊球210的焊接可靠性。
参考图1B,第一半导体芯片100可以以面朝上方式提供,在其中具有逻辑电路100c的有源(active)表面100f可以面朝上而相反的非有源表面100b可以面朝下。焊球110可以附接到第一半导体芯片100的非有源表面100b。第一半导体芯片100可以包括用于电连接焊球110与逻辑电路100c的穿孔102诸如穿过硅通孔(TSV)。在图1B中,穿孔102直接耦接到逻辑电路100c。然而,可以存在形成于穿孔102与逻辑电路100c之间的额外的导电图案。
在一些实施方式中,第一半导体芯片100可以包括用于电连接焊球210与逻辑电路100c的连接图案103诸如金属线、通孔(via)和/或焊盘(bondingpad)。作为另一示例,第一半导体芯片100可以以面朝下的方式提供,在其中有源表面100f面朝下且非有源表面100b面朝上。
第二半导体芯片200可以使用各种互连方法诸如倒装芯片技术电接合到第一半导体芯片100。例如,第二半导体芯片200可以层叠在第一半导体芯片100上,在其中第二半导体芯片200的具有存储电路200c的有源表面200f可以面朝下以面对第一半导体芯片100的有源表面100f且与有源表面200f相反的非有源表面200b可以面朝上。因为电连接到存储电路200c的焊球210连接到第一半导体芯片100的连接图案103,所以第一半导体芯片100和第二半导体芯片200可以彼此电连接。
参考图1C,第二半导体芯片200可以以面朝上方式层叠在第一半导体芯片100上,其中第一半导体芯片100可以面朝上或者面朝下地布置。例如,有源表面200f可以面朝上以及非有源表面200b可以面朝下。第二半导体芯片200可以包括用于电连接存储电路200c与焊球210的通孔202诸如TSV。
参考图1D,可以形成暴露第二半导体芯片200顶表面200s的平坦化模制层(molding layer)350。例如,具有足以覆盖第二半导体芯片200的厚度的模制层300(通过虚线示出)可以由封装材料诸如环氧树脂模制化合物(EMC)形成。模制层300可以使用压模(compression mold)形成以覆盖第一和第二半导体芯片100、200。然后,模制层300可以被平坦化直到暴露第二半导体芯片200的顶表面200s,从而形成可以暴露第二半导体芯片200的基本整个顶表面200s的平坦化模制层350。
在一些实施方式中,模制层300和第二半导体芯片200可以被同时研磨以暴露多个第二半导体芯片200的顶表面。
在一些实施方式中,模制层300可以被平坦化直到暴露第二半导体芯片200的顶表面200s,使得平坦化模制层350的顶表面与第二半导体芯片200的顶表面200s基本共面。
为了进一步区分本说明书中的模制层300与模制层350,模制层300被指定为树脂层。平坦化模制层350的顶表面可以在与以上所讨论的第二半导体芯片200的顶表面200s实质上相同的水平。当第二半导体芯片200如图1B所示地面朝下时,顶表面200s可以是非有源表面200b,当第二半导体芯片200如图1C所示地面朝上时,顶表面200s可以是有源表面200f。根据该实施方式,第二半导体芯片200可以接合(例如,倒装芯片接合)到第一半导体芯片100并且其顶表面200s可以是非有源表面200b。
作为另一示例,如果第二半导体芯片200面朝上,则顶表面200s可以是有源表面200f。在对树脂层300平坦化以形成平坦化模制层350的情形下,有源表面200f(图1d中未示出)可以被绝缘层保护使得有源表面200f可以不被损坏。另外,如果树脂层300被过度抛光,则有可能损坏有源表面200f。为了防止这样的损坏,顶表面200s还可以包括用于保护有源表面200f不被抛光损坏的保护层。
参考图1E,可以形成第一金属层410以及可以在第一金属层410上形成掩模图案500。第一金属层410可以形成为跨越半导体芯片200和平坦化模制层350的宽度的实质上连续的层。掩模图案500可以通过涂覆和图案化光致抗蚀剂的工艺形成为不连续层,由此产生不覆盖第二半导体芯片200但是覆盖一部分平坦化模制层350的层。掩模图案500可以与用于在晶片上的有效切片工艺的划线道600重叠。
第一金属层410可以是由材料诸如Ti、Cr、Ta、Ni、TiW、其组合或其合金形成的阻挡层,该阻挡层可以防止金属诸如Cu的扩散,其中金属的扩散使第二半导体芯片200的电性能劣化。
在形成掩模图案500之后,可以形成第二金属层420而不形成第一金属层410。在一些情形下,第二金属层420与半导体芯片200之间以及第二金属层420与平坦化模制层350之间的接合强度会变弱;导致第二金属层420分层。因为第一金属层410能减少第二金属层420从第二半导体芯片200的分层,所以第一金属层410可以在形成第二金属层420之前形成。
第一金属层410可以通过从由模版印刷工艺、丝网印刷工艺、喷墨印刷工艺、压印法、平版印刷工艺组成的组中选出的镀膜工艺、化学气相沉积、物理气相沉积、或软光刻技术形成。第一金属层410可以是薄的,典型地形成有小于大约1μm的厚度,例如,大约0.5μm至大约1μm。第一金属层410可以由用作金属(例如,Cu)扩散阻挡层的单层结构形成。作为另一示例,第一金属层410可以由多层结构形成,在该情形下,籽晶层层叠在扩散阻挡层上。参考图1F,第二金属层420可以由导电材料诸如Cu或Au形成。如果第二金属层420由Cu形成,则第二金属层420可以通过形成Cu籽晶层以及使用镀膜(plating)工艺(例如无电镀或电镀)随后形成Cu层而制成。在一些实施方式中,包括Au/Ni或Ni的层可以另外地形成在第二金属层420的顶部用于引线接合或形成球垫(ball pad)。然而,在形成再分配层的情形下,包括Au/Ni或Ni的层可以不是必需的。替代地,第二金属层420可以通过沉积Au籽晶层以及通过镀膜工艺在Au籽晶层上随后形成Au层而形成。
根据本发明构思的一实施方式,第二金属层420可以通过从由模版印刷工艺、丝网印刷工艺、喷墨印刷工艺、压印法、平版印刷工艺组成的组中选出的薄膜沉积工艺诸如物理气相沉积(PVD)技术、化学气相沉积(CVD)技术、原子层沉积(ALD)技术、或软光刻技术沉积金属而形成。第二金属层420可以形成有几微米至几十微米例如大约50μm的厚度。作为另一示例,可以在形成掩模图案500之后形成第二金属层420,而不形成第一金属层410。
第二金属层420的形状可以取决于掩模图案500的形状。例如,第二金属层420可以形成为跨越第二半导体芯片200的宽度的实质上连续的层,以及在交叠平坦化模制层350的第二金属层420的分段(segment)之间形成有间隙。第一金属层410和第二金属层420可以组成散热层401,该散热层401可直接接触半导体芯片200的顶表面200s。作为另一示例,如果不形成第一金属层410,则散热层401可以由第二金属层420形成。
在一些实施方式中,散热层401还可以直接接触平坦化模制层350的顶表面351以及第二半导体芯片200的暴露的顶表面200s。
在一些实施方式中,在剖视图中,散热层401可以沿跨越平坦化模制层350和第二半导体芯片200的顶表面200s的直线延伸。
参考图1G,掩模图案500可以通过例如灰化工艺去除。如果第一金属层410沿划线道600划分,则随后的切片工艺会变得更容易。第一金属层410的分离可以通过例如蚀刻工艺完成。作为另一示例,如果第一金属层410不太厚从而使切片工艺不难,则可以省略第一金属层410的分隔工艺。作为另一示例,不形成掩模图案500,第二金属层420可以形成为与第一金属层410实质相同的连续层。在该情形下,为了容易地执行切片工艺,第二金属层420和第一金属层410可以通过蚀刻工艺沿划线道600预先划分。因此,晶片级的散热层401可以分成彼此分开的独立散热层并安装在独立半导体封装上。
参考图1H,可以沿划线道600执行切片工艺。例如,平坦化模制层350、第一半导体芯片100、粘合层95、以及晶片级的载体90可以沿划线道600被划分以从晶片分割(singulate)第一半导体芯片,例如第一半导体芯片100。切片工艺可以通过例如切割轮或激光完成。
参考图1I,粘合层95和载体90可以从彼此拆卸或分离。因此,芯片叠层10可以形成,在该情形下,第二半导体芯片200层叠在第一半导体芯片100上以及散热层401直接接触第二半导体芯片200的通过平坦化模制层350暴露的顶表面200s。因为平坦化模制层350可以支撑芯片100和200,所以在切片工艺期间载体90可以不是必须的。因此,在形成平坦化模制层350之后,可以在去除粘合层95和载体90之后执行切片工艺。
参考图1J,芯片叠层10可以安装在封装基板80上以形成半导体封装1。封装基板80可以是印刷电路板(PCB)。一个或多个外部端子82诸如焊球可以进一步附接到封装基板80以电连接半导体封装1到任何电装置。芯片叠层10和封装基板80可以通过设置在第一半导体芯片100与封装基板80之间的一个或多个焊球110彼此电连接。下填充层85可以选择性地形成在第一半导体芯片100与封装基板80之间以围绕焊球110从而改善焊接可靠性。
根据该实施方式,因为半导体封装1包括可以直接接触第二半导体芯片200的顶表面200s的散热层401,所以从第二半导体芯片200和第一半导体芯片100产生的热能通过散热层401容易地释放。因此,由于半导体封装1的这样的特征,可以实现有效的热消散。
散热层401可具有如图1L所示的平板形状。作为另一示例,因为散热层401被进一步图案化以具有不平坦的形状,所以可以形成具有增加的表面面积的散热层402,如在图2G或图2H中所示的,随后将进一步描述。
半导体封装1可以是包括不同类型的层叠芯片100和200的系统级封装(SiP)。半导体封装1典型地需要高功率消耗,因而会出现过量热产生。然而,根据各种实施方式的原理,可以直接接触芯片100和/或200的散热层401可以提供有效的热消散或辐射。
根据本公开的一些实施方式,可以不必在第二半导体芯片200与散热层401之间形成各种材料层诸如模制层/粘合层/热界面材料(TIM)层。因此,可以在半导体封装1中充分减少由于不同材料间的热膨胀系数(CTE)的不匹配所引起的粘合性劣化。此外,半导体封装1的翘曲可以由于散热层401的硬度以及第二半导体芯片200与散热层401之间的强粘合而减少。根据一些实施方式,因为可以直接形成散热层401,所以半导体封装1的高度可以根据散热板401的厚度调整而设置,从而可以实现小型封装(small formfactor)。另外,因为半导体封装1通过晶片级工艺形成,所以与芯片级工艺相比可以降低制造成本。
半导体封装1可以以多种方式修改。作为一个示例,如图1K所示,半导体封装1a可以包括具有连接到散热层401的穿孔(或热通孔或穿过硅通孔)220的第二半导体芯片200。穿孔220可以不电连接到存储电路200c。因此,穿孔220可以是将来自存储电路200c的热传递到散热层401中的伪通孔。根据该实施方式,因为第二半导体芯片200可以接合(例如倒装芯片接合)到第一半导体芯片100,所以即使当通常发热的存储电路200c可以比散热层401更靠近第一半导体芯片100时,热也可以通过穿孔220直接且快速地传递到散热层401。
总之,如在图1M中所示,根据本发明构思的一实施方式,半导体层叠封装10可以通过以下步骤制成:步骤S101,在包括晶片级的第一半导体芯片100的晶片上方提供多个分离的第二半导体芯片200;步骤S102,形成与第二半导体芯片200的顶表面200s的至少一部分接触的散热层401。然后,在步骤S103,半导体层叠封装10可以通过从晶片分割多个第一半导体芯片100以形成多个芯片层叠而形成,在该情形下,多个分离的第二半导体芯片200层叠在被分割的第一半导体芯片100中的相应第一半导体芯片100上。在一些实施方式中,散热层401可以不包含树脂或聚合物。
在另一实施方式中,本发明构思的原理不仅可以应用于层叠型封装,而且可以应用到不是层叠型封装的半导体封装,例如,具有芯片而在其上没有层叠另一芯片的半导体封装。这样的半导体封装可以通过以下步骤形成:提供其中制造有半导体芯片的晶片;在晶片上方形成散热层,该散热层接触半导体芯片的顶表面;以及其后,从晶片分割多个半导体芯片。
在一些实施方式中,散热层401可以通过形成籽晶层然后在籽晶层上形成纳米管层而形成。
在另一实施方式中,如图1N所示,第三半导体芯片300可以覆盖第二半导体芯片200以形成半导体层叠封装20。在该情形下,第一半导体芯片100可以是逻辑器件以及第二和第三芯片200、300可以是存储器件。第二半导体芯片200和第三半导体芯片300可以通过导电凸块、焊球、或任何其它的芯片间连接器310互连。包括第一金属层410和第二金属层420的散热层401形成在第三半导体芯片300的顶表面300s上。
在该实施方式中,穿孔320形成以耦接到穿孔220并且还耦接到散热层401。根据本发明构思的一个方面,第三半导体芯片300的组件可以与第二半导体芯片200的组件相同或类似。然而,本发明构思不局限于该具体结构。例如,第一和第二半导体200、300可以通过穿孔220、320互连,但是它们也可以通过其它的互连方法诸如引线结合或任何其它的等效连接方法互连。在这方面,可以在本公开的其它实施方式中采用本公开的具体实施方式的半导体封装的一些或所有组件。此外,本公开的一些或所有组件(诸如下填充层460或平坦化模制层450)可以是可替换的或者根据应用可选择的。
第二实施方式
图2A至图2F是剖视图,示出根据本发明构思的一些实施方式的制造半导体封装的方法。图2G和图2H是根据本发明构思的一些实施方式的制造半导体封装的方法中散热层的透视图。
参考图2A,第一半导体芯片100可以利用插置在其间的粘合层95安装在载体90上以及第二半导体芯片200可以层叠在第一半导体芯片100上。围绕导电凸块或焊球210的下填充层250可以形成在第一半导体芯片100与第二半导体芯片200之间。平坦化模制层350可以通过形成并平坦化树脂层300(以虚线示出)形成。第二半导体芯片200的顶表面200s可以是如图1B所示的非有源表面200b或如图1C所示的有源表面200f。
参考图2B,可以形成第一金属层410和掩模图案502。第一金属层410可以是跨越第二半导体芯片200和平坦化模制层350的宽度的连续层。替代地,掩模图案502可以形成为不连续层以覆盖部分第二半导体芯片200和平坦化模制层350。
参考图2C,可以形成第二金属层422。例如,第二金属层422可以通过金属的无电镀或电镀形成,其形状取决于掩模图案。第二金属层422可以形成为沿第二半导体芯片200的顶表面200s的不连续层。
换句话说,第一金属层410形成为跨越第二半导体芯片200的宽度的实质连续的层,第二金属层422沿第二半导体芯片200的宽度形成有在第二金属层422的分段之间的间隙。
作为另一示例,第二金属层422可以使用如上所述的沉积技术或软光刻技术形成。可以在形成掩模图案502之后形成第二金属层422,而不形成第一金属层410。根据上述示例,包括第一金属层410和第二金属层422或仅包括第二金属层422的散热层402可以形成为晶片级。
参考图2D,在去除掩模图案502之后,可以执行切片工艺以通过使用例如切割轮或激光沿划线道600划分第一金属层410、平坦化模制层350、第一半导体芯片100、粘合层95以及载体90。在切片工艺之前,第一金属层410可以使用蚀刻工艺沿划线道600被预先划分。根据上述工艺,散热层402可以被分成独立的散热层,每个独立的散热层包括在分离的半导体封装中。
参考图2E,可以形成芯片叠层20,在该情形下分离粘合层95和载体90。在芯片叠层20中,第二半导体芯片200层叠在第一半导体芯片100上并且形成可以直接接触第二半导体芯片200的散热层402。作为另一示例,芯片叠层20可以在去除粘合层95和载体90之后通过切片工艺形成。
参考图2F,芯片叠层20可以安装在封装基板80诸如PCB上以形成半导体封装2。外部端子82可以附接到封装基板80。根据一些实施方式,下填充层85可以另外地形成在第一半导体芯片100与封装基板80之间以围绕一个或多个焊球110。第二半导体芯片200还可以包括连接到散热层402的穿孔或热通孔220,以提供从第二半导体芯片200到散热层402的热传递路径,用于有效的热消散。
根据该实施方式,散热层402可具有如图2G所示的鳍(fin)形状或如图2H所示的柱形状。具有鳍或柱形状的散热层402可相较于平面形状具有增加的表面面积,使得散热层402能更有效地消散热。
第三实施方式
图3A至图3E是剖视图,示出根据本发明构思的一实施方式的半导体封装的制造方法。
参考图3A,第一半导体芯片100可以利用插置在其间的粘合层95安装在载体90上以及第二半导体芯片200可以层叠在第一半导体芯片100上。围绕焊球210的下填充层250可以形成在第一半导体芯片100与第二半导体芯片200之间。
在一些实施方式中,下填充层250可以覆盖半导体芯片200的一部分侧壁207。
参考图3B,散热层403可以形成为围绕第二半导体芯片200的顶壁和侧壁并延伸到第一半导体芯片100的顶表面100s。因此,散热层403可以覆盖第二半导体芯片200的顶表面200s和侧壁200t以及第一半导体芯片100的顶表面100s。散热层403可以直接接触半导体芯片200的顶表面200s和/或侧壁200t。
在一些实施方式中,散热层405可以覆盖第二半导体芯片200的实质全部顶表面200s和大部分侧壁200t。第一半导体芯片100的顶表面100s可以是如图1B或1C所示的有源表面100f或非有源表面100b。散热层403可以仅包括第二金属层423或第一和第二金属层413和423。根据应用,第一金属层413可以是扩散阻挡层。
参考图3C,平坦化模制层353可以通过以下步骤形成:在第二半导体芯片200上方形成树脂层300,平坦化该树脂层300使得平坦化模制层353的顶表面358可以与散热层403的顶表面423s在实质上相同的水平。换句话说,散热层403的顶表面423s可以与平坦化模制层353的顶表面358实质上共面。因为平坦化模制层353暴露散热层403,所以散热层403可以有效地消散热。
作为另一示例,树脂层300可以保留在第二半导体芯片200上方以覆盖散热层403。在该情形下,处理步骤的数目可以减少,因此,制造成本可以降低。
在形成树脂层300之前,散热层403可以沿划线道600被划分。如果第一金属层413的厚度(例如,大约1μm)和第二金属层423的厚度(例如,大约50μm)的总和过厚,则切片工艺可能是困难的。因此,在切片工艺之前,可以执行蚀刻工艺以划分第二金属层423或第二金属层423和第一金属层413两者以使得随后的切片工艺更容易。
在形成树脂层300或平坦化模制层353之后,可以执行切片工艺以沿划线道600划分树脂层300或平坦化模制层353、第一半导体芯片100、粘合层95、以及载体90。
参考图3D,可以形成芯片叠层30,在该情形下,粘合层95和载体90分离;第二半导体芯片200层叠在第一半导体芯片100上;以及散热层403直接接触第二半导体芯片200并延伸以覆盖第一半导体芯片100的顶表面。或,在去除粘合层95和载体90之后,可以执行切片工艺以形成芯片叠层30。
参考图3E,芯片叠层30可以安装在封装基板80诸如PCB上以形成半导体封装3。一个或多个外部端子82可以进一步附接到封装基板80。下填充层85可以进一步形成在第一半导体芯片100与封装基板80之间以围绕一个或多个焊球110。
第二半导体芯片200还可以包括连接到散热层403的穿孔220。因为散热层403延伸到第一半导体芯片100的顶表面100s,所以第一半导体芯片100还可以包括连接到散热层403的穿孔120并将来自第一半导体芯片100的热传递到散热层403。换句话说,穿孔120可以耦接到一部分散热层403,在该情形下,散热层403与相应的一个第一半导体芯片100的顶表面100s接触。根据该实施方式,延伸到第一半导体芯片100的散热层403可以有效地消散来自第二半导体芯片200以及来自第一半导体芯片100的热。
第四实施方式
图4A至图4G是剖视图,示出根据本发明构思的一实施方式的半导体封装的制造方法。
参考图4A,第一半导体芯片100可以利用粘合层95接合在载体90上以及第二半导体芯片200可以利用粘合层240层叠在第一半导体芯片100上。第二半导体芯片200可以通过接合线260电连接到第一半导体芯片100。
参考图4B,可以形成暴露第二半导体芯片200的顶表面200s的平坦化模制层354。作为一个示例,树脂层300可以形成以覆盖第二半导体芯片200。然后,一部分树脂层300可以通过例如蚀刻工艺被去除,这可以形成具有凹陷区域302的平坦化模制层354,该凹陷区域302暴露第二半导体芯片200的顶表面200s的实质中心区域。平坦化模制层354可以覆盖第二半导体芯片200的顶表面200s的边缘区域,其中接合线260连接到该边缘区域。第二半导体芯片200的顶表面200s可以是有源表面。有源表面可以通过形成在其上的绝缘层被保护使得在蚀刻工艺期间有源表面不被损坏。替代地,顶表面200s可以另外地包括保护层230以覆盖第二半导体芯片200的有源表面,使得第二半导体芯片200的有源表面能在蚀刻工艺期间被保护而不受损坏。
参考图4C,第一金属层414可以通过无电镀或沉积技术形成在平坦化模制层354和第二半导体芯片200上,掩模图案504可以形成在第一金属层414上。掩模图案504可以选择性地形成在平坦化模制层354的区域上。或者,掩模图案504可以形成以如图2B所示地覆盖第二半导体芯片200的顶表面200s并覆盖部分平坦化模制层353。第一金属层414可以是扩散阻挡层。
参考图4D,第二金属层424可以形成在第一金属层424上使得可以形成晶片级的散热层404。第二金属层424可以通过利用第一金属层414作为籽晶的镀膜工艺、沉积、或印刷工艺由导电材料诸如金属形成。散热层404可具有与平坦化模制层354的轮廓相应的凹陷形状。因此,散热层404可以直接接触第二半导体芯片200的顶表面200s的中心区域,但是可以与接触接合线260的边缘区域间隔开。
参考图4E,在去除掩模图案504之后,可以沿划线道600执行切片工艺。在切片工艺之前,可以执行沿划线道600分离散热层404的工艺。散热层404可以通过分隔工艺从晶片级分离成芯片级。
参考图4F,可以形成芯片叠层40,在该情形下,粘合层和载体分离;第二半导体芯片200引线接合到第一半导体芯片100;直接接触第二半导体芯片200的散热层404被包括。作为另一示例,芯片叠层40可以在去除粘合层95和载体90之后通过执行切片工艺而形成。
参考图4G,芯片叠层40可以安装在封装基板80上以形成半导体封装4。可以进一步形成一个或多个外部端子和下填充层85。存储器芯片300还可以包括连接到散热层404的穿孔220。根据该实施方式,平坦化模制层354可以形成以覆盖接合线260但是暴露第二半导体芯片200。因此,散热层404可以形成以与第二半导体芯片200直接接触从而具有有效的热辐射。
第五实施方式
图5A至图5E是剖视图,示出根据本发明构思的一实施方式的半导体封装的制造方法。
参考图5A,第一半导体芯片100可以安装在载体90上,其间具有粘合层95,第二半导体芯片200可以层叠在第一半导体芯片100上。下填充层250可以形成在第一半导体芯片100与第二半导体芯片200之间以围绕一个或多个焊球210。在一些实施方式中,下填充层250可以覆盖半导体芯片200的侧壁207的一部分。
然后,平坦化模制层350可以通过形成并平坦化树脂层300而形成。平坦化模制层350可以暴露第二半导体芯片200的顶表面200s。在一些实施方式中,在平坦化处理步骤之后,第二半导体芯片200的实质整个顶表面200s被暴露。
然后,可以沿划线道600执行切片工艺以划分平坦化模制层350、第一半导体芯片100、粘合层95、以及载体90。
参考图5B,可以形成芯片叠层50,在该情形下粘合层95和载体90分离;第二半导体芯片200层叠在第一半导体芯片100上;第二半导体芯片200通过平坦化模制层350被暴露。作为另一示例,芯片叠层50可以在去除粘合层95和载体90之后通过切片工艺形成。
参考图5C,芯片叠层50可以安装在封装基板80上。一个或多个外部端子82可以进一步附接到封装基板80,以及下填充层85可以进一步形成在第一半导体芯片100与封装基板80之间以围绕一个或多个焊球110。
参考图5D,可以形成包括第二金属层425的散热层405。散热层405可以围绕芯片叠层50并覆盖封装基板80的顶表面80s。因此,散热层405可以与平坦化模制层350的顶表面350a和侧壁350b接触。
在形成第二金属层425之前,第一金属层415诸如扩散阻挡层可以进一步形成以形成散热层405。根据该实施方式,散热层405可以延伸到封装基板80的顶表面80s,由此有效地消散从芯片叠层50产生的热以及从封装基板80发生或从芯片叠层50传递到封装基板80的热。半导体封装5可以修改以进一步改善热辐射,如随后参考图5E所示地。
参考图5E,半导体封装5a可以形成以包括连接到散热层405并提供散热路径的穿孔84和220。作为一个示例,穿孔220可以形成在第二半导体芯片200中。因为散热层405延伸到封装基板80的顶表面80s,所以穿孔84可以另外地形成在封装基板80中。根据该实施方式,从半导体封装5a产生的热可以通过散热层405以及穿孔220和84更有效地消散。
因此,根据本发明构思的一实施方式,封装基板80可具有穿过其延伸的穿孔84。第一和第二半导体芯片100、200顺序地设置在封装基板80上方。散热层405可以与封装基板80的顶表面80s接触。穿孔84可以耦接到一部分散热层405,在该部分处散热层405与封装基板80的顶表面80s接触。
应用示例
图6A是方框图,示出具有根据本发明构思的不同实施方式的半导体封装的存储卡。图6B是方框图,示出具有根据本发明构思的不同实施方式的应用的半导体封装的信息处理系统。
参考图6A,可以应用包括在根据本发明构思的不同实施方式制造的一个或多个半导体封装中的半导体存储器1210以形成存储卡1200。例如,存储卡1200可以包括用于控制主机(未示出)与存储器1210之间的一般数据交换的存储控制器1220。SRAM 1221可以用作中央处理器(CPU)1222的操作存储器。主机接口1223可以包括连接到存储卡1200的主机的数据交换协议。误差校正码(ECC)1224可以检测并纠正从存储器1210读取的数据中的错误。存储器接口1225与存储器1210连接。CPU 1222执行一般的控制操作用于与存储控制器1220的数据交换。
参考图6B,信息处理系统1300可以包括根据本发明构思的一些实施方式的存储系统1310。信息处理系统1300可以包括在移动装置或电脑中。作为一个示例,信息处理系统1300可以包括电连接到系统总线1360的存储系统1310、调制解调器1320、CPU 1330、RAM 1340、以及用户接口1350。存储系统1310包括存储器1311和存储控制器1312并且可以与图6A的存储卡1200实质上相同。存储系统1310可以存储通过CPU 1330处理的数据或者从外部输入的数据。信息处理系统1300可以被提供作为存储卡、固态盘、照相机图像传感器、以及其它系统的应用芯片组。作为一个示例,存储系统1310可以包括半导体磁盘设备以及在该情形下,信息处理系统1300可以在存储系统1310中稳定地并可靠地存储大容量的数据。系统1300可以表现需要存储器1311的各种电子控制系统,并且例如可以在移动式电话、MP3播放器、导航装置、固态盘/驱动(SSD)、或家用电器中使用。
图6C是根据本发明构思的一实施方式的存储卡900的方框图。
参考图6C,存储卡900可以包括容纳在外壳930中的控制器910和存储器920。控制器910和存储器920可以交换电信号。例如,存储器920和控制器910可以根据控制器910的指令交换数据。因此,存储卡900可以在存储器920中存储数据或者从存储器920输出数据到外部。
例如,存储器920和/或控制器可以包括在之前描述的任何半导体封装中。存储卡900可以用作用于各种便携式器件的数据存储媒体。例如,存储卡900可以是多媒体卡(MMC)或安全数字卡(SD)。
根据本发明构思,由于形成可以直接接触半导体芯片的散热器,可以去除由于与半导体芯片的消弱的粘接性而引起的翘曲、热释放有效性的劣化、以及热膨胀常数的不匹配,从而可以改善半导体封装的热和机械寿命。此外,根据本公开的一个方面,因为散热层可以形成在半导体芯片的顶表面上而没有在其间形成粘合层,整体封装厚度可以任意地设置使得半导体封装的形状因数可以减小。此外,根据本发明构思,因为晶片级工艺(例如,以上关于图1M所述的)能被用以制造半导体封装,可以降低制造成本,并因此,可以改善整体产品的价格竞争能力。本发明构思可以被广泛地应用而不限制半导体芯片的倒装芯片接合或金属线接合法。
现在将以限制性方式说明本发明的特定实施方式。
在一个实施方式中,制造半导体层叠封装的方法可以包含:在包括第一半导体芯片的晶片上方提供多个分离的第二半导体芯片;形成接触第二半导体芯片的至少一部分顶表面的散热层;以及其后,从晶片分割多个第一半导体芯片以形成多个芯片叠层,其中多个分离的第二半导体芯片层叠在分割后的第一半导体芯片中的相应的第一半导体芯片上。
在另一实施方式中,散热层可以不包含树脂或聚合物。
在一些实施方式中,半导体层叠封装的制造方法可以另外包括:利用压模形成模制层以覆盖第一和第二半导体芯片;以及通过移除至少一部分模制层而暴露多个第二半导体芯片的顶表面。暴露多个第二半导体芯片的顶表面可以包括同时研磨模制层和第二半导体芯片。暴露半导体芯片的顶表面可以包括暴露半导体芯片的实质上整个顶表面。
在一个实施方式中,散热层可以包括第一金属层以及形成在第一金属层上的第二金属层。
在另一实施方式中,第一金属层可以包括从Ti、Cr、Ta、Ni、TiW、其组合、或其合金选出的材料,其中第二金属层包括Cu。
替代地,散热层还可以包括覆盖第二金属层的第三金属层,在该情形下,第三金属层包括Ni或Ni/Au。
在另一实施方式中,第一金属层可以形成为跨越第二半导体芯片的宽度的实质上连续的层,在该情形下第二金属层沿第二半导体芯片的宽度在第二金属层的分段之间形成有间隙。
在一个实施方式中,第二金属层可以形成为跨越第二半导体芯片的宽度的实质上连续的层,在该情形下第二金属层在覆盖模制层的第二金属层的分段之间形成有间隙。
在一些实施方式中,多个第一半导体芯片可以附接在载体上,其中粘合层插置在第一半导体芯片与载体之间。
在另一实施方式中,散热层可以利用选自镀膜、化学气相沉积、物理气相沉积、原子层沉积(ALD)或软光刻的技术形成。
在一个实施方式中,散热层的形成可以包括形成籽晶层以及在籽晶层上形成纳米管层。
在另一实施方式中,模制层可以利用压模形成以覆盖第一和第二半导体芯片并且被平坦化以暴露多个第二半导体芯片的实质上整个顶表面。散热层可以与平坦化模制层的顶表面和侧壁接触。
在一些实施方式中,提供具有穿过其延伸的穿孔的封装基板。第一和第二半导体芯片设置在封装基板上方。散热层可以与封装基板的顶表面接触,以及穿孔可以耦接到一部分散热层,在该部分散热层处散热层可以与封装基板的顶表面接触。
根据一实施方式,半导体封装的制造方法包括:提供其中制造有半导体芯片的晶片;在晶片上方形成散热层,该散热层接触半导体芯片的顶表面;以及其后,从晶片分割多个半导体芯片。在一些实施方式中,散热层可以形成而在散热层与半导体芯片之间没有粘合层。在一个实施方式中,散热层可以包括阻挡层以及形成在阻挡层上的导电层,导电层通过在阻挡层上形成籽晶层以及形成覆盖籽晶层的金属层而形成。
根据本公开的一个方面,籽晶层可以包括Cu以及金属层可以包括Cu。
根据本公开的另一方面,籽晶层可以包括Au以及金属层可以包括Au。
在一些实施方式中,一种形成半导体封装的方法,该方法包括:在相应的第一半导体芯片上方提供第二半导体芯片;以及形成接触第二半导体芯片的顶表面和侧壁的散热层。该方法还可以包括形成覆盖包括散热层的所得结构的模制层。该方法还可以包括平坦化模制层以暴露散热层的顶表面。散热层的顶表面可以与平坦化模制层的顶表面实质上共面。该方法还可以包括穿过第二半导体芯片并耦接到散热层的穿孔。散热层可以直接接触第一半导体芯片的顶表面。该方法还可以包括形成穿过相应的第一半导体芯片延伸的穿孔,在该情形下穿孔耦接到一部分散热层,在该部分散热层处散热层与相应的第一半导体芯片的顶表面接触。散热层可以直接接触第二半导体芯片的侧壁。
在一个实施方式中,一种形成半导体封装的方法,该方法包括:提供覆盖第一半导体芯片的第二半导体芯片,该第一半导体芯片具有穿过其至少一部分延伸的穿孔;形成覆盖第一和第二半导体芯片的模制层;平坦化模制层直到暴露第二半导体芯片的顶表面使得平坦化模制层的顶表面与第二半导体芯片的顶表面实质上共面;以及形成直接接触第二半导体芯片的暴露顶表面和平坦化模制层的顶表面的散热层。在剖视图中,散热层可以沿跨越平坦化模制层和第二半导体芯片的顶表面的直线延伸。第二半导体芯片可具有穿过其延伸并直接耦接到散热层的穿孔。
在一些实施方式中,半导体封装堆叠结构包括:第一半导体芯片;覆盖第一半导体芯片的第二半导体芯片;覆盖第二半导体芯片并暴露第二半导体芯片的顶表面的平坦化模制层,其中平坦化模制层的顶表面与第二半导体芯片的顶表面实质上共面;以及直接接触第二半导体芯片的暴露顶表面和平坦化模制层的散热层。封装层叠结构还可以包括覆盖第二半导体芯片的第三半导体芯片,在该情形下第一半导体芯片是逻辑器件以及第二和第三芯片是存储器件。
在一个实施方式中,半导体封装堆叠结构包括:第一半导体芯片上方的第二半导体芯片;直接接触第二半导体芯片的顶表面和侧壁的散热层;覆盖散热层并暴露散热层顶表面的平坦化模制层,在该情形下平坦化模制层的顶表面与散热层的顶表面实质上共面。
在另一实施方式中,半导体封装层叠结构包括:在第一半导体芯片上方的第二半导体芯片;覆盖暴露第二半导体芯片顶表面的第一和第二芯片的平坦化模制层,直接接触第二半导体芯片的顶表面、平坦化模制层的顶表面、以及平坦化模制层的侧壁的散热层,在该情形下平坦化模制层的顶表面与第二半导体芯片的顶表面实质上共面。半导体封装层叠结构还可以包括在封装基板中的穿孔,在该情形下散热层接触封装基板的顶表面;以及在该情形下穿过硅通孔耦接到一部分散热层,在该部分散热层处散热层接触封装基板的顶表面。
在另一实施方式中,半导体封装层叠结构包括:第一半导体芯片;覆盖第一半导体芯片的第二半导体芯片;覆盖第二半导体芯片并暴露第二半导体芯片顶表面的平坦化模制层,其中平坦化模制层的顶表面与第二半导体芯片的顶表面实质上共面;以及接触第二半导体芯片的暴露顶表面和平坦化模制层而在其间没有粘合层的散热层。
根据一个方面,散热层可以不包含树脂或聚合物。在一个实施方式中,一个系统包括:存储控制器;以及与存储控制器相邻的存储器,在该情形下存储控制器和存储器的至少一个包括:第一半导体芯片;覆盖第一半导体芯片的第二半导体芯片;覆盖第二半导体芯片并暴露第二半导体芯片的顶表面的平坦化模制层,其中平坦化模制层的顶表面与第二半导体芯片的顶表面实质上共面;以及接触第二半导体芯片的暴露顶表面和平坦化模制层而在其间没有粘合层的散热层。当前应用的实施方式还可以被应用以形成ASIC、PLD/栅阵列、DSP、Graphics和PC芯片组。此外,当前应用的实施方式可用于形成笔记本PC以及用于企业的迷你笔记本电脑、超级便携式移动PC(UMPC)、以及平板PC(Tablet PC)的存储装置。
在整个说明书中被称为“一个实施方式”或“一实施方式”指的是结合实施方式描述的特定特征、结构或者特征包括在本发明的至少一个实施方式中。因而,在整个说明书中在不同位置处出现的短语“在一个实施方式中”或“在一实施方式中”不必全部关于相同的实施方式。此外,特定的特征、结构或特性可以以任何适当的方式结合在一个或多个实施方式中。
在使用与“A、B和C等的至少一个”类似的常规(convention)的情况下,一般地,这样的表述旨在使得本领域的技术人员将理解该常规(例如,“具有A、B和C至少一个的系统”将包括但是不限于仅具有A、仅具有B、仅具有C、A和B一起、A和C一起、B和C一起、和/或A、B和C一起等的系统)。
各种操作将被描述为以最有助于理解本发明的方式执行的多个分离的步骤。然而,其中描述该步骤的顺序并不暗示该操作是取决于顺序的或者执行该步骤的顺序必须是其中存在该步骤的顺序。
以上公开的主题将被认为是示意性的而非限制性的,附加的权利要求意欲覆盖所有这样的修改、改进、以及落入本发明构思的实质精神和范围内的其它实施方式。因而,为了法律允许的最大程度,本发明构思的范围将由权利要求书及其等效物的最宽可允许解释确定,而不会受前述详细描述约束或限制。
本发明专利申请要求享有2010年12月31日提交的韩国专利申请No.10-2010-0139991的权益,其全部内容通过引用结合于此。
Claims (46)
1.一种制造半导体层叠封装的方法,该方法包括:
在包括第一半导体芯片的晶片上方提供多个分离的第二半导体芯片;
形成接触所述第二半导体芯片的所述顶表面的至少一部分的散热层;以及
其后,从所述晶片分割所述多个第一半导体芯片以形成多个芯片叠层,其中所述多个分离的第二半导体芯片层叠在所述分割后的第一半导体芯片中的相应的第一半导体芯片上。
2.根据权利要求1所述的方法,其中所述散热层不包含聚合物。
3.根据权利要求1所述的方法,该方法还包括:
利用压模形成模制层以覆盖所述第一半导体芯片和所述第二半导体芯片;以及
通过去除所述模制层的至少一部分暴露所述多个第二半导体芯片的顶表面。
4.根据权利要求3所述的方法,其中暴露所述多个第二半导体芯片的顶表面包括同时研磨所述模制层和所述第二半导体芯片。
5.根据权利要求4所述的方法,其中暴露所述半导体芯片的所述顶表面包括暴露所述半导体芯片的实质上整个顶表面。
6.根据权利要求1所述的方法,其中所述散热层包括第一金属层以及形成在所述第一金属层上的第二金属层。
7.根据权利要求6所述的方法,其中所述第一金属层包括从Ti、Cr、Ta、Ni、TiW、其组合、或其合金选出的材料,其中所述第二金属层包括Cu。
8.根据权利要求7所述的方法,其中所述散热层还包括覆盖所述第二金属层的第三金属层,其中所述第三金属层包括Ni或Ni/Au。
9.根据权利要求6所述的方法,其中所述第一金属层形成为跨越所述第二半导体芯片的宽度的实质上连续的层,其中所述第二金属层形成为沿所述第二半导体芯片的所述宽度在所述第二金属层的分段之间具有间隙。
10.根据权利要求6所述的方法,其中所述第二金属层形成为跨越所述第二半导体芯片的所述宽度的实质上连续的层,其中所述第二金属层形成为在覆盖所述模制层的所述第二金属层的分段之间具有间隙。
11.根据权利要求1所述的方法,还包括利用插置在其间的粘合层在载体上附接所述多个第一半导体芯片。
12.根据权利要求1所述的方法,其中形成所述散热层包括利用选自镀膜、化学气相沉积、物理气相沉积、原子层沉积或软光刻的技术。
13.根据权利要求1所述的方法,其中形成所述散热层包括形成籽晶层以及在该籽晶层上形成纳米管层。
14.根据权利要求1所述的方法,还包括:
利用压模形成模制层以覆盖所述第一半导体芯片和所述第二半导体芯片;以及
平坦化所述模制层以及暴露所述多个第二半导体芯片的实质上所述整个顶表面,
其中所述散热层与所述平坦化模制层的顶表面和侧壁接触。
15.根据权利要求14所述的方法,还包括提供具有穿过其延伸的穿孔的封装基板,其中所述第一半导体芯片和所述第二半导体芯片设置在所述封装基板上方,其中所述散热层与所述封装基板的顶表面接触,以及其中所述穿孔耦接到一部分所述散热层,在所述一部分所述散热层处所述散热层与所述封装基板的所述顶表面接触。
16.一种制造半导体封装的方法,所述方法包括:
提供在其中制造有半导体芯片的晶片;
在所述晶片上方形成散热层,所述散热层接触所述半导体芯片的顶表面;以及
其后,从所述晶片分割所述多个半导体芯片。
17.根据权利要求16所述的方法,其中形成所述散热层而在所述散热层与所述半导体芯片之间没有粘合层。
18.根据权利要求17所述的方法,其中所述散热层由金属层形成。
19.根据权利要求16所述的方法,其中所述散热层包括阻挡层以及形成在所述阻挡层上的导电层,导电层通过在阻挡层上形成籽晶层以及形成覆盖所述籽晶层的金属层而形成。
20.根据权利要求19所述的方法,其中所述籽晶层包括Cu以及所述金属层包括Cu。
21.根据权利要求19所述的方法,其中所述籽晶层包括Au以及所述金属层包括Au。
22.一种形成半导体封装的方法,所述方法包括:
在相应的第一半导体芯片上方提供第二半导体芯片;以及
形成接触所述第二半导体芯片的顶表面和侧壁的散热层。
23.根据权利要求22所述的方法,还包括形成覆盖包括所述散热层的所得结构的模制层。
24.根据权利要求23所述的方法,还包括:
平坦化所述模制层以暴露所述散热层的顶表面。
25.根据权利要求24所述的方法,其中所述散热层的所述顶表面与所述平坦化模制层的顶表面实质上共面。
26.根据权利要求23所述的方法,还包括形成延伸穿过所述第二半导体芯片并耦接到所述散热层的穿孔。
27.根据权利要求23所述的方法,其中所述散热层直接接触所述第一半导体芯片的所述顶表面。
28.根据权利要求27所述的方法,还包括形成穿过相应的所述第一半导体芯片而延伸的穿孔,其中所述穿孔耦接到所述散热层的一部分,在该部分散热层处所述散热层与相应的所述第一半导体芯片的所述顶表面接触。
29.根据权利要求26所述的方法,其中所述散热层直接接触所述第二半导体芯片的所述侧壁。
30.一种形成半导体封装的方法,所述方法包括:
提供覆盖第一半导体芯片的第二半导体芯片,该第一半导体芯片具有穿过其至少一部分延伸的穿孔;
形成覆盖所述第一半导体芯片和所述第二半导体芯片的模制层;
平坦化所述模制层直到暴露所述第二半导体芯片的顶表面使得所述平坦化的模制层的顶表面实质上与所述第二半导体芯片的所述顶表面共面;以及
形成直接接触所述第二半导体芯片的暴露的顶表面以及所述平坦化模制层的所述顶表面的散热层。
31.根据权利要求30所述的方法,其中,在剖视图中,所述散热层沿跨越所述平坦化模制层和所述第二半导体芯片的所述顶表面的直线延伸。
32.根据权利要求30所述的方法,其中所述第二半导体芯片具有穿过其延伸并直接耦接到所述散热层的穿孔。
33.一种半导体封装层叠结构,包括:
第一半导体芯片;
覆盖所述第一半导体芯片的第二半导体芯片;
覆盖所述第二半导体芯片并暴露所述第二半导体芯片的顶表面的平坦化模制层,其中所述平坦化模制层的顶表面实质上与所述第二半导体芯片的所述顶表面共面;以及
直接接触所述第二半导体芯片和所述平坦化模制层的暴露的顶表面的散热层。
34.根据权利要求33所述的封装层叠结构,其中,在剖视图中,所述散热层沿跨越所述平坦化模制层和所述第二半导体芯片的所述顶表面的直线延伸。
35.根据权利要求33所述的封装层叠结构,其中所述第二半导体芯片包括穿过其至少一部分延伸的穿孔,以及其中所述穿孔接触所述散热层。
36.根据权利要求33所述的封装层叠结构,还包括覆盖所述第二半导体芯片的第三半导体芯片,其中所述第一半导体芯片是逻辑器件以及所述第二半导体芯片和所述第三半导体芯片是存储器件。
37.一种半导体封装层叠结构,包括:
在第一半导体芯片上方的第二半导体芯片;
直接接触所述第二半导体芯片的顶表面和侧壁的散热层;
覆盖所述散热层并暴露所述散热层的顶表面的平坦化模制层,
其中所述平坦化模制层的顶表面与所述散热层的所述顶表面实质上共面。
38.根据权利要求37所述的半导体封装层叠结构,其中所述散热层与所述第一半导体芯片的顶表面接触。
39.根据权利要求38所述的半导体封装层叠结构,其中所述第一半导体芯片包括穿过其延伸并耦接到所述散热层的穿孔。
40.根据权利要求37所述的半导体封装层叠结构,其中所述第二半导体芯片包括穿过其至少一部分延伸的穿孔,所述穿孔耦接到所述散热层。
41.一种半导体封装层叠结构,包括:
在第一半导体芯片上方的第二半导体芯片;
覆盖暴露所述第二半导体芯片的顶表面的所述第一半导体芯片和所述第二半导体芯片的平坦化模制层;
散热层,直接接触所述第二半导体芯片的所述顶表面、所述平坦化模制层的顶表面、以及所述平坦化模制层的侧壁,
其中所述平坦化模制层的顶表面与所述第二半导体芯片的所述顶表面实质上共面。
42.根据权利要求41所述的半导体封装层叠结构,其中所述第一半导体芯片和所述第二半导体芯片顺序地安装在半导体封装基板上方。
43.根据权利要求42所述的半导体封装层叠结构,还包括在所述封装基板中的穿孔,
其中所述散热层接触所述封装基板的顶表面,以及其中所述穿过硅通孔耦接到一部分散热层,在该部分散热层处所述散热层接触所述封装基板的所述顶表面。
44.一种半导体封装层叠结构,包括:
第一半导体芯片;
覆盖所述第一半导体芯片的第二半导体芯片;
覆盖所述第二半导体芯片并暴露所述第二半导体芯片的顶表面的平坦化模制层,其中所述平坦化模制层的顶表面实质上与所述第二半导体芯片的所述顶表面共面;以及
接触所述第二半导体芯片的暴露的顶表面和所述平坦化模制层而不用粘合层的散热层。
45.根据权利要求44所述的方法,其中所述散热层不包含树脂。
46.一种系统,包括:
存储控制器;以及
与所述存储控制器相邻的存储器,
其中所述存储控制器和所述存储器的至少一个包括:
第一半导体芯片;
覆盖所述第一半导体芯片的第二半导体芯片;
覆盖所述第二半导体芯片并暴露所述第二半导体芯片的顶表面的平坦化模制层,其中所述平坦化模制层的顶表面实质上与所述第二半导体芯片的所述顶表面共面;以及
接触所述第二半导体芯片的暴露的顶表面和所述平坦化模制层而不用粘合层的散热层。
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Also Published As
Publication number | Publication date |
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KR20120077875A (ko) | 2012-07-10 |
US20120171814A1 (en) | 2012-07-05 |
CN102569208B (zh) | 2017-04-12 |
US8759147B2 (en) | 2014-06-24 |
DE102011055013A1 (de) | 2012-07-05 |
KR101715761B1 (ko) | 2017-03-14 |
US20140300004A1 (en) | 2014-10-09 |
US9059072B2 (en) | 2015-06-16 |
JP2012142572A (ja) | 2012-07-26 |
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