JP4688526B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP4688526B2 JP4688526B2 JP2005059269A JP2005059269A JP4688526B2 JP 4688526 B2 JP4688526 B2 JP 4688526B2 JP 2005059269 A JP2005059269 A JP 2005059269A JP 2005059269 A JP2005059269 A JP 2005059269A JP 4688526 B2 JP4688526 B2 JP 4688526B2
- Authority
- JP
- Japan
- Prior art keywords
- heat
- semiconductor device
- electrode
- penetrating
- laminated structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 158
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 230000017525 heat dissipation Effects 0.000 claims description 46
- 230000005855 radiation Effects 0.000 claims description 40
- 230000000149 penetrating effect Effects 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 230000035515 penetration Effects 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 2
- 238000007790 scraping Methods 0.000 claims 2
- 238000005524 ceramic coating Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 230000006378 damage Effects 0.000 description 4
- 230000001771 impaired effect Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002918 waste heat Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Description
(半導体装置の構成例)
まず、図1を参照して、この発明の第1の実施の形態の構成例につき説明する。
図1(C)に示すように、上述した構成を有する積層構造体100は、実装基板200上に搭載されて実装構造体300とされる。実装基板200は、例えば、従来公知の構成を有するプリント配線基板といった任意好適な基板である。このとき、積層構造体100は、最下面100b、及びこの最下面100bから露出する第4の半導体装置10−4の第2頂面部12b及び第2端面部20bを、実装基板200の上面上に接触させて搭載してある。
以下、図2及び図3を参照して、この発明の半導体装置10の製造方法例につき説明する。
図6を参照して、この発明の第2の実施の形態につき説明する。第2の実施の形態の積層構造体及び実装構造体は、その最上面に、これらの構造体が発する熱をより効果的に放熱させる構成をさらに具えていることを特徴としている。この放熱効果を増強するさらなる構成を除けば、この実施の形態の積層構造体及び実装構造体自体、並びにこれらを構成する半導体装置及び実装基板については、既に説明した第1の実施の形態と何ら変わるところがない。従って、既に説明した構成についての詳細な説明は、同一番号を付して省略する。
図7を参照して、この発明の第3の実施の形態につき説明する。第3の実施の形態の積層構造体及び実装構造体は、その露出面に、これらの構造体が発する熱をより効果的に放熱させる被膜をさらに具えていることを特徴としている。この放熱効果を増強する被膜を除けば、この実施の形態の積層構造体及び実装構造体自体、並びにこれらを構成する半導体装置及び実装基板については、既に説明した第2の実施の形態と何ら変わるところがない。従って、既に説明した構成についての詳細な説明は、同一番号を付して省略する。
1a:表面
1b:裏面
1c:電極パッド(配線)
1ca:表面
2、14:絶縁膜
2a:表面絶縁膜
2aa:表面
3:金属膜
10:半導体装置
10a:第1主表面
10b:第2主表面
10c:外側領域
10d:内側領域
11:ヴィアホール
11a:電気的接続用ヴィアホール
11b:放熱用ヴィアホール
12:貫通電極部
12a:第1頂面部
12b:第2頂面部
12X:貫通電極部連続体
13:溝部
13a:閉環状溝部
13b:直線状溝部
13b1:第1溝部
13b2:第2溝部
20:放熱貫通部
20a:第1端面部
20b:第2端面部
20X:放熱貫通部連続体
22:熱伝導配線
24:熱伝導用バンプ
26:電気的接続用バンプ
28:熱伝導性バンプ
30:放熱体
30a:上面
30b:下面
30c:突起部
32:放熱体放熱貫通部
32a:第1放熱体放熱貫通部
32b:第2放熱体放熱貫通部
32aa、32ba:上端部
32ab、32bb:下端部
40:塗布部
100:積層構造体
100a:最上面
100b:最下面
200:実装基板
300:実装構造体
Claims (21)
- 基板と、該基板に作りこまれた素子とを具える半導体装置であって、
第1主表面及び該第1主表面と対向する第2主表面と、
前記第1主表面から前記第2主表面に貫通し、前記第1及び第2主表面の端縁に沿って配列されている複数個の貫通電極部と、
前記第1主表面から前記第2主表面に貫通している複数個の放熱貫通部と
を具え、
複数個の前記貫通電極部は、当該半導体装置への入力又は出力信号の経路として機能し、
複数個の前記放熱貫通部は、複数個の前記貫通電極部の配列よりも内側の内側領域に配列されていて、
前記放熱貫通部は、前記素子と前記貫通電極部の間に設けられていることを特徴とする半導体装置。 - 複数個の前記放熱貫通部は、前記貫通電極部の配列に沿って、配列されていることを特徴とする請求項1に記載の半導体装置。
- 前記貫通電極部及び前記放熱貫通部を、互いに接続する熱伝導配線をさらに具えていることを特徴とする請求項1又は2に記載の半導体装置。
- 前記熱伝導配線は、前記貫通電極部及び前記放熱貫通部を、互いに1対1の対応関係で接続していることを特徴とする請求項3に記載の半導体装置。
- 前記貫通電極部及び放熱貫通部は、銅又は銅合金により形成されていることを特徴とする請求項1〜4のいずれか一項に記載の半導体装置。
- 前記第1及び第2主表面から露出する前記貫通電極部の第1頂面部及び第2頂面部のいずれか一方又は両方上に設けられている電気的接続用バンプと、
前記第1及び第2主表面から露出する前記放熱貫通部の第1端面部及び第2端面部のいずれか一方又は両方上に設けられている熱伝導用バンプと
をさらに具えていることを特徴とする請求項1〜5のいずれか一項に記載の半導体装置。 - 基板と、該基板に作りこまれた素子とを具える半導体装置であって、第1主表面及び該第1主表面と対向する第2主表面、前記第1主表面から前記第2主表面に貫通し、前記第1及び第2主表面の端縁に沿って複数が配列されている貫通電極部、及び前記第1主表面から前記第2主表面に貫通している複数個の放熱貫通部を具えている当該半導体装置を複数個含む積層構造体において、
前記放熱貫通部は、前記素子と前記貫通電極部の間に設けられていて、
複数個の前記半導体装置同士は、前記第1及び第2主表面から露出する前記放熱貫通部同士を互いに接続し、前記積層構造体の最上面から最下面に連続する一続きの放熱貫通部連続体を形成して積層され、
複数個の前記貫通電極部は、前記半導体装置への入力又は出力信号の経路として機能し、
前記放熱貫通部連続体は、前記半導体装置の前記貫通電極部が配列されている領域よりも内側の領域に設けられていることを特徴とする積層構造体。 - 前記放熱貫通部連続体は、前記貫通電極部の配列に沿って、配列されていることを特徴とする請求項7に記載の積層構造体。
- 複数個の前記半導体装置それぞれは、前記貫通電極部及び前記放熱貫通部を、互いに接続する熱伝導配線をさらに具えていることを特徴とする請求項7又は8に記載の積層構造体。
- 前記熱伝導配線は、前記貫通電極部及び前記放熱貫通部を、互いに1対1の対応関係で接続していることを特徴とする請求項9に記載の積層構造体。
- 複数個の前記半導体装置が具える前記放熱貫通部同士を互いに接続する熱伝導用バンプをさらに具えていることを特徴とする請求項7〜10のいずれか一項に記載の積層構造体。
- 複数個の前記半導体装置同士は、前記第1及び第2主表面から露出する前記貫通電極部同士が互いに接続され、前記積層構造体の最上面から最下面に連続する一続きの貫通電極部連続体を形成して積層されていることを特徴とする請求項7〜11のいずれか一項に記載の積層構造体。
- 前記貫通電極部同士を接続する電気的接続用バンプをさらに具えていることを特徴とする請求項7〜12のいずれか一項に記載の積層構造体。
- 上面及び該上面と対向する下面を有し、当該下面を前記積層構造体の前記最上面に対向させて搭載されている放熱体をさらに具えていることを特徴とする請求項7〜13のいずれか一項に記載の積層構造体。
- 前記放熱体は、前記上面から前記下面に貫通する放熱体放熱貫通部を有し、該放熱体放熱貫通部の下端部が、前記積層構造体の前記最上面から露出する前記放熱貫通部及び前記貫通電極部のいずれか一方又は両方に接続されて設けられていることを特徴とする請求項14に記載の積層構造体。
- 前記放熱体は、前記上面から突出する突起部をさらに有していることを特徴とする請求項14又は15に記載の積層構造体。
- 請求項7〜16のいずれか一項に記載の積層構造体において、
露出面全面に、放熱を促進する液状セラミックの塗布部をさらに具えていることを特徴とする前記積層構造体。 - 前記最下面から露出する前記放熱貫通部が前記実装基板の表面に接続されて、実装基板上に搭載されていることを特徴とする請求項7〜16のいずれか一項に記載の前記積層構造体を含む実装構造体。
- 表面及び該表面と対向する裏面を有する半導体ウェハに、マトリクス状に配列された複数のチップ領域を設定し、該チップ領域に素子を作り込む工程と、
前記半導体ウェハの前記表面上に絶縁膜を形成する工程と、
前記半導体ウェハの前記チップ領域に、電気的接続用ヴィアホール及び放熱用ヴィアホールを含むヴィアホールを、前記半導体ウェハを非貫通として作り込む工程と、
前記絶縁膜上に、前記ヴィアホールを埋め込む金属膜を形成する工程と、
前記絶縁膜が露出するまで、前記金属膜を削り取って、前記電気的接続用ヴィアホールを埋め込む貫通電極部の第1頂面部及び前記放熱用ヴィアホールを埋め込む放熱貫通部の第1端面部を露出させる工程と、
前記半導体ウェハを前記裏面側から削って、前記貫通電極部の第2頂面部及び放熱貫通部の第2端面部を露出させる工程と、
前記半導体ウェハを切削して、前記チップ領域を切り出し、複数個の半導体装置として個片化する工程と
を含み、
前記貫通電極部は、前記半導体装置への入力又は出力信号の経路として機能し、
前記放熱貫通部は、前記貫通電極部の配列よりも内側の内側領域に配列されていて、
前記放熱貫通部は、前記素子と前記貫通電極部の間に設けられている
ことを特徴とする半導体装置の製造方法。 - 前記ヴィアホールを形成する工程の後に、電気的接続用ヴィアホール及び放熱用ヴィアホールを接続する溝部を前記半導体ウェハを非貫通として作り込む工程をさらに含み、
前記金属膜を形成する工程は、前記絶縁膜上に、前記ヴィアホール及び前記溝部を埋め込む金属膜を形成する工程であり、
前記貫通電極部の前記第1頂面部及び前記放熱貫通部の前記第1端面部を露出させる工程は、前記絶縁膜が露出するまで、前記金属膜を削り取って、前記溝部を埋め込む熱伝導配線をさらに形成する工程であることを特徴とする請求項19に記載の半導体装置の製造方法。 - 前記表面及び前記裏面から露出する前記貫通電極部の第1頂面部及び第2頂面部のいずれか一方又は両方上に、電気的接続用バンプを設ける工程と、
前記表面及び裏面から露出する前記放熱貫通部の第1端面部及び第2端面部のいずれか一方又は両方上に、熱伝導用バンプを設ける工程と
をさらに含むことを特徴とする請求項19又は20に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005059269A JP4688526B2 (ja) | 2005-03-03 | 2005-03-03 | 半導体装置及びその製造方法 |
US11/365,842 US7649249B2 (en) | 2005-03-03 | 2006-03-02 | Semiconductor device, stacked structure, and manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005059269A JP4688526B2 (ja) | 2005-03-03 | 2005-03-03 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006245311A JP2006245311A (ja) | 2006-09-14 |
JP4688526B2 true JP4688526B2 (ja) | 2011-05-25 |
Family
ID=36943338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005059269A Active JP4688526B2 (ja) | 2005-03-03 | 2005-03-03 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7649249B2 (ja) |
JP (1) | JP4688526B2 (ja) |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4617209B2 (ja) * | 2005-07-07 | 2011-01-19 | 株式会社豊田自動織機 | 放熱装置 |
KR100874910B1 (ko) | 2006-10-30 | 2008-12-19 | 삼성전자주식회사 | 수직형 열방출 통로를 갖는 적층형 반도체 패키지 및 그제조방법 |
DE602007013281D1 (de) | 2006-12-12 | 2011-04-28 | Nxp Bv | Verfahren zur herstellung von öffnungen in einem substrat, insbesondere von durchgangslöchern durch ein substrat |
JP4731456B2 (ja) * | 2006-12-19 | 2011-07-27 | 富士通セミコンダクター株式会社 | 半導体装置 |
WO2008108334A1 (ja) * | 2007-03-06 | 2008-09-12 | Nikon Corporation | 半導体装置及び該半導体装置の製造方法 |
KR101176187B1 (ko) * | 2007-11-21 | 2012-08-22 | 삼성전자주식회사 | 스택형 반도체 장치 및 이 장치의 직렬 경로 형성 방법 |
JP5315688B2 (ja) * | 2007-12-28 | 2013-10-16 | 株式会社ニコン | 積層型半導体装置 |
CN101499480B (zh) * | 2008-01-30 | 2013-03-20 | 松下电器产业株式会社 | 半导体芯片及半导体装置 |
KR100936070B1 (ko) * | 2008-02-26 | 2010-01-12 | 재단법인 서울테크노파크 | 웨이퍼 스택 제작 방법 |
JP2009239256A (ja) * | 2008-03-03 | 2009-10-15 | Panasonic Corp | 半導体装置及びその製造方法 |
US8022535B2 (en) | 2008-06-06 | 2011-09-20 | Coolsilicon Llc | Systems, devices, and methods for semiconductor device temperature management |
US8298914B2 (en) * | 2008-08-19 | 2012-10-30 | International Business Machines Corporation | 3D integrated circuit device fabrication using interface wafer as permanent carrier |
JP5568467B2 (ja) | 2008-08-28 | 2014-08-06 | パナソニック株式会社 | 半導体装置 |
US20100085607A1 (en) * | 2008-10-02 | 2010-04-08 | Silverbrook Research Pty Ltd | Method of encoding coding pattern |
JP5298762B2 (ja) * | 2008-10-21 | 2013-09-25 | 株式会社ニコン | 積層型半導体装置、積層型半導体装置の製造方法及び半導体基板 |
KR101046393B1 (ko) * | 2009-07-07 | 2011-07-05 | 주식회사 하이닉스반도체 | 반도체 패키지 |
US20120099274A1 (en) * | 2009-07-10 | 2012-04-26 | Coolsilicon Llc | Devices and methods providing for intra-die cooling structure reservoirs |
US10181454B2 (en) * | 2010-03-03 | 2019-01-15 | Ati Technologies Ulc | Dummy TSV to improve process uniformity and heat dissipation |
WO2011122228A1 (ja) * | 2010-03-31 | 2011-10-06 | 日本電気株式会社 | 半導体内蔵基板 |
KR101212061B1 (ko) * | 2010-06-09 | 2012-12-13 | 에스케이하이닉스 주식회사 | 반도체 칩 및 그 반도체 패키지와 이를 이용한 스택 패키지 |
US10115654B2 (en) * | 2010-06-18 | 2018-10-30 | Palo Alto Research Center Incorporated | Buried thermally conductive layers for heat extraction and shielding |
US8518746B2 (en) * | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
US8569861B2 (en) | 2010-12-22 | 2013-10-29 | Analog Devices, Inc. | Vertically integrated systems |
KR101715761B1 (ko) * | 2010-12-31 | 2017-03-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US20120248621A1 (en) * | 2011-03-31 | 2012-10-04 | S.O.I.Tec Silicon On Insulator Technologies | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods |
US8338294B2 (en) | 2011-03-31 | 2012-12-25 | Soitec | Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods |
FR2973938A1 (fr) * | 2011-04-08 | 2012-10-12 | Soitec Silicon On Insulator | Procédés de formation de structures semi-conductrices collées, et structures semi-conductrices formées par ces procédés |
US8552567B2 (en) * | 2011-07-27 | 2013-10-08 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
US8937309B2 (en) | 2011-08-08 | 2015-01-20 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
US9082633B2 (en) * | 2011-10-13 | 2015-07-14 | Xilinx, Inc. | Multi-die integrated circuit structure with heat sink |
KR20130044052A (ko) * | 2011-10-21 | 2013-05-02 | 에스케이하이닉스 주식회사 | 적층 반도체 패키지 |
US8941233B1 (en) * | 2012-02-22 | 2015-01-27 | Altera Corporation | Integrated circuit package with inter-die thermal spreader layers |
KR101941995B1 (ko) * | 2012-07-11 | 2019-01-24 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이를 갖는 적층 반도체 패키지 |
JP2014054718A (ja) | 2012-09-14 | 2014-03-27 | Seiko Epson Corp | 電子装置 |
US9196575B1 (en) * | 2013-02-04 | 2015-11-24 | Altera Corporation | Integrated circuit package with cavity in substrate |
US8907480B2 (en) * | 2013-03-14 | 2014-12-09 | Intel Mobile Communications GmbH | Chip arrangements |
US9159642B2 (en) * | 2013-04-02 | 2015-10-13 | Gerald Ho Kim | Silicon-based heat dissipation device for heat-generating devices |
JP5626400B2 (ja) * | 2013-04-22 | 2014-11-19 | 株式会社ニコン | 積層型半導体装置 |
KR102032907B1 (ko) * | 2013-04-22 | 2019-10-16 | 삼성전자주식회사 | 반도체 소자, 반도체 패키지 및 전자 시스템 |
KR101428754B1 (ko) * | 2013-05-14 | 2014-08-11 | (주)실리콘화일 | 방열 특성이 개선된 반도체 장치 |
JP2013179373A (ja) * | 2013-06-20 | 2013-09-09 | Nikon Corp | 積層型半導体装置 |
US9997494B2 (en) * | 2013-09-27 | 2018-06-12 | Gerald Ho Kim | Three-dimensional silicon structure for integrated circuits and cooling thereof |
KR102222988B1 (ko) * | 2014-09-24 | 2021-03-04 | 삼성전자주식회사 | 반도체 패키지의 멀티 적층체 |
CN107210287B (zh) * | 2015-01-13 | 2020-04-14 | 迪睿合株式会社 | 多层基板 |
WO2016114318A1 (ja) * | 2015-01-13 | 2016-07-21 | デクセリアルズ株式会社 | 多層基板 |
JP6737009B2 (ja) * | 2016-06-30 | 2020-08-05 | 株式会社デンソー | 半導体装置およびその製造方法 |
US10192843B1 (en) | 2017-07-26 | 2019-01-29 | Micron Technology, Inc. | Methods of making semiconductor device modules with increased yield |
JPWO2019078291A1 (ja) * | 2017-10-20 | 2020-11-26 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置 |
US10730743B2 (en) | 2017-11-06 | 2020-08-04 | Analog Devices Global Unlimited Company | Gas sensor packages |
US10804180B2 (en) | 2017-11-30 | 2020-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10937713B2 (en) * | 2018-06-12 | 2021-03-02 | Novatek Microelectronics Corp. | Chip on film package |
US10629512B2 (en) * | 2018-06-29 | 2020-04-21 | Xilinx, Inc. | Integrated circuit die with in-chip heat sink |
US11469360B2 (en) * | 2019-05-13 | 2022-10-11 | Innolux Corporation | Electronic device |
CN111935946B (zh) * | 2019-05-13 | 2023-07-04 | 群创光电股份有限公司 | 电子装置 |
KR20200140654A (ko) | 2019-06-07 | 2020-12-16 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US11587839B2 (en) | 2019-06-27 | 2023-02-21 | Analog Devices, Inc. | Device with chemical reaction chamber |
US11495506B2 (en) * | 2020-03-30 | 2022-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with separate electric and thermal paths |
CN116759403A (zh) * | 2022-03-03 | 2023-09-15 | 长鑫存储技术有限公司 | 一种半导体结构 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223833A (ja) * | 1996-12-02 | 1998-08-21 | Toshiba Corp | マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップおよびその形成方法 |
JPH11345933A (ja) * | 1998-06-01 | 1999-12-14 | Toshiba Corp | マルチチップ半導体装置およびその製造方法 |
JP2001085603A (ja) * | 1999-09-13 | 2001-03-30 | Toshiba Corp | 半導体装置 |
JP2001156247A (ja) * | 1999-11-25 | 2001-06-08 | Seiko Epson Corp | 半導体装置 |
JP2003197855A (ja) * | 2001-12-27 | 2003-07-11 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2005244143A (ja) * | 2004-03-01 | 2005-09-08 | Hitachi Ltd | 半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6492719B2 (en) * | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
JP3920399B2 (ja) * | 1997-04-25 | 2007-05-30 | 株式会社東芝 | マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置 |
JP2001077301A (ja) * | 1999-08-24 | 2001-03-23 | Amkor Technology Korea Inc | 半導体パッケージ及びその製造方法 |
KR100391093B1 (ko) * | 2001-01-04 | 2003-07-12 | 삼성전자주식회사 | 히트 싱크가 부착된 볼 그리드 어레이 패키지 |
TW200302685A (en) * | 2002-01-23 | 2003-08-01 | Matsushita Electric Ind Co Ltd | Circuit component built-in module and method of manufacturing the same |
US6852627B2 (en) * | 2003-03-05 | 2005-02-08 | Micron Technology, Inc. | Conductive through wafer vias |
TW200504895A (en) * | 2003-06-04 | 2005-02-01 | Renesas Tech Corp | Semiconductor device |
KR100674907B1 (ko) * | 2003-11-26 | 2007-01-26 | 삼성전자주식회사 | 고신뢰성을 갖는 스택형 반도체 패키지 |
US7122891B2 (en) * | 2003-12-23 | 2006-10-17 | Intel Corporation | Ceramic embedded wireless antenna |
-
2005
- 2005-03-03 JP JP2005059269A patent/JP4688526B2/ja active Active
-
2006
- 2006-03-02 US US11/365,842 patent/US7649249B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223833A (ja) * | 1996-12-02 | 1998-08-21 | Toshiba Corp | マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップおよびその形成方法 |
JPH11345933A (ja) * | 1998-06-01 | 1999-12-14 | Toshiba Corp | マルチチップ半導体装置およびその製造方法 |
JP2001085603A (ja) * | 1999-09-13 | 2001-03-30 | Toshiba Corp | 半導体装置 |
JP2001156247A (ja) * | 1999-11-25 | 2001-06-08 | Seiko Epson Corp | 半導体装置 |
JP2003197855A (ja) * | 2001-12-27 | 2003-07-11 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2005244143A (ja) * | 2004-03-01 | 2005-09-08 | Hitachi Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US7649249B2 (en) | 2010-01-19 |
JP2006245311A (ja) | 2006-09-14 |
US20060197181A1 (en) | 2006-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4688526B2 (ja) | 半導体装置及びその製造方法 | |
US7772692B2 (en) | Semiconductor device with cooling member | |
US8441121B2 (en) | Package carrier and manufacturing method thereof | |
EP2023699A2 (en) | Heat radiation package and semiconductor device | |
JP6286477B2 (ja) | パッケージキャリアおよびその製造方法 | |
JP2006210777A (ja) | 半導体装置 | |
JP2007533082A (ja) | 光取出しが改善された発光ダイオード・アレイ | |
EP2224484A1 (en) | Semiconductor module | |
US8716830B2 (en) | Thermally efficient integrated circuit package | |
JP2006245226A (ja) | 半導体装置及びその製造方法 | |
WO2018168591A1 (ja) | モジュール | |
US7298028B2 (en) | Printed circuit board for thermal dissipation and electronic device using the same | |
JP2019071412A (ja) | チップパッケージ | |
JP2009188376A (ja) | 半導体装置とその製造方法 | |
JP2006295119A (ja) | 積層型半導体装置 | |
TWI269414B (en) | Package substrate with improved structure for thermal dissipation and electronic device using the same | |
JP3650689B2 (ja) | 半導体装置 | |
JP2008235576A (ja) | 電子部品の放熱構造及び半導体装置 | |
US8648478B2 (en) | Flexible heat sink having ventilation ports and semiconductor package including the same | |
JP2007115894A (ja) | 半導体装置 | |
JP2009176839A (ja) | 半導体素子の放熱構造 | |
JP4047819B2 (ja) | Bgaハンダ・ボールによる相互接続部およびその作製方法 | |
JP2007281201A (ja) | 半導体装置 | |
JP2018085495A (ja) | 発光素子用基板、発光素子モジュールおよび発光装置 | |
JP5092274B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070808 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080130 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081203 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090210 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100810 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101012 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101102 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101227 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110125 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110215 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4688526 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140225 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |